Patents Examined by Alia Sabur
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Patent number: 12211861Abstract: Various embodiments of the present disclosure are directed towards a method for forming a pixel sensor. The method comprises forming a photodetector in a substrate. The substrate is patterned to define an opening above the photodetector. A gate electrode is formed within the opening, where the gate electrode has a top conductive body overlying a bottom conductive body. A first segment of a sidewall of the top conductive body contacts the bottom conductive body. A floating diffusion node is formed in the substrate laterally adjacent to the gate electrode. A second segment of the sidewall of the top conductive body overlies the floating diffusion node.Type: GrantFiled: June 17, 2021Date of Patent: January 28, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Seiji Takahashi
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Patent number: 12211847Abstract: A semiconductor device may include a substrate including first and second active regions and a field region therebetween, first and second active patterns respectively provided on the first and second active regions, first and second source/drain patterns respectively provided on the first and second active patterns, a first channel pattern between the first source/drain patterns and a second channel pattern between the second source/drain patterns, and a gate electrode extended from the first channel pattern to the second channel pattern to cross the field region. Each of the first and second channel patterns may include semiconductor patterns, which are stacked to be spaced apart from each other. A width of a lower portion of the gate electrode on the field region may decrease with decreasing distance from a top surface of the substrate.Type: GrantFiled: July 22, 2021Date of Patent: January 28, 2025Assignee: Samsung Electronics Co., Ltd.Inventors: Jaehoon Shin, Bongseok Suh, Daewon Kim, Sukhyung Park, Junggun You, Jaeyun Lee
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Patent number: 12211916Abstract: Example embodiments relate to a field-effect transistors having improved layouts. One example field-effect transistor includes a semiconductor substrate on which at least one transistor cell array is arranged. Each transistor cell includes a first transistor cell unit. Each first transistor cell unit includes a plurality of gate fingers, a main gate finger segment, a plurality of drain fingers, and a main drain finger segment. Each first transistor cell unit also includes a main gate finger base connected to the main gate finger segment of the first transistor cell unit and extending from that main gate finger segment towards the main drain finger segment of that first transistor cell unit. Further, each first transistor cell unit includes a main drain finger base connected to the main drain finger segment of that first transistor cell and extending from that main drain finger segment towards that main gate finger segment.Type: GrantFiled: October 30, 2020Date of Patent: January 28, 2025Assignee: Ampleon Netherlands B.V.Inventor: Patrick Valk
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Patent number: 12199104Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.Type: GrantFiled: March 19, 2021Date of Patent: January 14, 2025Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Atsushi Hirose, Masashi Tsubuku, Kosei Noda
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Patent number: 12200930Abstract: A semiconductor device includes: a substrate that includes a first region and a second region; gate electrodes stacked on the first region in a first direction, extend by different lengths in a second direction on the second region, and respectively including a pad region having an upper surface that is upwardly exposed in the second region; interlayer insulating layers alternately stacked with the gate electrodes; channel structures that extend in the first direction and penetrate through the gate electrodes; plug insulating layers alternately disposed with the interlayer insulating layers and parallel to the gate electrodes below the pad region; and contact plugs that extend in the first direction and respectively penetrate through the pad region and the plug insulating layers below the pad region. In each of the gate electrodes, the pad region has physical properties that differ from physical properties of regions other than the pad region.Type: GrantFiled: September 2, 2021Date of Patent: January 14, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seungmin Lee, Junhyoung Kim, Kangmin Kim, Byungkwan You
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Patent number: 12200954Abstract: According to one embodiment, a display device includes a base material, a first insulating layer disposed on the substrate, a first electrode disposed on the first insulating layer, an organic layer disposed on the first electrode, a second electrode disposed on the organic layer, a second insulating layer disposed on the first insulating layer and including an opening portion overlapping with the second electrode, and a third electrode covering the second electrode and the second insulating layer. The first electrode, the organic layer, and the second electrode are separated for each pixel.Type: GrantFiled: January 27, 2022Date of Patent: January 14, 2025Assignee: Japan Display Inc.Inventor: Hideyuki Takahashi
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Patent number: 12185534Abstract: An integrated circuit device includes a substrate, a peripheral wiring circuit that includes a bypass via and is disposed on the substrate, a peripheral circuit that includes an interlayer insulating layer surrounding at least a portion of the peripheral wiring circuit, and a memory cell array disposed on and overlapping the peripheral circuit. The memory cell array includes a base substrate, a plurality of gate lines disposed on the base substrate, and a plurality of channels penetrating the plurality of gate lines. The integrated circuit device further includes a barrier layer interposed between the peripheral circuit and the memory cell array. The barrier layer includes a bypass hole penetrating from a top surface to a lower surface of the barrier layer. The bypass via is disposed in the bypass hole.Type: GrantFiled: February 1, 2022Date of Patent: December 31, 2024Inventors: Junhyoung Kim, Byunggon Park, Seungmin Lee, Kangmin Kim, Taemin Eom, Byungkwan You
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Patent number: 12166102Abstract: A nitride-based semiconductor device includes a substrate, a buffer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a S/D electrode, a second S/D electrode, and a gate electrode. The buffer is disposed over the substrate and includes at least one layer of a nitride-based semiconductor compound doped with an acceptor at a top-most portion of the buffer. The first and second nitride-based semiconductor layers are disposed over the buffer. The first S/D electrode is disposed over the second nitride-based semiconductor layer, in which the first S/D electrode extends downward to a position lower than the first nitride-based semiconductor layer, so as to form at least one first interface with the top-most portion of the buffer, making contact with the at least one layer of the nitride-based semiconductor compound. The second S/D electrode and the gate electrode are disposed over the second nitride-based semiconductor layer.Type: GrantFiled: December 18, 2020Date of Patent: December 10, 2024Assignee: INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.Inventors: Ronghui Hao, Fu Chen, Chuan He, King Yuen Wong
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Patent number: 12166133Abstract: A semiconductor structure includes: a substrate; a gate structure located on the substrate, wherein the gate structure comprises a first conductive layer, a barrier layer and a second conductive layer which are stacked in sequence; wherein the first conductive layer includes a first polysilicon layer, a first metal layer and a second polysilicon layer, wherein the first polysilicon layer is adjacent to the substrate and the second polysilicon layer is contiguous to the barrier layer; and wherein the first metal layer is located between the first polysilicon layer and the second polysilicon layer. The gate structure of the embodiments of the application has a straight profile and an excellent electrical performance.Type: GrantFiled: November 25, 2021Date of Patent: December 10, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Qiang Long
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Patent number: 12161053Abstract: A superconducting quantum hybrid system includes: a silicon carbide (SiC) epitaxial layer; and a superconducting qubit line, the superconducting qubit line corresponding to a superconducting qubit, where a designated region of the SiC epitaxial layer includes a nitrogen vacancy (NV) center, the NV center being formed by implanting nitrogen ions into the designated region of the SiC epitaxial layer, and where the superconducting qubit line is located on a surface of the SiC epitaxial layer, the superconducting qubit is coupled to a solid-state defect qubit, and the solid-state defect qubit is a qubit corresponding to the NV center in the designated region.Type: GrantFiled: February 3, 2022Date of Patent: December 3, 2024Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITEDInventors: Yu Zhou, Zhenxing Zhang, Sainan Huai, Yarui Zheng, Shengyu Zhang
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Patent number: 12140557Abstract: A method for manufacturing a sensor includes etching an insulator layer disposed over a substrate to define an opening exposing a sensor surface of a sensor disposed on the substrate, a native oxide forming on the sensor surface; sputtering the sensor surface with a noble gas to at least partially remove the native oxide from the sensor surface; and annealing the sensor surface in a hydrogen atmosphere.Type: GrantFiled: August 16, 2019Date of Patent: November 12, 2024Assignee: LIFE TECHNOLOGIES CORPORATIONInventors: Phil Waggoner, Jordan Owens, Scott Parker
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Patent number: 12137567Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a substrate, an alternating layer stack including a staircase structure on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes an alternating dielectric stack and an alternating conductor/dielectric stack. The alternating dielectric stack includes dielectric layer pairs enclosed by at least the barrier structure. The alternating conductor/dielectric stack includes conductor/dielectric layer pairs. The memory device further includes a channel structure and a slit structure each extending vertically through the alternating conductor/dielectric stack, an etch stop layer on an end of the channel structure, and first contacts.Type: GrantFiled: October 26, 2020Date of Patent: November 5, 2024Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Lidong Song, Yongna Li, Feng Pan, Steve Weiyi Yang, Wenguang Shi
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Patent number: 12125940Abstract: A semiconductor heterostructure for an optoelectronic device with improved light emission is disclosed. The heterostructure can include a first semiconductor layer having a first index of refraction n1. A second semiconductor layer can be located over the first semiconductor layer. The second semiconductor layer can include a laminate of semiconductor sublayers having an effective index of refraction n2. A third semiconductor layer having a third index of refraction n3 can be located over the second semiconductor layer. The first index of refraction n1 is greater than the second index of refraction n2, which is greater than the third index of refraction n3.Type: GrantFiled: July 12, 2021Date of Patent: October 22, 2024Assignee: Sensor Electronic Technology, Inc.Inventors: Maxim S. Shatalov, Alexander Dobrinsky
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Patent number: 12119359Abstract: An imaging device according to an embodiment of the present disclosure includes: a first substrate including, in a first semiconductor substrate, a sensor pixel that performs photoelectric conversion; a second substrate including, in a second semiconductor substrate, a readout circuit that outputs a pixel signal based on charges outputted from the sensor pixel, in which the second substrate is stacked on the first substrate; and a first hydrogen diffusion prevention layer provided between the first semiconductor substrate and the second semiconductor substrate.Type: GrantFiled: December 6, 2019Date of Patent: October 15, 2024Assignee: Sony Semiconductor Solutions CorporationInventor: Koichi Baba
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Patent number: 12107130Abstract: A semiconductor device includes a semiconductor substrate having a first dopant and a second dopant. A covalent atomic radius of a material of the semiconductor substrate is i) larger than a covalent atomic radius of the first dopant and smaller than a covalent atomic radius of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than the covalent atomic radius of the second dopant. The semiconductor device further includes a semiconductor layer on the semiconductor substrate and semiconductor device elements in the semiconductor layer. A vertical concentration profile of the first dopant decreases along at least 80% of a distance between an interface of the semiconductor substrate and the semiconductor layer to a surface of the semiconductor substrate opposite to the interface.Type: GrantFiled: April 21, 2021Date of Patent: October 1, 2024Assignee: Infineon Technologies AGInventors: Ingo Muri, Johannes Konrad Baumgartl, Oliver Hellmund, Jacob Tillmann Ludwig, Iris Moder, Thomas Neidhart, Gerhard Schmidt, Hans-Joachim Schulze
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Patent number: 12096632Abstract: Two types of support pillar structures are formed in a staircase region of an alternating stack of insulating layers and sacrificial material layers. First-type support pillar structures are formed in areas distal from backside trenches to be subsequently formed, and second-type support pillar structures may be formed in areas proximal to the backside trenches. The second-type support pillar structures may be formed as dielectric support pillar structures, or may be formed with at least one additional dielectric spacer.Type: GrantFiled: April 29, 2021Date of Patent: September 17, 2024Assignee: SANDISK TECHNOLOGIES LLCInventors: Koichi Matsuno, Johann Alsmeier
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Patent number: 12080596Abstract: A semiconductor structure and a forming method thereof are provided, and the forming method includes: providing a base; forming, on the base, a plurality of conductive function layers extending in a first direction and sequentially arranged in a second direction, a bottom dielectric layer located on the base between the conductive function layers, and a blocking structure located in the conductive function layer, the blocking structure segmenting the conductive function layers located on two sides of the blocking structure in the first direction; forming a top dielectric layer covering the bottom dielectric layer, the conductive function layers, and the blocking structure; etching the top dielectric layer located above a junction of the blocking structure and the conductive function layer and a part of the blocking structure located at a side wall of the conductive function layer, to form a via running through the top dielectric layer and exposing a part of a top and a part of a side wall of the conductive fuType: GrantFiled: April 6, 2021Date of Patent: September 3, 2024Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Jisong Jin, Abraham Yoo
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Patent number: 12080593Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.Type: GrantFiled: July 7, 2022Date of Patent: September 3, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Ping Chen, Ming-Han Lee, Shin-Yi Yang, Yung-Hsu Wu, Chia-Tien Wu, Shau-Lin Shue, Min Cao
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Patent number: 12082417Abstract: A 3-dimensional (3D) flash memory having a structure that mitigates an interference phenomenon between neighboring cells in an oxide-nitride-oxide (ONO) layer, which is a charge storage layer, and a method of manufacturing the same are provided.Type: GrantFiled: January 23, 2020Date of Patent: September 3, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Yun Heub Song
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Patent number: 12069898Abstract: The present disclosure provides a display panel, a manufacturing method thereof and a display device. The display panel includes a base substrate, a TFT array, a pixel definition layer, and a plurality of light-emitting units. The display panel further includes a plurality of spacers arranged on a surface of the pixel definition layer away from the base substrate, the plurality of spacers is formed integrally with the pixel definition layer, a surface of each spacer away from the base substrate includes a first portion and a second portion, a distance between the second portion and the base substrate is smaller than a distance between the first portion and the base substrate, and a ratio of a sum of areas of the first portions of the plurality of spacers to an area of a display region of the display panel is not smaller than a preset threshold.Type: GrantFiled: September 22, 2020Date of Patent: August 20, 2024Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Qun Ma, Yue Wei, Mingxi Pan, Haoming Lv