Patents Examined by Alia Sabur
  • Patent number: 10895800
    Abstract: A segmented light or optical power emitting device and an illumination device are described. The segmented device includes a die having a light or optical power emitting semiconductor structure that includes an active layer disposed between an n-layer and a p-layer. Trenches are formed in at least the semiconductor structure and separate the die into individually addressable segments. The active layer emits light or optical power having a first color point or spectrum. At least one wavelength converting layer is adjacent the die and converts the light or optical power to light or optical power having at least one second color point or spectrum and limits an energy ratio of the pump light or optical power that passes through the at least one wavelength converting layer unconverted to total light or optical power emitted by the light or optical power emitting device to less than 10%.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: January 19, 2021
    Assignee: Lumileds LLC
    Inventors: Arjen Gerben Van Der Sijde, Quint Van Voorst Vader, Nicola Pfeffer
  • Patent number: 10886320
    Abstract: An image-sensor device includes a substrate including a pixel region and a logic region. A logic transistor is disposed in the logic region and is surrounded by a logic isolation feature. A radiation-sensing region is disposed in the pixel region of the substrate. An epitaxial pixel isolation feature is disposed in the pixel region and surrounds the radiation-sensing region. A doped region with a same doping polarity as the radiation-sensing region is located between a bottom of the radiation-sensing region and the back surface of the substrate. The epitaxial pixel isolation feature is in direct contact with the doped region. The doped region extends continuously under the pixel region and the logic region. The epitaxial pixel isolation feature is in direct contact with the doped region, and the logic isolation feature is spaced apart from the doped region.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: January 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-I Hsu, Feng-Chi Hung, Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu
  • Patent number: 10870151
    Abstract: A sealing structure with a surface of a base material with a through-hole, an underlying metal film, and a sealing member bonded to the underlying metal film to seal the through-hole. The sealing member includes a compressed product of a metal powder including gold having a purity of 99.9% by mass or more and a lid-like metal film including a bulk-like metal including gold and having a thickness of not less than 0.01 ?m and not more than 5 ?m. The sealing material includes an outer periphery-side densified region in contact with an underlying metal film and a center-side porous region in contact with the through-hole. The shape of pores in the densified region is specified, and the horizontal length (l) of a pore in the radial direction at any cross-section of the densified region and the width (W) of the densified region satisfy the relationship of l?0.1W.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: December 22, 2020
    Assignee: TANAKA KIKINZOKU KOGYO K.K.
    Inventors: Toshinori Ogashiwa, Yuya Sasaki, Masayuki Miyairi, Kenichi Inoue
  • Patent number: 10872837
    Abstract: The present disclosure relates to an air-cavity semiconductor package, which includes a thermal carrier, a ring structure, a package lid, and at least one semiconductor device. The thermal carrier has a carrier body, a heat slug residing within the carrier body, a top coating layer formed over a top surface of the heat slug, and a bottom coating layer formed over a bottom surface of the heat slug. The ring structure includes a ring body with an interior opening, which resides over the thermal carrier, such that a portion of a top surface of the thermal carrier is exposed through the interior opening. The package lid resides over the ring structure and has a recess conjoined with the interior opening forming an enclosed cavity. The at least one semiconductor device is attached to the exposed portion of the top surface of the thermal carrier and encapsulated in the enclosed cavity.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: December 22, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Robert Charles Dry, Christine Blair
  • Patent number: 10867898
    Abstract: An electroconductive substrate, including: a base material; a foundation layer disposed on the base material; a trench formation layer disposed on the foundation layer, and an electroconductive pattern layer including metal plating. A trench including a bottom surface to which the foundation layer is exposed, is formed. The trench is filled with the electroconductive pattern layer. The foundation layer includes a mixed region which is formed from a surface of the foundation layer on the electroconductive pattern layer side towards the inside thereof, and contains metal particles which contain a metal configuring the electroconductive pattern layer, and enter the foundation layer.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: December 15, 2020
    Assignee: TDK CORPORATION
    Inventors: Takashi Daitoku, Susumu Taniguchi, Akiko Seki, Atsushi Sato, Yuhei Horikawa, Makoto Orikasa, Hisayuki Abe
  • Patent number: 10867925
    Abstract: A method for forming a chip package structure is provided. The method includes forming a first redistribution structure over a first carrier substrate. The method includes bonding a chip structure to the first surface through a first conductive bump. The method includes forming a first molding layer over the first redistribution structure. The method includes removing the first carrier substrate. The method includes forming a second conductive bump over the second surface. The method includes forming a second redistribution structure over a second carrier substrate. The method includes bonding the first redistribution structure to the third surface. The method includes forming a second molding layer over the second redistribution structure. The method includes removing the second carrier substrate. The method includes removing a portion of the second redistribution structure from the fourth surface. The method includes forming a third conductive bump over the fourth surface.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shin-Puu Jeng, Shuo-Mao Chen, Feng-Cheng Hsu, Po-Yao Lin
  • Patent number: 10861868
    Abstract: Embodiments of 3D memory devices with a structurally-reinforced semiconductor plug and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack is formed on a substrate. The dielectric stack includes a plurality of interleaved dielectric layers and sacrificial layers. An opening extending vertically through the dielectric stack is formed. A shallow recess is formed by removing a part of a sacrificial layer abutting a sidewall of the opening. The sacrificial layer is at a lower portion of the dielectric stack. A semiconductor plug is formed at a lower portion of the opening. A part of the semiconductor plug protrudes into the shallow recess. A channel structure is formed above and in contact with the semiconductor plug in the opening. A memory stack including a plurality of conductor/dielectric layer pairs is formed by replacing, with a plurality of conductor layers, the sacrificial layers in the dielectric stack.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: December 8, 2020
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Yangbo Jiang, Liang Hui Wu, Ya Jun Wang, Jingping Zhang
  • Patent number: 10832957
    Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor is a grading strained stressor including multiple graded portions formed at graded depths. The first stressor is configured to create one of a graded compressive stress or a graded tensile stress.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: November 10, 2020
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Che-Wei Yang, Hao-Hsiung Lin, Samuel C. Pan
  • Patent number: 10818565
    Abstract: A circuit board includes: a ceramic substrate that has a first surface and a second surface; a first metal part that has a first metal plate joined to the first surface and a protrusion projecting from a front surface of the first metal plate; and a second metal part that has a second metal plate joined to the second surface. When the ceramic substrate is equally divided into first to third sections along a longer side direction, V1, V2, V3, V4, V5, and V6 are numbers satisfying formula V4/V1+V6/V3?2(V5/V2), 0.5?V4/V1?2, 0.5?V5/V2?2, and 0.5?V6/V3?2.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: October 27, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD.
    Inventors: Hiromasa Kato, Takashi Sano
  • Patent number: 10819085
    Abstract: A ridge structure (9) having a ridge lower part (6), a ridge upper part (8) above the ridge lower part (6) and having a larger width than the ridge lower part (6), is formed on a semiconductor substrate (1). A recess (11) of the ridge structure (9), where the ridge lower part (6) is laterally set back from the ridge upper part (8) due to a difference in width between the ridge upper part (8) and the ridge lower part t (6), is completely filled with an insulating film (10) by an atomic layer deposition method to form a protrusion (19) from the semiconductor substrate (1), the ridge structure (9), and the insulating film (10) without any step in a side face of the protrusion (19).
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: October 27, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Tsutomu Yamaguchi
  • Patent number: 10818518
    Abstract: A plurality of surface mounting components are arranged on a component mounting surface of a transfer substrate. A resin layer is formed on the transfer substrate and the plurality of surface mounting components are buried in the resin layer. The resin layer is peeled off the transfer substrate, with the plurality of surface mounting components buried in the resin layer, to expose a surface resin layer. An intermediate auxiliary layer is provided on the exposed surface of the resin layer. The intermediate auxiliary layer has openings to expose respective mounting terminals of the surface mounting component. Metal materials are arranged in the openings. A wiring sheet which includes a thermoplastic resin sheet with an electrode pattern and a plurality of unmetallized via patterns is joined to the intermediate auxiliary layer so that each of the via patterns aligns with a respective one of the openings in the intermediate auxiliary layer.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: October 27, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Noboru Kato
  • Patent number: 10804287
    Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a plurality of channel holes penetrating the alternating dielectric stack; forming a channel structure in each channel hole; forming a channel column structure on the channel structure in each channel hole; trimming an upper portion of each channel column structure to form a channel plug; and forming a top selective gate cut between neighboring channel plugs.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: October 13, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Yu Ru Huang, Qian Tao, Yushi Hu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Yongna Li, Lidong Song
  • Patent number: 10804416
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to graphene detectors integrated with optical waveguide structures and methods of manufacture. The structure includes a plurality of non-planar fin structures composed of substrate material, and a non-planar sheet of graphene material extending entirely over each of the plurality of non-planar fin structures.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: October 13, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Ajey P. Jacob
  • Patent number: 10804306
    Abstract: A solid-state imaging device having flat microlenses is provided. The solid-state imaging device includes a semiconductor substrate having a plurality of photoelectric conversion elements. The solid-state imaging device further includes a color filter layer disposed above the semiconductor substrate. The solid-state imaging device also includes a microlens having a flat top surface disposed on the color filter layer. The flat top surface of the microlens is directly above the photoelectric conversion element, and the area of the flat top surface of the microlens is equal to the area of the photoelectric conversion element.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: October 13, 2020
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventors: Tzu-Wei Huang, Ji-Hong Lin, Huang-Jen Chen
  • Patent number: 10797068
    Abstract: Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: October 6, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon-Sung Lim, Jang-Gn Yun, Jaesun Yun
  • Patent number: 10797166
    Abstract: A manufacturing method for an IGZO active layer is disclosed. The method comprises steps of: after depositing a first metal layer and a gate insulation layer on a substrate, depositing an IGZO material on the gate insulation layer, and forming an IGZO film; and performing a plasma cleaning treatment on a surface of the IGZO film by using an argon gas or a helium gas to adjust element contents on the surface of the IGZO film, and forming an IGZO active layer. The present invention also correspondingly discloses a manufacturing method for an oxide thin film transistor. By implementing the embodiments of the present invention, the elements on the film surface of the IGZO active layer can be adjusted to improve electrical properties.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: October 6, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Yue Wu, Wei Wu
  • Patent number: 10796904
    Abstract: A conductive C-plane GaN substrate has a resistivity of 2×10?2 ?·cm or less or an n-type carrier concentration of 1×1018 cm?3 or more at room temperature. At least one virtual line segment with a length of 40 mm can be drawn at least on one main surface of the substrate. The line segment satisfies at least one of the following conditions (A1) and (B1): (A1) when an XRC of (004) reflection is measured at 1 mm intervals on the line segment, a maximum value of XRC-FWHMs across all measurement points is less than 30 arcsec; and (B1) when an XRC of the (004) reflection is measured at 1 mm intervals on the line segment, a difference between maximum and minimum values of XRC peak angles across all the measurement points is less than 0.2°.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: October 6, 2020
    Assignee: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Yutaka Mikawa, Hideo Fujisawa, Tae Mochizuki, Hideo Namita, Shinichiro Kawabata
  • Patent number: 10790150
    Abstract: A method for fabricating a semiconductor device includes: preparing a substrate; forming an isolation layer defining an active region in the substrate; forming a first insulation structure over the substrate, the first insulation structure defining a line-type opening that exposes the isolation layer and the active region; forming a plug pad through a Selective Epitaxial Growth (SEG) process over the exposed active regions; forming a second insulation structure inside the line-type opening, the second insulation structure defining a contact hole landing on the plug pad; and filling the contact hole with a contact plug.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: September 29, 2020
    Assignee: SK hynix Inc.
    Inventors: Oh-Hyun Kim, Sung-Hwan Ahn, Hae-Jung Park, Tae-Hang Ahn
  • Patent number: 10784319
    Abstract: An organic EL element including light emitting layers is formed above a first region of a main surface of a back film. A plurality of terminal portions are formed above a second region of the main surface of the back film. A cover film including an opening is provided as an uppermost layer above the main surface of the back film.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: September 22, 2020
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tetsunori Tanaka, Shoji Okazaki, Yuki Yasuda
  • Patent number: 10782581
    Abstract: A display device including a curved display surface. The display device comprises a first substrate bent in a first direction, a second substrate that is bent in the first direction, spacers disposed between the first substrate and the second substrate; and bases holding the spacers. The first substrate includes data lines and gate lines, the bases includes: a central base disposed on around a center in the first direction of the display surface; an end base disposed on around an end in the first direction of the display surface; and intermediate bases disposed between the central base and the end base in the first direction, and a width in the first direction of one of intermediate bases is larger than a width in the first direction of the central base.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: September 22, 2020
    Assignee: Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Masafumi Hirata, Hiroaki Goto