Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a fin extending from a substrate. A dummy gate is formed over the fin. The dummy gate extends along sidewalls and a top surface of the fin. The dummy gate is removed to form a recess. A replacement gate is formed in the recess. Forming the replacement gate includes forming an interfacial layer along sidewalls and a bottom of the recess. A dipole layer is formed over the interfacial layer. The dipole layer includes metal atoms. Fluorine atoms are incorporated in the dipole layer. The fluorine atoms and the metal atoms are driven from the dipole layer into the interfacial layer. The dipole layer is removed.

Abstract: The present disclosure is directed to a package that includes a transparent layer that is on and covers a sensor of a die as well as a plurality of electrical connections that extend from a first surface of the package to the second surface of the package opposite to the first surface. In at least one embodiment of a package, the electrical connections each include a conductive structure that extends through the transparent layer to a first side of a corresponding contact pad of the die, and at least one electrical that extends into the second surface of the die to a second side of the corresponding contact pad that is opposite to the first side. In at least another embodiment of a package, the electrical connections include a conductive structure that extends through a molding compound to a first side of a corresponding contact pad of the die, and at least one electrical via that extends into the second surface of the die to a second side of the corresponding contact pad opposite to the first side.

Abstract: A method of forming a semiconductor device includes the following steps. A metal layer with at least one silicon-containing pattern therein is provided. A first wet etching process is performed by using a first etching solution, to clean a surface of the metal layer, wherein the first etching solution contains a base and a first oxidant. At least one cycle is performed. Each cycle includes a second wet etching process and a cleaning process. The second wet etching process is performed by using a second etching solution, to remove the metal layer, wherein the second etching solution contains an acid and a second oxidant. A cleaning process is performed.

Abstract: A semiconductor package having a package substrate including an upper surface, a controller, a first die stack, and a second die stack. The controller, the first die stack, and the second die stack are at the upper surface. The first die stack includes a first shingled sub-stack and a first reverse-shingled sub-stack. The first die stack also includes a first bridging chip between the first shingled and reverse-shingled sub-stacks. The second die stack similarly includes a second shingled sub-stack and a second reverse-shingled sub-stack. The second die stack also includes a second bridging chip bonded to the top of the second reverse-shingled sub-stack. At least a portion of a bottom semiconductor die of the first reverse-shingled sub-stack is vertically aligned with a semiconductor die of the second shingled sub-stack and a semiconductor die of the second reverse-shingled sub-stack.

Abstract: A light-emitting diode (LED) die can include a p-n junction between a p-doped semiconductor material and an n-doped semiconductor material. The LED die can include vias that can electrically power the p-n junction. The vias can optionally be electrically connected in parallel to one another. A controller can supply current to the vias to electrically power the LED die. The vias can be distributed with a density that peaks at or near a center of the LED die and decreases with increasing distances away from the peak of the density, such that when the vias are electrically powered, the LED die emits light with a surface luminance that peaks at or near the center of the LED die and decreases with increasing distances away from the peak of the surface luminance.

Abstract: The disclosure concerns an electronic device comprising, stacked from a first surface to a second surface, a first stack and a second stack of two high electron mobility transistors, referred to as first and second transistor, the first and the second stack each comprising, from an insulating layer, interposed between the first and the second stack, a barrier layer and a channel layer, the first and the second transistor respectively comprising a first and a second set of electrodes, the first and the second set of electrodes being each provided with a source electrode, with a drain electrode, and with a gate electrode which are arranged so that the first and the second transistor form a half-arm of a bridge.

Abstract: A display substrate, a method for manufacturing the display substrate and a display device are provided in this disclosure. The display substrate includes a substrate film layer and functional film layers, the display substrate includes a display region and a hole-forming region, and the method includes: forming a plurality of functional film layers on the substrate film layer; etching at least one of the functional film layers in the hole-forming region to form a first via-hole penetrating the at least one of the functional film layers; forming a transition layer that covers the display region and reveals the first via-hole; forming a second via-hole in the hole-forming region by using the transition layer as a mask, the second via-hole penetrating the substrate film layer and all the functional film layers apart from the at least one of the functional film layers; and removing the transition layer.

Abstract: A display device includes: a substrate; a display element on the substrate; a capping layer on the display element; a first auxiliary layer on the capping layer; and a thin-film encapsulation layer on the first auxiliary layer, wherein the thin-film encapsulation layer comprises a (1-1)-th inorganic encapsulation layer on the first auxiliary layer and a (1-2)-th inorganic encapsulation layer on the (1-1)-th inorganic encapsulation layer, wherein a refractive index of the first auxiliary layer is smaller than a refractive index of the capping layer and a refractive index of the (1-1)-th inorganic encapsulation layer, and a refractive index of the (1-2)-th inorganic encapsulation layer is smaller than the refractive index of the (1-1)-th inorganic encapsulation layer.

Abstract: A modular electronic structure includes a first chip having a first interleaved portion and a first electromagnetic coupler on the first interleaved portion. There is a second chip having a second interleaved portion and a second electromagnetic coupler on the second interleaved portion and configured to electromagnetically couple with the first electromagnetic coupler. The first interleaved portion fits between two surfaces of the second chip. The second interleaved portion fits between two surfaces of the first chip.

Abstract: An optoelectronic semiconductor component includes a semiconductor body having a main emission surface and an active region arranged to emit electromagnetic radiation. The optoelectronic semiconductor component also includes a receiving element arranged on the side of the semiconductor body opposite to the main emission surface. The optoelectronic semiconductor component also includes a radiation-transmissive molding compound. The radiation-transmissive molding compound completely surrounds the semiconductor body and the receiving element. A receiver frequency is assigned to the receiving element. The receiving element is configured to extract energy for operating the active region from an alternating electromagnetic field.

Abstract: A device includes a first source/drain region including: a first metal layer including a first metal; and a conductive two-dimensional material on the first metal layer; an isolation layer physically contacting a sidewall of the first metal layer, wherein the conductive two-dimensional material protrudes above the isolation layer; a two-dimensional semiconductor material on the isolation layer, wherein a sidewall of the two-dimensional semiconductor material physically contacts a sidewall of the conductive two-dimensional material; and a gate stack on the two-dimensional semiconductor material.

Abstract: To manufacture a semiconductor device, a structure is formed by alternately stacking a plurality of first films and a plurality of second films one-by-one on a substrate. A vertical hole is formed to vertically pass through the structure. A carbon-containing barrier film is formed to conformally cover an inner sidewall of the vertical hole. The carbon-containing barrier film is in contact with portions of the plurality of first films and the plurality of second films. A sacrificial metal film is formed on the carbon-containing barrier film in the vertical hole. The sacrificial metal film is removed to expose the carbon-containing barrier film. The carbon-containing barrier film is removed using an ashing process.

Abstract: Discussed are a display device and a method for manufacturing the same, in which a source electrode and a drain electrode are disposed under an active layer of a thin film transistor, thereby simplifying a manufacturing process of the device, reducing a manufacturing time thereof, and reducing a manufacturing cost thereof. To this end, the source electrode, the drain electrode and a light-blocking layer are disposed on a substrate, and constitute the same layer and are made of the same material. An interlayer insulating layer is disposed thereon. A first contact-hole and a second contact-hole are disposed in the interlayer insulating layer. A first connection line connects the source electrode and an active layer to each other, and a second connection line connects the drain electrode and the active layer to each other, whereby the array substrate of the display device can be manufactured using the total of 7 mask processes.

Abstract: A vertical memory device may include a first conductive line structure and an address decoder. The first conductive line structure may be on a substrate. The first conductive line structure may include conductive lines and insulation layers alternately and repeatedly stacked in a direction perpendicular to the substrate. The address decoder may be connected to a first end of each of conductive lines included in the first conductive line structure. The address decoder may apply electrical signal to the conductive lines. In each of the conductive lines, a first portion adjacent to the first end and a second portion adjacent to a second end may have different shapes. A first resistance in the first portion may be lower than a second resistance in the second portion. RC delay of the conductive lines may be reduced.

Abstract: The present application provides a method of manufacturing a memory device.

Abstract: To reduce the manufacturing cost of a display device using a micro LED as a display element. To manufacture a display device using a micro LED as a display element in a high yield. Employed is a method for manufacturing a display device, including: forming a plurality of transistors in a matrix over a substrate (800), forming conductors (21, 23) electrically connected to the transistors over the substrate (800), and forming a plurality of light-emitting elements (51) in a matrix over a film (927). Each of the light-emitting elements (51) includes electrodes (85, 87) on one surface and the other surface is in contact with the film (927). The conductors (21, 23) and the electrodes (85, 87) are opposed to each other. An extrusion mechanism (929) is pushed out from the film (927) side to the substrate (800) side so that the conductors (21, 23) and the electrodes (85, 87) are in contact with each other, whereby the conductors (21, 23) and the electrodes (85, 87) are electrically connected to each other.

Abstract: A semiconductor device that includes an epitaxial layer having a first-type dopant, a first well having a second-type dopant, a base layer having the second-type dopant, a first metal layer comprising a first base terminal and an inner conductor, and a first via connecting the first base terminal to the first well. The base layer is formed within the epitaxial layer and in contact with the first well and at least one dielectric separates the inner conductor from the first base terminal, and the base layer.

Abstract: Methods for fabricating metallization stacks with one or more self-aligned staggered metal lines, and related semiconductor devices, are disclosed. Methods and devices are based on providing a spacer material conformal to bottom metal lines of a first layer of a metallization stack. By carefully designing parameters of the deposition process, the spacer material may be deposited in such a manner that, for each pair of adjacent bottom metal lines of the first layer, an opening in the spacer material is formed in a layer above the bottom metal lines (i.e., in the second layer of the metallization stack), the opening being substantially equidistant to the adjacent bottom metal lines of the first layer. Top metal lines are formed by filling the openings with an electrically conductive material, resulting in the top metal lines being self-aligned and staggered with respect to the bottom metal lines.

Abstract: Provided is an oxide thin film transistor, including a gate, a gate insulator, a channel layer, a protective layer, and a source electrode and drain electrode layer that are disposed on a base substrate, wherein the source electrode and drain electrode layer includes a source electrode and a drain electrode that are spaced; and the protective layer is disposed between the channel layer and the source electrode and drain electrode layer, and is in contact with both the source electrode and drain electrode layer and the channel layer; an orthographic projection of the protective layer on the base substrate covers an orthographic projection of the channel layer on the base substrate; and the protective layer includes a first portion, a second portion, and a third portion that are in different areas of the protective layer.

Abstract: A display panel and a display device are provided. Each includes a light-emitting device layer including a first conductive layer, an organic layer, and a second conductive layer. The first conductive layer includes a first electrode electrically connected to a pixel driving circuit. The second conductive layer includes a second electrode disposed on a first portion located on the organic layer. The auxiliary structure includes a base, an auxiliary electrode, and an auxiliary portion. A cross-section of the base is trapezoidal in shape. The second electrode exceeds the first portion and is connected to the auxiliary electrode.