Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a 3D NAND memory device includes a substrate, core regions, isolation regions, a layer stack, channel structures, and an isolation structure. Each core region is surrounded by one or more of the isolation regions. The layer stack is formed in each core region and includes first dielectric layers and conductor layers that are alternatingly stacked over each other. The channel structures are formed through the layer stack. The isolation structure is formed in one or more of the isolation regions, and includes second dielectric layers and third dielectric layers that are alternatingly stacked over each other.

Abstract: An organic light emitting device including, in sequence, a first electrode, a first charge transport layer, a second charge transport layer in contact with the first charge transport layer, a light emitting layer in contact with the second charge transport layer, and a second electrode, wherein the first charge transport layer includes a first material and a second material, the second charge transport layer includes the second material and a third material, and the light emitting layer includes the third material and a fourth material.

Abstract: In a semiconductor chip manufacturing device which produces a plurality of LD chips by dividing a semiconductor wafer, being placed in a casing in which a fluid medium is filled, on which a block line is formed in advance and also on which a scribed line is inscribed so that a microcrack is formed along the scribed line, the semiconductor chip manufacturing device comprises a reception stage for supporting the semiconductor wafer, and a blade cutting-edge for pressurizing the semiconductor wafer along its crack portion made of the block line or the scribed line, so that the semiconductor wafer is divided into a plurality of LD chips by pressurizing it by means of the blade cutting-edge along the crack portion in the fluid medium.

Abstract: The present disclosure relates to a semiconductor memory device and a manufacturing method of the semiconductor memory device. A semiconductor memory device includes a gate stacked structure, a channel layer passing through the gate stacked structure in a vertical direction, a memory layer disposed between the channel layer and the gate stacked structure, a dummy stacked structure extended toward the gate stacked structure, a first dummy pattern passing through the dummy stacked structure in the vertical direction, and a gap arranged in the first dummy pattern.

Abstract: A fabrication process for an STT MTJ MRAM device includes steps of cooling the device at individual or at multiple stages in its fabrication. The cooling process, which may be equally well applied during the fabrication of other multi-layered devices, is demonstrated to produce an operational device that is more resistant to adverse thermal effects during operation that would normally cause a similar device not so fabricated to lose stored data and otherwise fail to operate properly.

Abstract: An electroluminescent device includes a first electrode and a second electrode facing each other; an emission layer disposed between the first electrode and the second electrode and including a plurality of quantum dots and a first hole transporting material having a substituted or unsubstituted C4 to C20 alkyl group attached to a backbone structure; a hole transport layer disposed between the emission layer and the first electrode and including a second hole transporting material; and an electron transport layer disposed between the emission layer and the second electrode.

Abstract: A three-dimensional (3D) memory device is provided. In an example, the 3D memory device includes a staircase and a plurality of groups of support structures through the staircase. The plurality of groups of support structures are arranged in a first direction, and each of the groups of support structures comprises three support structures, wherein projections of the three support structures form a triangular shape in a plane parallel to the first direction.

Abstract: A set of features for a product is identified. It is determined that preventing an electrical connection at a ball-grid-array location on a ball-grid-array assembly of the product would result in the set of features. The ball-grid-array location is established as a target BGA location based on that determination. Suction is applied to a via at the target BGA location during reflow of the ball-grid-array assembly. With that application of suction, a solder ball at the target BGA location is drawn into the via.

Abstract: An organic light emitting device including, in sequence, a first electrode, a first charge transport layer, a second charge transport layer in contact with the first charge transport layer, a light emitting layer in contact with the second charge transport layer, and a second electrode, wherein the first charge transport layer includes a first material and a second material, the second charge transport layer includes the second material and a third material, and the light emitting layer includes the third material and a fourth material.

Abstract: A display panel and a display device are disclosed, the display panel comprises: a base substrate; and pixel circuits in an array, the display panel comprises a light transmittance region and a display region around the light transmittance region, the pixel circuits are disposed in the display region, a gate line of each row of m rows of pixel circuits is divided into a first gate line portion and a second gate line portion which are connected through an auxiliary gate line, a data line of each column of n columns of pixel circuits is divided into a first data line portion and a second data line portion which are connected through an auxiliary data line.

Abstract: An organic light-emitting device having a perovskite layer having a thickness of 50 nm or more has a low drive voltage and a high power efficiency, and can suppress interelectrode short-circuiting and current leakage.

Abstract: A display device including: a substrate; an active layer disposed on the substrate and including active patterns; a first conductive layer disposed on the active layer; a second conductive layer disposed on the first conductive layer and including a data line; a third conductive layer disposed on the second conductive layer; and a light-emitting element disposed on the third conductive layer, wherein the first conductive layer includes a scan line, a first voltage line, and a second voltage line, the third conductive layer includes a third voltage line connected to the first voltage line and a fourth voltage line connected to the second voltage line, the first voltage line and the second voltage line extend in a first direction, the third voltage line and the fourth voltage line extend in a second direction, and the third voltage line and the fourth voltage line are alternately arranged in the first direction.

Abstract: Provided is a semiconductor super junction power device. The semiconductor super junction power device includes an MOSFET cell array composed of multiple super junction MOSFET cells. Each of multiple MOSFET cells includes a p-type body region located at the top of an n-type drift region, a p-type columnar doping region located below the p-type body region, an n-type source region located in the p-type body region, a gate dielectric layer located above the p-type body region, a gate electrode located above the p-type body region, an n-type floating gate located above the p-type body region and an opening located in the gate dielectric layer, where in a lateral direction, the gate electrode is located on one side close to the n-type source region; an opening located in the gate dielectric layer, where the n-type floating gate contacts the p-type body region through the opening to form a p-n junction diode.

Abstract: Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

Abstract: The present invention provides a photosensitive element, and a preparation method and a display device thereof. The photosensitive element includes a substrate; a first electrode arranged on the substrate; an N-type doped silicon layer arranged on the first electrode; an undoped silicon layer arranged on the N-type doped silicon layer; a molybdenum oxide layer arranged on the undoped silicon layer; an insulating layer arranged on the molybdenum oxide layer and the substrate, wherein a first opening is arranged on the insulating layer to expose the molybdenum oxide layer; and a second electrode arranged on the insulating layer and the molybdenum oxide layer, wherein the second electrode contacts the molybdenum oxide layer through the first opening.

Abstract: Provided are a perovskite optoelectronic device containing an exciton buffer layer, and a method for manufacturing the same. The optoelectronic device of the present invention comprises: an exciton buffer layer in which a first electrode, a conductive layer disposed on the first electrode and comprising a conductive material, and a surface buffer layer containing fluorine-based material having lower surface energy than the conductive material are sequentially deposited; a photoactive layer disposed on the exciton buffer layer and containing a perovskite photoactive layer; and a second electrode disposed on the photoactive layer. Accordingly, a perovskite is formed with a combined FCC and BSS crystal structure in a nanoparticle photoactive layer. The present invention can also form a lamellar or layered structure in which an organic plane and an inorganic plane are alternatively deposited; and an exciton can be bound by the inorganic plane, thereby being capable of expressing high color purity.

Abstract: Described herein is a technique capable of detecting a substrate state without contacting the substrate. According to one aspect of the technique, there is provided (a) loading a substrate retainer, where a plurality of substrates is placed, into a reaction tube; (b) processing the plurality of the substrates by supplying a gas into the reaction tube; (c) unloading the substrate retainer out of the reaction tube after the plurality of the substrates is processed; and (d) detecting the plurality of the substrates placed on the substrate retainer after the substrate retainer is rotated by a first angle with respect to a transferable position, wherein the plurality of the substrates is transferable to/from the substrate retainer in the transferable position.

Abstract: An electroconductive substrate, including: a base material; a foundation layer disposed on the base material; a trench formation layer disposed on the foundation layer, and an electroconductive pattern layer including metal plating. A trench including a bottom surface to which the foundation layer is exposed, is formed. The trench is filled with the electroconductive pattern layer. The foundation layer includes a mixed region which is formed from a surface of the foundation layer on the electroconductive pattern layer side towards the inside thereof, and contains metal particles which contain a metal configuring the electroconductive pattern layer, and enter the foundation layer.

Abstract: A thin film of metal oxide includes zinc (Zn); tin (Sn); silicon (Si); and oxygen (O). In terms of oxide, based on 100 mol % of total of oxides of the thin film, SnO2 is greater than 15 mol % but less than or equal to 95 mol %.

Abstract: A dielectric composition including a metal oxide particle including a diameter of 5 nanometers or less capped with an organic ligand at at least a 1:1 ratio. A method including synthesizing metal oxide particles including a diameter of 5 nanometers or less; and capping the metal oxide particles with an organic ligand at at least a 1:1 ratio. A method including forming an interconnect layer on a semiconductor substrate; forming a first hardmask material and a different second hardmask material on the interconnect layer, wherein at least one of the first hardmask material and the second hardmask material is formed over an area of interconnect layer target for a via landing and at least one of the first hardmask material and the second hardmask material include metal oxide nanoparticles; and forming an opening to the interconnect layer selectively through one of the first hardmask material and the second hardmask material.