Abstract: Techniques are provided for radio frequency interconnections between oscillators and transmission lines for oscillatory neural networks (ONNs). An ONN gate implementing the techniques according to an embodiment includes a transmission line, a first oscillator circuit tuned to a first frequency based on a first tuning voltage associated with a first synapse weight, and a first capacitive coupler to couple the first oscillator circuit to the transmission line to generate an oscillating signal in the transmission line. The ONN gate further includes a second oscillator circuit tuned to a second frequency based on a second tuning voltage associated with a second synapse weight, and a second capacitive coupler to couple the second oscillator circuit to the transmission line to adjust the oscillating signal in the transmission line such that the amplitude of the adjusted oscillating signal is associated with a degree of match between the first frequency and the second frequency.

Abstract: Provided are a perovskite light emitting device containing an exciton buffer layer, and a method for manufacturing the same. A light emitting device of the present invention comprises: an exciton buffer layer in which a first electrode, a conductive layer disposed on the first electrode and comprising a conductive material, and a surface buffer layer containing fluorine-based material having lower surface energy than the conductive material are sequentially deposited; a light-emitting layer disposed on the exciton buffer layer and containing a perovskite light-emitter; and a second electrode disposed on the light-emitting layer. Accordingly, a perovskite is formed with a combined FCC and BSS crystal structure in a nanoparticle light-emitter. The present invention can also form a lamellar or layered structure in which an organic plane and an inorganic plane are alternatively deposited; and an exciton can be bound by the inorganic plane, thereby being capable of expressing high color purity.

Abstract: A method of depositing a cathode on an organic light emitting diode (OLED) stack is provided. The method includes providing a substrate having at least a partial organic light emitting diode (OLED) stack disposed on a surface of the substrate. The method further includes depositing, on top of the partial OLED stack, a solution comprising a metal compound. The method further includes forming a conductive solid layer from the metal compound in the solution to form a cathode for the partial OLED stack.

Abstract: The present invention relates to an electrical component. The present invention further relates to an electrical device comprising such an electrical component and to a flat no-lead package. According to the invention, the flat no-lead package comprises a semiconductor die comprising electrical circuitry that has a plurality of terminals for inputting and outputting one or more signals, a thermal pad on which the semiconductor die is mounted, a plurality of leads arranged spaced apart from the thermal pad, and a plurality of further leads that are integrally connected to the thermal pad. One or more terminals among the plurality of terminals are each connected to a respective lead, and one or more terminals among the plurality of terminals are each connected to a respective further lead.

Abstract: A substrate processing method is implemented in a substrate processing apparatus including a processing chamber, a turntable on which a substrate is placed inside the processing chamber, and first and second gas supplies that supply first and second gases, respectively. The substrate processing method deposits a film, generated by a reaction between the first gas and the second gas, on the substrate in a first state where the substrate rotates and the turntable undergoes a clockwise orbital rotation around a rotating shaft so that the substrate passes through a region supplied with the first gas and thereafter passes through a region supplied with the second gas, and deposits the film on the substrate in a second state where the substrate rotates and the turntable undergoes a counterclockwise orbital rotation.

Abstract: Described herein is a technique capable of detecting a substrate state without contacting the substrate. According to one aspect of the technique, there is provided (a) loading a substrate retainer, where a plurality of substrates is placed, into a reaction tube; (b) processing the plurality of the substrates by supplying a gas into the reaction tube; (c) unloading the substrate retainer out of the reaction tube after the plurality of the substrates is processed; and (d) detecting the plurality of the substrates placed on the substrate retainer after the substrate retainer is rotated by a first angle with respect to a transferable position, wherein the plurality of the substrates is transferable to/from the substrate retainer in the transferable position.

Abstract: A package on package structure includes a first package, a plurality of conductive bumps, a second package and an underfill. The conductive bumps are disposed on a second surface of the first package and electrically connected to the first package. The second package is disposed on the second surface of the first package through the conductive bumps, and includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. A shortest distance from an upper surface of the encapsulating material to an upper surface of the semiconductor device is greater than or substantially equal to twice a thickness of the semiconductor device. The underfill is filled between the first package and the second package.

Abstract: A support for a semiconductor structure includes a charge-trapping layer on a base substrate. The charge-trapping layer consists of a polycrystalline main layer and, interposed in the main layer or between the main layer and the base substrate, at least one intermediate polycrystalline layer composed of a silicon and carbon alloy or carbon. The intermediate layer has a resistivity greater than 1000 ohm·cm.

Abstract: In some embodiments, a system for monitoring a tool is provided. The system includes a tool monitoring device, a transporting system and an external apparatus. The tool monitoring device is configured to monitor an environmental parameter of a load port of a tool. The tool monitoring device includes a wafer pod and a monitoring module disposed in the wafer pod. The monitoring module includes at least one sensor, a computer coupled to the at least one sensor, a power supply electrically coupled to the at least one sensor and the computer, and a wireless unit coupled to the computer. The transporting system is configured to transfer the tool monitoring device from one load port to another load port. The external apparatus is coupled to the tool monitoring device.

Abstract: A dielectric composition including a metal oxide particle including a diameter of 5 nanometers or less capped with an organic ligand at at least a 1:1 ratio. A method including synthesizing metal oxide particles including a diameter of 5 nanometers or less; and capping the metal oxide particles with an organic ligand at at least a 1:1 ratio. A method including forming an interconnect layer on a semiconductor substrate; forming a first hardmask material and a different second hardmask material on the interconnect layer, wherein at least one of the first hardmask material and the second hardmask material is formed over an area of interconnect layer target for a via landing and at least one of the first hardmask material and the second hardmask material include metal oxide nanoparticles; and forming an opening to the interconnect layer selectively through one of the first hardmask material and the second hardmask material.

Abstract: An X-ray source is disposed and a detector is disposed adjacent to the X-ray source. A test specimen holder is disposed between the X-ray source and the detector. A filter is disposed between the X-ray source and the test specimen holder. The filter has a plate-shaped semiconductor, a granular semiconductor, or a combination thereof.

Abstract: A light emitting device includes a mounting board, light sources, a light diffuser, a wavelength conversion layer, and scatter reflection portions. Each of the light sources has an upper face on which a light reflecting layer is disposed. The light diffuser is arranged above the plurality of light sources. The wavelength conversion layer is located at least between the light sources and the light diffuser. The wavelength conversion layer is configured to absorb at least a portion of light from the light sources and to emit light having a wavelength which is different from a wavelength of the light from the light sources. The scatter reflection portions are arranged on a surface of the wavelength conversion layer that is closer to the light diffuser. Each of the scatter reflection portions is arranged above at least a portion of the upper face of a corresponding one of the light sources.

Abstract: A display device including: a substrate; an active layer disposed on the substrate and including active patterns; a first conductive layer disposed on the active layer; a second conductive layer disposed on the first conductive layer and including a data line; a third conductive layer disposed on the second conductive layer; and a light-emitting element disposed on the third conductive layer, wherein the first conductive layer includes a scan line, a first voltage line, and a second voltage line, the third conductive layer includes a third voltage line connected to the first voltage line and a fourth voltage line connected to the second voltage line, the first voltage line and the second voltage line extend in a first direction, the third voltage line and the fourth voltage line extend in a second direction, and the third voltage line and the fourth voltage line are alternately arranged in the first direction.

Abstract: Techniques are disclosed for fabricating and using a neuromorphic computing device including biological neurons. For example, a method for fabricating a neuromorphic computing device includes forming a channel in a first substrate and forming at least one sensor in a second substrate. At least a portion of the channel in the first substrate is seeded with a biological neuron growth material. The second substrate is attached to the first substrate such that the at least one sensor is proximate to the biological neuron growth material and growth of the seeded biological neuron growth material is stimulated to grow a neuron in the at least a portion of the channel.

Abstract: A method of separating a wafer including rows of light emitting devices is described. Dicing streets are provided on the wafer such that a respective one of the dicing streets is provided between each of the rows of light emitting devices on the wafer. The wafer is broken along a first one of the dicing streets to separate a first portion of the wafer from a remaining portion of the wafer. The first portion of the wafer includes more than one of the rows of light emitting devices. The first portion of the wafer is broken along a second one of the dicing streets to separate a second portion of the wafer from the first portion of the wafer.

Abstract: A semiconductor device that is a surface mount-type device includes a nitride semiconductor chip including a silicon substrate having a first thermal expansion coefficient and an InxGayAl1-x-yN layer in contact with a surface of the silicon substrate, where 0?x?1, 0?y?1, 0?x+y?1; and a die pad including Cu and having a second thermal expansion coefficient that is greater than the first thermal expansion coefficient. A thickness of the nitride semiconductor chip is at least 0.2 mm, length L of the nitride semiconductor chip is at least 3.12 mm, and thickness tm of the die pad and length L of the nitride semiconductor chip satisfy tm?2.00×10?3×L2+0.173, tm being a thickness in mm and L being a length in mm.

Abstract: A drilling method includes collecting survey data at a drilling site, and determining a waypoint or borehole path based on the survey data. The drilling method also includes sending the survey data to a remote monitoring facility that applies corrections to the survey data. The drilling method also includes receiving the corrected survey data, and automatically updating the waypoint or borehole path based on the corrected survey data.

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes a substrate, a first device layer disposed on the substrate, and a first bonding layer disposed above the first device layer and including a first bonding contact. The second semiconductor structure includes a second device layer, and a second bonding layer disposed below the second device layer and including a second bonding contact. The first bonding contact is in contact with the second bonding contact at the bonding interface. At least one of the first bonding contact and the second bonding contact includes a capping layer at the bonding interface and having a conductive material different from a remainder of the respective first or second bonding contact.

Abstract: Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers.

Abstract: Some embodiments include a conductive structure of an integrated circuit. The conductive structure includes an upper primary portion, with the upper primary portion having a first conductive constituent configured as a container. The container has a bottom, and a pair of sidewalls extending upwardly from the bottom. An interior region of the container is over the bottom and between the sidewalls. The upper primary portion includes a second conductive constituent configured as a mass filling the interior region of the container. The second conductive constituent is a different composition than the first conductive constituent. One or more conductive projections join to the upper primary portion and extend downwardly from the upper primary portion. Some embodiments include assemblies comprising memory cells over conductive structures. Some embodiments include methods of forming conductive structures.