Abstract: HVAC load can be shifted to change indoor temperature. A time series change in HVAC load data is used as input modified scenario values that represent an HVAC load shape. The HVAC load shape is selected to meet desired energy savings goals, such as reducing or flattening peak energy consumption load to reduce demand charges, moving HVAC consumption to take advantage of lower utility rates, or moving HVAC consumption to match PV production. Time series change in indoor temperature data can be calculated using only inputs of time series change in the time series HVAC load data combined with thermal mass, thermal conductivity, and HVAC efficiency. The approach is applicable for both winter and summer and can be applied when the building has an on-site renewable power system.

Abstract: A three-dimensional integrated circuit includes a first die structure having a first geometry. The first die structure includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The three-dimensional integrated circuit includes a second die structure having a second geometry. A stacked portion of the second die structure is aligned with the first region. The three-dimensional integrated circuit includes an additional die structure stacked with the first die structure and the second die structure. The additional die structure has the first geometry or the second geometry.

Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.

Abstract: A semiconductor component includes a semiconductor body having opposing first surface and second surfaces, and a side surface surrounding the semiconductor body. The semiconductor component also includes an active region including a first semiconductor region of a first conductivity type, which is electrically contacted via the first surface, and a second semiconductor region of a second conductivity type, which is electrically contacted via the second surface. The semiconductor component further includes an edge termination region arranged in a lateral direction between the first semiconductor region of the active region and the side surface, and includes a first edge termination structure and a second edge termination structure. The second edge termination structure is arranged in the lateral direction between the first edge termination structure and the side surface and extends from the first surface in a vertical direction more deeply into the semiconductor body than the first edge termination structure.

Abstract: A semiconductor package is provided. The semiconductor package includes an encapsulating layer, a semiconductor die formed in the encapsulating layer, and an interposer structure covering the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure also includes insulting features formed on the first surface of the insulating base and extending into the encapsulating layer. The insulting features are arranged in a matrix and face a top surface of the semiconductor die. The interposer structure further includes first conductive features formed on the first surface of the insulating base and extending into the encapsulating layer. The first conductive features surround the matrix of the plurality of insulting features.

Abstract: A semiconductor device comprises an electrode on a substrate, an insulating layer covering an edge of the electrode and disposed on the substrate, and an organic layer comprising a charge transport layer on the electrode and insulating layer and a functional layer, wherein the insulating layer has a first portion forming an angle of 0° to 50° with respect to a surface parallel to a lower surface of the electrode, a second portion located closer to the substrate than the first portion and sloping at more than 50°, and a third portion located closer to the organic layer than the first portion and sloping at more than 50°, wherein a length of the third portion in a direction perpendicular to the parallel surface is larger than a thickness of the charge transport layer at a position in contact with the electrode.

Abstract: A semiconductor storage device includes: a first conductive layer and a second conductive layer arranged in a first direction; a plurality of first semiconductor layers facing the first conductive layer, the plurality of first semiconductor layers arranged in a second direction intersecting the first direction; a first charge storage layer disposed between the plurality of first semiconductor layers and the first conductive layer; and a first insulating layer provided between the plurality of first semiconductor layers and the first charge storage layer in the first direction. The first insulating layer includes a first region, a second region, and a third region provided between the first region and the second region in the second direction. A nitrogen concentration in the first region and the second region is lower than a nitrogen concentration in the third region.

Abstract: A semiconductor device includes a first dielectric layer, a second dielectric layer and a memory device. The second dielectric layer includes a first layer and a second layer. The memory device includes a first conductive structure under the first dielectric layer, a second conductive structure over the second dielectric layer, and a memory cell between the first and the second dielectric layers. The memory cell includes a bottom electrode via, a bottom electrode over the bottom electrode via, a top electrode over the bottom electrode, a top electrode via over the top electrode, and a MTJ between the top electrode and the bottom electrode. The second layer of the second dielectric layer surrounds sidewalls of the top electrode via entirely. The first layer of the second dielectric layer surrounds sidewalls of the bottom electrode entirely, sidewalls of the MTJ entirely, and sidewalls of the top electrode entirely.

Abstract: A conductive C-plane GaN substrate has a resistivity of 2×10?2 ?·cm or less or an n-type carrier concentration of 1×1018 cm?3 or more at room temperature. At least one virtual line segment with a length of 40 mm can be drawn at least on one main surface of the substrate. The line segment satisfies at least one of the following conditions (A1) and (B1): (A1) when an XRC of (004) reflection is measured at 1 mm intervals on the line segment, a maximum value of XRC-FWHMs across all measurement points is less than 30 arcsec; and (B1) when an XRC of the (004) reflection is measured at 1 mm intervals on the line segment, a difference between maximum and minimum values of XRC peak angles across all the measurement points is less than 0.2°.

Abstract: A transparent electrode-equipped substrate includes, on a film base material having a transparent film substrate, a non-crystalline transparent foundation oxide layer and a non-crystalline transparent conductive oxide layer. The transparent electrode-equipped substrate is capable of achieving low resistivity by having the transparent oxide layers being formed sequentially from the film base material side through sputtering such that the absolute value of a discharge voltage (VU) of a direct-current (DC) power supply when forming the transparent foundation oxide layer is 255-280 V, the ratio (VU/VC) between the discharge voltage (VU) of the DC power supply when forming the transparent foundation oxide layer and the discharge voltage VC of the DC power supply when forming the transparent conductive oxide layer is 0.86-0.98.

Abstract: A method includes transferring a tool monitoring device to a load port of a tool. An environmental parameter of the load port is monitored by the tool monitoring device. The tool monitoring device is removed from the load port after the environmental parameter of the load port is monitored. A door of the tool in front of the load port is closed. The door of the tool is kept closed during a period from a time of transferring the tool monitoring device to the load port to a time of removing the tool monitoring device from the load port.

Abstract: Discussed is a substrate chuck for self-assembling micro LEDs. The substrate chuck can include a first frame having a hole at a central portion thereof, a second frame having a hole at a central portion thereof and disposed to overlap the first frame, a frame transfer part configured to transfer the second frame so that the second frame presses the substrate while the substrate is disposed between the first and second frames, and an auxiliary clamp configured to additionally press the second frame toward the substrate while the second frame is pressing on the substrate.

Abstract: A system may include a main line for delivering a first gas, and a sensor for measuring a concentration of a precursor in the first gas delivered through the main line. The system may further include first and second sublines for providing fluid access to first and second processing chambers, respectively. The first subline may include a first flow controller for controlling the first gas flowed through the first subline. The second subline may include a second flow controller for controlling the first gas flowed through the second subline. A delivery controller may be configured to control the first and second flow controllers based on the measured concentration of the precursor to deliver a first mixture of the first gas and a second gas and a second mixture of the first and second gases into the first and second semiconductor processing chambers, respectively.

Abstract: Disclosed is a support unit for supporting a substrate. The support unit includes a support plate having an inner space defined therein, a heating member disposed in the inner space and emitting light for heating the substrate supported on the support unit, and a reflective member disposed along an edge region of the support plate and reflecting thermal energy of the light to an edge region of the substrate supported on the support unit.

Abstract: A method of making a semiconductor structure includes forming a plurality of gate electrodes over a plurality of active regions. The method further includes increasing a width of a portion of each of the plurality of gate electrodes between adjacent active regions of the plurality of active regions, wherein increasing the width of the portion of each of the plurality of gate electrodes comprises increasing the width of less than an entirety of each of the plurality of gate electrodes between the adjacent active regions. The method further includes removing a central region of each of the plurality of gate electrodes, wherein the central region has the increased width, and removing the central region comprises removing less than an entirety of the portion of each of the plurality of gate electrodes.

Abstract: A method for forming a chip package structure is provided. The method includes forming a first redistribution structure over a first carrier substrate. The method includes bonding a chip structure to the first surface through a first conductive bump. The method includes forming a first molding layer over the first redistribution structure. The method includes removing the first carrier substrate. The method includes forming a second conductive bump over the second surface. The method includes forming a second redistribution structure over a second carrier substrate. The method includes bonding the first redistribution structure to the third surface. The method includes forming a second molding layer over the second redistribution structure. The method includes removing the second carrier substrate. The method includes removing a portion of the second redistribution structure from the fourth surface. The method includes forming a third conductive bump over the fourth surface.

Abstract: The present disclosure provides a quantum dot light emitting diode, a manufacturing method thereof and a display device, and belongs to the field of display technologies. The quantum dot light emitting diode of the present disclosure includes an anode layer, a cathode layer, a quantum dot layer disposed between the anode layer and the cathode layer, an electron transport layer disposed between the quantum dot layer and the cathode layer, and an electron blocking layer disposed between the electron transport layer and the quantum dot layer; and metal-sulfur bonds are formed in an interface between the electron blocking layer and the quantum dot layer, and contain metal elements from the quantum dot layer and sulfur elements from the electron blocking layer.

Abstract: Disclosed herein are implementations of a particles-transferring system, particle transferring unit, and method of transferring particles in a pattern. In one implementation, a particles-transferring system includes a first substrate including a first surface to support particles in a pattern, particle transferring unit including an outer surface to be offset from the first surface by a first gap, and second substrate including a second surface to be offset from the outer surface by a second gap. The particle transferring unit removes the particles from the first surface in response to the particles being within the first gap, secures the particles in the pattern to the outer surface, and transports the particles in the pattern. The second substrate removes the particles in the pattern from the particle transferring unit in response to the particles being within the second gap. The particles are to be secured in the pattern to the second surface.

Abstract: In a method for forming an integrated structure, a top dielectric layer is formed over a top surface of a substrate. The top dielectric layer includes a plurality of vias that are formed through the top dielectric layer and extend into the substrate. A bottom dielectric layer is formed on a bottom surface of the substrate. An isolation opening and a plurality of contact openings are further formed in the bottom dielectric layer and the substrate, where the isolation opening passes through the bottom dielectric layer and extends from the bottom surface to the top surface of the substrate. The isolation opening is filled with an insulating layer to form an isolation trench. The plurality of contact openings are filled with a conductive layer to form a plurality of through silicon contacts (TSCs). A conductive plate is further formed over the bottom dielectric layer.

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first device layer is formed on a first substrate. A first bonding layer including a first bonding contact is formed above the first device layer. A first capping layer is formed at an upper end of the first bonding contact. The first capping layer has a conductive material different from a remainder of the first bonding contact. A second device layer is formed on a second substrate. A second bonding layer including a second bonding contact is formed above the second device layer. The first substrate and the second substrate are bonded in a face-to-face manner, so that the first bonding contact is in contact with the second bonding contact by the first capping layer.