Patents Examined by Allan Olsen
  • Patent number: 10224221
    Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. Where multiple plasma grids are used, one or more of the grids may be movable, allowing for tenability of the plasma conditions in at least the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: March 5, 2019
    Assignee: Lam Research Corporation
    Inventors: Harmeet Singh, Thorsten Lill, Vahid Vahedi, Alex Paterson, Monica Titus, Gowri Kamarthy
  • Patent number: 10221488
    Abstract: A method of reducing surface roughness in an internal passage of a workpiece includes contacting the internal passage with a corrosive working fluid comprising water at or near supercritical conditions.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: March 5, 2019
    Assignee: General Electric Company
    Inventor: Scott Alan Gold
  • Patent number: 10224213
    Abstract: A method for forming patterns of a semiconductor device includes sequentially forming a hard mask layer, a sacrificial layer, and an anti-reflection layer on a substrate, the substrate including a cell region and a peripheral circuit region, patterning the sacrificial layer to form a first sacrificial pattern on the cell region and a second sacrificial pattern on the peripheral circuit region, forming spacers covering sidewalls of the first and second sacrificial patterns, and removing the first sacrificial pattern. The anti-reflection layer includes a lower anti-reflection layer and an upper anti-reflection layer which are formed of materials different from each other. In the patterning of the sacrificial layer, the anti-reflection layer is patterned to form a first anti-reflection pattern on the first sacrificial pattern and a second anti-reflection pattern on the second sacrificial pattern. The second anti-reflection pattern remains when the first sacrificial pattern is removed.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: March 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungmun Byun, Sinhae Do, Badro Im
  • Patent number: 10217610
    Abstract: Methods for controlling bevel etch rate of a substrate during plasma processing within a processing chamber includes securing the substrate on a lower electrode within the processing chamber. A power source is provided. A gas mixture is flowed into the processing chamber. A first match arrangement coupled to an upper electrode is adjusted to control current flowing through the upper electrode to change the upper electrode from a grounded state to a floating state. A second match arrangement coupled to a top ring electrode is adjusted to control current flowing through the top ring electrode so as to control plasma formed above a top edge of the substrate. An extension of the upper electrode is lowered during plasma processing so as to minimize a gap between the extension of the upper electrode and the substrate received on the lower electrode, such that the gap is incapable of supporting plasma formed in the processing chamber.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: February 26, 2019
    Assignee: Lam Research Corporation
    Inventors: Eller Y. Juco, Neungho Shin, Yunsang Kim, Andrew Bailey
  • Patent number: 10192743
    Abstract: A method of preparing a self-aligned block (SAB) structure is described. The method includes providing a substrate having raised features defined by a first material containing silicon nitride and a second material containing silicon oxide formed on side walls of the first material, and a third material containing an organic material covering some of the raised features and exposing some raised features according to a block pattern formed in the third material. The method further includes forming a first chemical mixture by plasma-excitation of a first process gas, and exposing the first material on the substrate to the first chemical mixture. Thereafter, the method includes forming a second chemical mixture by plasma-excitation of a second process gas, and exposing the first material on the substrate to the second plasma-excited process gas to selectively etch the first material relative to the second and third material.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: January 29, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Sonam D. Sherpa, Alok Ranjan
  • Patent number: 10187999
    Abstract: The present invention discloses a method for manufacturing a printed circuit board having an ultra-thin metal layer. The method discharges alkaline aliphatic amine gas and the nitrogen bubbled in the cupric sulfate solution via capacitive coupling in a vacuum, to generate low temperature plasma. The polyimide film and the epoxy resin board coated with fiberglass cloth are etched and the surface is treated to graft active groups, so as to increase the surface roughness and chemical activity. Subsequently, sputtering copper plating or chemical copper plating is directly conducted. The electroplating is conducted to thicken the copper film to a required thickness. The method of the invention not only does not need adhesive (adhesive free), but also has a high peeling strength. It can be used for the preparation of the flexible PCB, the rigid PCB, the multi-layer PCB, and rigid-flex PCB, having an ultra-thin metal layer.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: January 22, 2019
    Assignees: SUZHOU WEIPENG ELECTRICAL TECHNOLOGY CO., LTD., CHANGSHU MUTUAL-TEK CO., LTD.
    Inventors: Yuedong Meng, Futang Fang, Peng Chang
  • Patent number: 10182501
    Abstract: A method for preparing an adhesive-free polyimide flexible printed circuit board is provided. The method includes the following steps: 1) placing a polyimide thin film into a low vacuum environment, and treating the polyimide thin film using plasma produced by capacitively coupled discharge of an organic amine; 2) placing the polyimide thin film obtained in step 1) into a low vacuum environment, and pretreating the polyimide thin film using plasma formed by capacitively coupled discharge of a nitrogen gas bubbled through a metal salt solution; 3) pre-plating the polyimide thin film obtained in step 2) using vacuum sputtering or chemical plating so as to obtain a dense copper film with a thickness of less than 100 nm; and 4) thickening the copper film to a required thickness by means of an electroplating method.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: January 15, 2019
    Assignee: SUZHOU WEIPENG ELECTRICAL TECHNOLOGY CO., LTD.
    Inventors: Yuedong Meng, Peng Chang, Gangqiang Cai
  • Patent number: 10170284
    Abstract: A plasma processing method according to an aspect includes: preparing a plasma processing apparatus including: a chamber; a lower electrode; an upper electrode; a focus ring surrounding a peripheral edge of the lower electrode; and an annular coil disposed on an upper portion of the upper electrode at a more outer position than the peripheral edge of the lower electrode; placing a substrate on the lower electrode, with a peripheral edge of the substrate surrounded by the focus ring; introducing process gas into the chamber; generating plasma of the process gas by applying high-frequency power across the upper electrode and the lower electrode; and leveling an interface of a plasma sheath on an upper portion of the substrate with that on an upper portion of the focus ring by generating a magnetic field by supplying a current to the annular coil.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: January 1, 2019
    Assignees: TOKYO ELECTRON LIMITED, KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenta Yasuda, Toru Kubota, Takashi Kondo, Katsuhiro Ishida
  • Patent number: 10144850
    Abstract: Chemical mechanical polishing (CMP) compositions, methods and systems are for polishing patterned semiconductor wafers. The CMP compositions comprising an abrasive and a water soluble aluminum compound additive with a pH>7 suppress CMP stop layer (a silicon containing layer, such as silicon nitride, silicon oxide, or silicon carbide) removal rate. CMP compositions optionally contain surfactant to help wet surface; a corrosion inhibitor to provide corrosion inhibition on metal lines, vias, or trenches; and a pH adjusting agent that is used to adjust pH of the CMP polishing composition.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: December 4, 2018
    Assignee: VERSUM MATERIALS US, LLC
    Inventors: Matthias Stender, Maitland Gary Graham
  • Patent number: 10147612
    Abstract: A metal pattern forming method according to an embodiment includes forming a metal film on a surface of a substrate by an electroless plating method, the substrate including a first layer including a protrusion and a recess, and a film thickness of the metal film being a half or more of a width of the recess; and performing wet etching, the metal film in the recess removed by the wet etching and the metal film on the protrusion remained after the wet etching.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: December 4, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Nakanishi, Yusuke Tanaka, Atsushi Hieno, Yasuhito Yoshimizu, Akihiko Happoya
  • Patent number: 10147789
    Abstract: The present invention relates to a method for manufacturing a GaAs semiconductor nanowire in a bottom-up type and, more particularly, to a method for manufacturing a vertically-aligned gallium arsenide semiconductor nanowire array in a large area by applying a voltage and a current from the outside using a metal thin film, which has been made through an economical method of fabricating a mesh-type metal thin film in a large area, as an anode such that holes (h+) are injected into a gallium arsenide substrate, thereby inducing a wet etching process continuously. The obtained vertically-aligned gallium arsenide semiconductor nanowire of a large area can be applied to fabrication of nanoelements, such as a solar cell, a transistor, and a light-emitting diode.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: December 4, 2018
    Assignee: Korea Research Institute of Standards and Science
    Inventors: Woo Lee, Jeong Ho Shin
  • Patent number: 10138117
    Abstract: Compositions useful for the selective removal of titanium nitride and/or photoresist etch residue materials relative to metal conducting, e.g., tungsten, and insulating materials from a microelectronic device having same thereon. The removal compositions are low pH and contain at least one oxidizing agent and at least one etchant as well as corrosion inhibitors to minimize metal erosion and passivating agents to protect dielectric materials.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: November 27, 2018
    Assignee: Entegris, Inc.
    Inventors: Li-Min Chen, Steven Lippy, Daniela White, Emanuel I. Cooper
  • Patent number: 10134603
    Abstract: In an embodiment, a method of planarizing a surface includes applying a first layer to a surface including a protruding region including at least one compound semiconductor and a stop layer on an upper surface such that the first layer covers the surface and the protruding region, removing a portion of the first layer above the protruding region and forming an indentation in the first layer above the protruding region, the protruding region remaining covered by material of the first layer, and progressively removing an outermost surface of the first layer to produce a planarized surface including the stop layer on the upper surface of the protruding region and an outer surface of the first layer.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: November 20, 2018
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Helmut Brech
  • Patent number: 10121682
    Abstract: A purge ring for providing a gas to a wafer processing chamber includes an inlet ring wall defining a ring hole space. An outer perimeter of the inlet ring wall is elliptical. An outer perimeter of the ring hole space is circular. The inlet ring wall is a continuous structure surrounding the ring hole space. An inlet baffle formed within the inlet ring wall surrounds at least 180 degrees of the outer perimeter of the ring hole space. An inlet plenum arranged in a first end of the inlet ring wall provides the gas to the ring hole space through the inlet baffle. An exhaust channel is formed within the inlet ring wall in a second end of the inlet ring wall. An exhaust outlet hole arranged in the second end of the inlet ring wall exhausts the gas out of the ring hole space via the exhaust channel.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: November 6, 2018
    Assignee: Novellus Systems, Inc.
    Inventors: Eugene Smargiassi, Stephen Yu-Hong Lau, George D. Kamian, Ming Xi
  • Patent number: 10115601
    Abstract: Embodiments of the invention provide a processing method for selective film formation for raised and recessed features using deposition and etching processes. According to one embodiment, the method includes providing a substrate having a recessed feature with a sidewall and a bottom portion, and depositing a film in the recessed feature and on a field area around the opening of the recessed feature, where the film is non-conformally deposited with a greater film thickness on the bottom portion than on the sidewall and the field area. The method further includes etching the film in an atomic layer etching (ALE) process in the absence of a plasma, where the etching thins the film on the bottom portion and removes the film from the sidewall and the field area, and repeating the depositing and the etching at least once to increase the film thickness of on the bottom portion.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: October 30, 2018
    Assignee: Tokyo Electron Limited
    Inventor: Kandabara N. Tapily
  • Patent number: 10103034
    Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: October 16, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Chieh Hsu, Fu-Shou Tsai, Yu-Ting Li, Yi-Liang Liu, Kun-Ju Li
  • Patent number: 10103331
    Abstract: The present invention relates to slurry for polishing crystalline phase-change materials and to a method for producing a phase-change device using the same. The slurry for polishing crystalline phase-change materials according to one embodiment of the present invention comprises an abrasive, an alkaline abrasive enhancer, an oxidizing agent having a standard reduction potential higher than that of perchlorates, and ultrapure water. In addition, the method for producing a phase-change device according to one embodiment of the present invention comprises the following steps: preparing a substrate; forming a crystalline phase-change material film on the substrate; and removing the phase-change material film through a chemical-mechanical polishing process using slurry for polishing phase-change materials, which comprises an abrasive, an alkaline abrasive enhancer, an oxidizing agent having a standard reduction potential higher than that of perchlorates, and ultrapure water.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: October 16, 2018
    Assignee: Industry-University Cooperation Foundation Hanyang University
    Inventors: Jeagun Park, Ungyu Paik, Jinhyung Park, Hao Cui, Jongyoung Cho, Heesub Hwang, Jaehyung Lim, Yehwan Kim
  • Patent number: 10083838
    Abstract: Wafers processed by methods of plasma etching are disclosed. In one embodiment, a wafer is prepared by a process including positioning the wafer within a chamber of a plasma etcher, generating plasma ions using a radio frequency power source and a plasma source gas, directing the plasma ions toward the wafer using an electric field, focusing the plasma ions using a plasma focusing ring to increase a flux of plasma ions arriving at a surface of the wafer, and etching a plurality of through-wafer vias in the wafer.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: September 25, 2018
    Assignee: Skyworks Solutions, Inc.
    Inventors: Daniel Kwadwo Amponsah Berkoh, Elena Becerra Woodard, Dean G. Scott
  • Patent number: 10077380
    Abstract: Proposed is a polishing composition including hydroxyethyl cellulose, water and abrasive grains, wherein the hydroxyethyl cellulose has a molecular weight of 500,000 or more and 1,500,000 or less, and the mass ratio of the hydroxyethyl cellulose to the abrasive grains is 0.0075 or more and 0.025 or less.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: September 18, 2018
    Assignee: NITTA HAAS INCORPORATED
    Inventors: Masashi Teramoto, Tatsuya Nakauchi, Noriaki Sugita, Shinichi Haba, Akiko Miyamoto
  • Patent number: 10066128
    Abstract: The present disclosure provides a method for preparing an aluminum oxide polishing solution. The methods include: 1) mixing a silane coupling agent, ethyl alcohol, and water to form a hydrolysate; 2) under a condition of heating and stirring at a temperature between 95° C. and 110° C., adding the hydrolysate into aluminum oxide powder; keeping stirring while heating till liquid is completely volatilized, thereby obtaining a modified aluminum oxide; 3) grinding the modified aluminum oxide into powder and dispersing the powder into water; adjusting solution pH to 9.5-10.5, thereby obtaining the aluminum oxide polishing solution. It may achieve a polishing efficiency of pH=13.00 by using the aluminum oxide polishing solution of the present disclosure; meanwhile, less scratches will occur to a polishing disc.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: September 4, 2018
    Assignee: SHANGHAI XINANNA ELECTRONIC TECHNOLOGY CO., LTD
    Inventors: Weilei Wang, Weili Liu, Zhitang Song