Patents Examined by Allan Olsen
  • Patent number: 9887096
    Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch created from a remote plasma etch. The remote plasma excites a fluorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor. Reactants thereby produced etch the patterned heterogeneous structures to remove two separate regions of differing silicon oxide at different etch rates. The methods may be used to remove low density silicon oxide while removing less high density silicon oxide.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: February 6, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Seung H. Park, Yunyu Wang, Jingchun Zhang, Anchuan Wang, Nitin K. Ingle
  • Patent number: 9878420
    Abstract: A CMP method uses a slurry including colloidal metal oxide or colloidal semiconductor oxide particles (colloidal particles) in water. At least one particle feature is selected from (i) the colloidal particles having a polydispersity >30%, and (ii) mixed particle types including the colloidal particles having an average primary size >50 nm mixed with fumed oxide particles having average primary size <25 nm. A substrate having an alumina surface is placed into a CMP apparatus, and CMP is performed with a rotating polishing pad and the slurry to polish the alumina surface. The polydispersity is determined by a polydispersity formula for a distribution width (w) involving width w1 and width w2 at a second larger particle size. The polydispersity formula=(w2?w1)×100/dav which includes 63% of a total of the colloidal particles by volume and day is an average particle size of the colloidal particles.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: January 30, 2018
    Assignees: Sinmat, Inc., University of Florida Research Foundation, Inc.
    Inventors: Rajiv K. Singh, Kannan Balasundaram, Arul Chakkaravarthi Arjunan, Deepika Singh, Wei Bai
  • Patent number: 9870898
    Abstract: A plasma processing method includes applying a pulse wave of high frequency electric power for plasma generation and a pulse wave of high frequency electric power for bias whose frequency is lower than that of the high frequency electric power for plasma generation on the mounting table; and controlling the pulse wave of the high frequency electric power for plasma generation and the pulse wave of the high frequency electric power for bias such that a predetermined phase difference is generated between the pulse wave of the high frequency electric power for plasma generation and the pulse wave of the high frequency electric power for bias, and a duty ratio of the high frequency electric power for plasma generation becomes greater than or equal to a duty ratio of the high frequency electric power for bias.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: January 16, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masafumi Urakawa, Koichi Nagami
  • Patent number: 9862862
    Abstract: Described is a chemical-mechanical polishing (CMP) composition comprising the following components: (A) surface modified silica particles having a negative zeta potential of ?15 mV or below at a pH in the range of from 2 to 6 (B) one or more polyethylene imines (C) water (D) optionally one or more further constituents, wherein the pH of the composition is in the range of from 2 to 6.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: January 9, 2018
    Assignee: BASF SE
    Inventors: Yongqing Lan, Peter Przybylski, Zhenyu Bao, Julian Proelss
  • Patent number: 9865484
    Abstract: Semiconductor systems and methods may include methods of performing selective etches that include modifying a material on a semiconductor substrate. The substrate may have at least two exposed materials on a surface of the semiconductor substrate. The methods may include forming a low-power plasma within a processing chamber housing the semiconductor substrate. The low-power plasma may be a radio-frequency (“RF”) plasma, which may be at least partially formed by an RF bias power operating between about 10 W and about 100 W in embodiments. The RF bias power may also be pulsed at a frequency below about 5,000 Hz. The methods may also include etching one of the at least two exposed materials on the surface of the semiconductor substrate at a higher etch rate than a second of the at least two exposed materials on the surface of the semiconductor substrate.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: January 9, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Bhargav Citla, Chentsau Ying, Srinivas Nemani, Viachslav Babayan, Michael Stowell
  • Patent number: 9859127
    Abstract: A photon-assisted plasma processing method for processing a substrate with a process layer is provided. A process gas is flowed into the chamber. The process gas is formed into a plasma. The process layer is exposed to the plasma. The process layer is illuminated with a light with a wavelength of between 200 nm and 1 micron, while exposing the substrate to the plasma.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: January 2, 2018
    Assignee: Lam Research Corporation
    Inventors: Zhongkui Tan, Qing Xu, Qian Fu, Sangjun Park
  • Patent number: 9859102
    Abstract: A method of etching a porous film is provided. The method includes supplying a first gas into a processing chamber of a plasma processing apparatus in which an object to be processed including a porous film is accommodated, and generating a plasma of a second gas for etching the porous film in the processing chamber. The first gas is a processing gas having a saturated vapor pressure of less than or equal to 133.3 Pa at a temperature of a stage on which the object is mounted in the processing chamber, or includes the processing gas. In the step of supplying the first gas, no plasma is generated, and a partial pressure of the processing gas which is supplied into the processing chamber is set to be greater than or equal to 20% of the saturated vapor pressure.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: January 2, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Shigeru Tahara, Eiichi Nishimura, Mikhail Baklanov, Liping Zhang, Jean-Francois de Marneffe
  • Patent number: 9850402
    Abstract: The present invention provides chemical mechanical polishing compositions and methods for polishing a substrate comprising silicon dioxide and silicon nitride, which provide selective removal of SiN relative to silicon oxide (e.g., PETEOS) on patterned wafers. In one embodiment, a CMP method comprises abrading a surface of a substrate comprising SiN and silicon oxide with a CMP composition to remove at least some SiN therefrom. The CMP composition comprises, consists essentially of, or consists of a particulate abrasive (e.g., ceria) suspended in an aqueous carrier and containing a cationic polymer bearing pendant quaternized nitrogen-heteroaromatic moieties, wherein the composition has a pH of greater than about 3.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: December 26, 2017
    Assignee: Cabot Microelectronics Corporation
    Inventors: Dmitry Dinega, Sairam Shekhar, Renhe Jia, Daniel Mateja
  • Patent number: 9852924
    Abstract: A method for reducing sidewall roughness in an etch layer below a first mask with sidewall roughness in a processing chamber is provided. Sidewalls of the first mask are smoothed, comprising, flowing a processing gas into the processing chamber and forming the processing gas into an in situ plasma in the processing chamber with sufficient energy to sputter and smooth sidewall roughness of the first patterned mask. The etch layer is etched through the first patterned mask.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: December 26, 2017
    Assignee: Lam Research Corporation
    Inventors: Zhongkui Tan, Hua Xiang, Yiting Zhang, Qian Fu, Qing Xu
  • Patent number: 9847245
    Abstract: A method of filling cavities in a semiconductor structure during fabrication. A layer of a first material, e.g., a polysilazane, is deposited on the semiconductor, and subjected to a first thermal process to change its chemical composition, e.g., to change it to silicon dioxide. It is then etched back, and the cycle of deposition, and thermal processing is repeated. The etch-back may also be repeated in one or more of the cycles after the first cycle, and a second thermal process, that may increase the density of one or more of the deposited layers, may be performed in one or more of the cycles.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: December 19, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jorge A. Kittl, Kyungseok Oh, Sung Min Kim
  • Patent number: 9842750
    Abstract: Disclosed is a plasma processing device that provides an object to be treated with plasma treatment. A wafer as an object to be treated, which is attached on the upper surface of adhesive sheet held by a holder frame, is mounted on a stage. In a vacuum chamber that covers the stage therein, plasma is generated, by which the wafer mounted on the stage undergoes plasma treatment. The plasma processing device contains a cover member made of dielectric material. During the plasma treatment on the wafer, the holder frame is covered with a cover member placed at a predetermined position above the stage, at the same time, the wafer is exposed from an opening formed in the center of the cover member.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: December 12, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Tetsuhiro Iwai
  • Patent number: 9837273
    Abstract: A method of forming fine patterns of semiconductor devices is disclosed. The method comprises forming a hard mask layer on an etch target, which includes first and second regions. The hard mask layer may further have first and second preliminary mask patterns formed on the same. Furthermore, a spacer layer may be formed on the first and second preliminary mask patterns. The spacer layer and the first and second preliminary mask patterns may be partially removed to form first and second spacers on sidewalls of the first and second preliminary mask patterns, respectively. The second spacer in the second region may have a top surface higher than a top surface of the first spacer in the first region. The height differences between the spacers allow forming of first and second patterns in the first and second regions, and thereby forming fine patterns of semiconductor devices.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: December 5, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Sub Lee, Kyoung-Ha Eom, Ha-Neul Lee, Sang-Gyo Chung
  • Patent number: 9828677
    Abstract: A process for etching includes disposing an activating catalyst on a substrate; providing a vapor composition that includes an etchant oxidizer, an activatable etchant, or a combination thereof; contacting the activating catalyst with the etchant oxidizer; contacting the substrate with the activatable etchant; performing an oxidation-reduction reaction between the substrate, the activatable etchant, and the etchant oxidizer in a presence of the activating catalyst and the vapor composition; forming an etchant product that includes a plurality of atoms from the substrate; and removing the etchant product from the substrate to etch the substrate.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: November 28, 2017
    Assignee: THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCE
    Inventor: Owen Hildreth
  • Patent number: 9831096
    Abstract: A plasma processing method including disposing a wafer to be processed on a sample stage disposed in a processing chamber within a vacuum vessel, supplying an electric field using first high frequency power for plasma forming into the processing chamber and forming plasma, and supplying second high frequency power for bias potential forming to electrodes disposed within the sample stage and processing a film on a top surface of the wafer. At least the first or second high frequency power repeats a change of becoming a plurality of predetermined amplitudes for predetermined periods with a predetermined repetition period. In the processing of the film, supply of the high frequency power is changed by finally increasing a predetermined magnitude of amplitude among the repetition period, ratio of the period, and amplitude of the at least the first or second high frequency power, or first decreasing a predetermined magnitude of the amplitude.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: November 28, 2017
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Hiromitsu Terauchi, Tsutomu Iida, Yuuzou Oohirabaru
  • Patent number: 9824858
    Abstract: A de-coating method includes: exposing a coated body in which a coating made of an inorganic material is formed on a surface of the metal body to ion flows to peel off the coating from the metal body, wherein the coated body is placed at an ion flow-concentrated portion where two or more ion flows overlap each other, and is exposed to the ion flows without addition of a positive or negative bias to the coated body. As gases for use in generating ions from plasma, oxygen and CF4 that promote de-coating through a chemical reaction are preferably used in addition to Ar that performs de-coating under the physical action of ion collision and stabilizes plasma.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: November 21, 2017
    Assignee: SHINMAYWA INDUSTRIES, LTD.
    Inventors: Kensuke Uemura, G. Alexey Remnev
  • Patent number: 9818621
    Abstract: Embodiments described herein relate to methods for etching a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment to implant ions into a spacer material, performing an etching process on an implanted region of the spacer material, and repeating the inert plasma treatment and the etching process to form a predominantly flat top spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as pressure, may be controlled to influence a desired spacer profile.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: November 14, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Aurelien Tavernier, Qingjun Zhou, Tom Choi, Yungchen Lin, Ying Zhang, Olivier Joubert
  • Patent number: 9818582
    Abstract: Disclosed is a plasma processing method. The method includes forming a protective film on an inner wall surface of a processing container of a plasma processing apparatus; and executing a processing on a workpiece within the processing container. When forming the protective film, a protective film forming gas is supplied from an upper side of the space between the mounting table and the side wall of the processing container so that plasma is generated. When executing the processing, a workpiece processing gas is supplied from an upper side of the mounting table so that plasma is generated.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: November 14, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiraku Murakami, Nobutaka Sasaki, Shigeru Senzaki, Takanori Banse, Hiroshi Tsujimoto, Keigo Toyoda
  • Patent number: 9816010
    Abstract: A polishing composition of the present invention is to be used for polishing an object including a portion containing a high-mobility material and a portion containing a silicon material. The polishing composition comprises an oxidizing agent and abrasive grains having an average primary particle diameter of 40 nm or less. The polishing composition preferably further contains a hydrolysis-suppressing compound that bonds to a surface OH group of the portion containing a silicon material of the object to function to suppress hydrolysis of the portion containing a silicon material. Alternatively, a polishing composition of the present invention contains abrasive grains, an oxidizing agent, and a hydrolysis-suppressing compound. The polishing composition preferably has a neutral pH.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: November 14, 2017
    Assignee: FUJIMI INCORPORATED
    Inventors: Shuugo Yokota, Yasuyuki Yamato, Satoru Yarita, Tomohiko Akatsuka, Shuichi Tamada
  • Patent number: 9812996
    Abstract: There are provided a method for obtaining a distance between a base portion of an electrostatic chuck and a back surface of a target object and a method for neutralizing the electrostatic chuck based on the obtained distance. The electrostatic chuck has an upper surface including the base portion and a plurality of convex portions projecting from the base portion. The target object is mounted on apexes of the convex portions of the electrostatic chuck such that the back surface is in contact with the apexes. By processing a first wavelength spectrum output from a spectroscope based on reflected light of light emitted from a light source, a distance between the back surface of the target object and the base portion of the electrostatic chuck is calculated. Based on the calculated distance, a voltage is applied to the electrostatic chuck to neutralize the electrostatic chuck.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: November 7, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kenji Nagai, Yoshinobu Ooya
  • Patent number: 9803139
    Abstract: A method for selectively removing an aluminum-silicon coating fired on a surface of a metallic structure is described. The method includes the step of contacting the coating with molten potassium hydroxide (KOH), under conditions sufficient to remove the coating without substantially affecting the metallic surface. Methods for preparing a magnetic component are also described. They involve masking pre-selected regions of the surface of the component, using an aluminum-silicon coating that is fired onto the surface, prior to a nitriding step. The coating is then removed according to the procedure outlined herein.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: October 31, 2017
    Assignee: General Electric Company
    Inventors: Peter John Bonitatibus, Jr., Francis Johnson, Min Zou