Patents Examined by Allan Olsen
  • Patent number: 9695515
    Abstract: An example provides a method including providing a substrate including an area having a plurality of pores and etching the area of the substrate to remove the plurality of pores to form a recess in the substrate. In some examples, the recess may form, at least in part, a device.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: July 4, 2017
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Roger A. McKay, Jr., Patrick Sadik
  • Patent number: 9691629
    Abstract: Compositions useful for the selective removal of silicon nitride materials relative to polysilicon, silicon oxide materials and/or silicide materials from a microelectronic device having same thereon. The removal compositions include fluorosilicic acid, silicic acid, and at least one organic solvent. Typical process temperatures are less than about 100° C. and typical selectivity for nitride versus oxide etch is about 200:1 to about 2000:1. Under typical process conditions, nickel-based silicides as well as titanium and tantalum nitrides are largely unaffected, and polysilicon etch rates are less than about 1 ? min?1.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: June 27, 2017
    Assignee: Entegris, Inc.
    Inventors: Emanuel I. Cooper, Eileen Sparks, William R. Bowers, Mark A. Biscotto, Kevin P. Yanders, Michael B. Korzenski
  • Patent number: 9669514
    Abstract: Polishing systems and methods for polishing a substrate are provided. The polishing system includes a polishing assembly having a platen and a polishing pad over the platen. The polishing system also includes a substrate carrying assembly configured to engage a substrate to the polishing pad. The polishing system further includes a thickness sensing assembly configured to monitor a thickness of the polishing pad.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: June 6, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Jiun-Yu Lai, Ying-Hsiu Tsai, Wei-Chen Chang, Yi-Ching Chiou
  • Patent number: 9666461
    Abstract: A semiconductor processing device includes a first etching chamber, a second etching chamber, and an etching module. The etching module is adapted to interchangeably contain the first etching chamber or the second etching chamber for wafer etching. A semiconductor process using the semiconductor processing device is also provided.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yii-Cheng Lin, Chih-Ming Sun, Pinyen Lin
  • Patent number: 9666441
    Abstract: A semiconductor device and method of manufacturing are presented in which features of reduced size are formed using an irradiated mask material. In an embodiment a mask material that has been irradiated with charged ions is utilized to focus a subsequent irradiation process. In another embodiment the mask material is irradiated in order to reshape the mask material and reduce the size of openings formed within the mask material. Through such processes the limits of photolithography may be circumvented and smaller feature sizes may be achieved.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Heng Kao, Samuel C. Pan, Chi-Wen Liu, Miin-Jang Chen, Po-Shuan Yang
  • Patent number: 9666446
    Abstract: An etching method includes generating a plasma from a hydrogen-containing gas and a fluorine-containing gas with high-frequency electric power for plasma generation. A first film including a silicon oxide film and a silicon nitride film is etched with the generated plasma in an environment at a temperature lower than or equal to ?30° C. The first etch rate of first etching that etches the first film and the second etch rate of second etching that etches a second film having a structure different from the structure of the first film are controlled, so that the difference between the first etch rate and the second etch rate is within ±20% of the first etch rate.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: May 30, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Sho Tominaga, Wataru Takayama, Yoshiki Igarashi
  • Patent number: 9659789
    Abstract: An etching method is provided. In the etching method, a temperature of a chiller configured to cool a pedestal is controlled so as to become ?20 degrees C. or lower. Plasma is generated from a hydrogen-containing gas and a fluoride-containing gas supplied from a gas supply source by supplying first high frequency power having a first frequency supplied to the pedestal from a first high frequency power source. A silicon oxide film deposited on a substrate placed on the pedestal is etched by the generated plasma. Second high frequency power having a second frequency lower than the first frequency of the first high frequency power is supplied to the pedestal from a second high frequency power source in a static eliminating process after the step of etching the silicon oxide film.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: May 23, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Ryohei Takeda, Ryuichi Takashima, Yoshinobu Ooya
  • Patent number: 9648752
    Abstract: A process and device for removing a solid ink mask printed onto a substrate is disclosed. The substrate is bent around a bar set perpendicular to the substrate, causing the mask to flake off the substrate. The process permits fast removal of solid ink masks.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: May 9, 2017
    Assignee: XEROX CORPORATION
    Inventors: Paul McConville, Jeffrey J. Folkins, James R. Larson, Alexander J. Fioravanti
  • Patent number: 9638851
    Abstract: A method of manufacturing a wire grid polarizer includes: preparing a stamp having a nanostructure body at one surface and forming a mask layer with anisotropic vapor deposition at the one surface; forming a metal film on a substrate; transferring a mask layer of an upper portion of a nanostructure body in the mask layer onto the metal film; and patterning the metal film into metal lines by removing a portion that is not covered with the mask layer in the metal film with dry etching.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: May 2, 2017
    Assignee: KOREA INSTITUTE OF MACHINERY & MATERIALS
    Inventors: Jun-Ho Jeong, Junhyuk Choi, Dae-Guen Choi, So Hee Jeon, Ji Hye Lee, Joo Yun Jung, Soon-Hyoung Hwang, Sang Keun Sung
  • Patent number: 9631122
    Abstract: Described are chemical mechanical polishing compositions and methods of using the compositions for planarizing a surface of a substrate that contains tungsten, the compositions containing silica abrasive particles and cationic surfactant.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: April 25, 2017
    Assignee: Cabot Microelectronics Corporation
    Inventors: Kevin Dockery, Helin Huang, Lin Fu
  • Patent number: 9633862
    Abstract: A semiconductor manufacturing apparatus according to an embodiment includes a reactor, a mover, and a controller. The reactor houses an outer edge portion of a semiconductor substrate in inside thereof through a gap portion and scrapes the outer edge portion. The mover moves at least either the semiconductor substrate or end faces of the gap portion in a thickness direction of the semiconductor substrate to change distances in the thickness direction between the semiconductor substrate and the end faces of the gap portion. The controller controls a movement amount in the thickness direction of at least either the semiconductor substrate or the end faces of the gap portion according to a warp amount of the outer edge portion in the thickness direction.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: April 25, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi Kubota, Takashi Ohashi
  • Patent number: 9627221
    Abstract: A method of continuous fabrication of a layered structure on a substrate having a patterned recess, includes: (i) forming a dielectric layer on a substrate having a patterned recess in a reaction chamber by PEALD using a first RF power; (ii) continuously after completion of step (i) without breaking vacuum, etching the dielectric layer on the substrate in the reaction chamber by PEALE using a second RF power, wherein a pressure of the reaction chamber is controlled at 30 Pa to 1,333 Pa throughout steps (i) and (ii); a noble gas is supplied to the reaction chamber continuously throughout steps (i) and (ii); and the second RF power is higher than the first RF power.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: April 18, 2017
    Assignee: ASM IP Holding B.V.
    Inventors: Masaru Zaitsu, Atsuki Fukazawa, Hideaki Fukuda
  • Patent number: 9607855
    Abstract: An etching method includes: disposing a target substrate including a silicon and a silicon-germanium within a chamber; and performing both of selectively etching the silicon-germanium with respect to the silicon and selectively etching the silicon with respect to the silicon-germanium by varying ratios of F2 gas and NH3 gas in an etching gas that has a gas system including the F2 gas and the NH3 gas.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: March 28, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Nobuhiro Takahashi, Masashi Matsumoto, Ayano Hagiwara, Koji Takeya, Junichiro Matsunaga
  • Patent number: 9601343
    Abstract: In a semiconductor device manufacturing method, on a film to be processed, a mask material film is formed which has pattern openings for a plurality of contact patterns and connection openings for connecting adjacent pattern openings in such a manner that the connection between them is constricted in the middle. Then, a sidewall film is formed on the sidewalls of the individual openings in the mask material film, thereby not only making the diameter of the pattern openings smaller but also separating adjacent pattern openings. Then, the film to be processed is selectively etched with the mask material film and sidewall film as a mask, thereby making contact holes.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: March 21, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinya Watanabe
  • Patent number: 9593260
    Abstract: The present invention relates to a CMP slurry composition for polishing copper, comprising: polishing particles; a complexing agent; a corrosion inhibitor; and deionized water. The complexing agent comprises one or more organic acids selected from oxalic acid, malic acid, malonic acid, and formic acid, and glycine.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: March 14, 2017
    Assignee: CHEIL INDUSTRIES, INC.
    Inventors: Jong Il Noh, Dong Hun Kang, Tae Wan Kim, Jeong Hwan Jeong, Young Nam Choi, Chang Ki Hong
  • Patent number: 9581746
    Abstract: A method of manufacturing a wire grid polarizer includes: preparing a stamp having a nanostructure body at one surface and forming a mask layer with anisotropic vapor deposition at the one surface; forming a metal film on a substrate; transferring a mask layer of an upper portion of a nanostructure body in the mask layer onto the metal film; and patterning the metal film into metal lines by removing a portion that is not covered with the mask layer in the metal film with dry etching.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: February 28, 2017
    Assignee: KOREA INSTITUTE OF MACHINERY & MATERIALS
    Inventors: Jun-Ho Jeong, Junhyuk Choi, Dae-Guen Choi, So Hee Jeon, Ji Hye Lee, Joo Yun Jung, Soon-Hyoung Hwang, Sang Keun Sung
  • Patent number: 9583345
    Abstract: A method of fabricating a semiconductor device includes forming a first layer over a substrate and forming a second layer over the first layer. The method further includes patterning the second layer into a mask having one or more openings that expose portions of the first layer. The method further includes etching the first layer through the one or more openings via a first etching process, resulting in a patterned first layer. The first etching process includes forming a coating layer around both the mask and the patterned first layer while the first layer is being etched.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: February 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Yen Chen, Kuan-Nan Liu
  • Patent number: 9583317
    Abstract: A plasma processing method of performing a plasma process, using a plasma processing apparatus that includes a process chamber including a chromium (Cr) containing member and a mounting table placed in the process chamber, on a substrate on the mounting table, includes etching the substrate by plasma generated by a first gas containing bromine; after the etched substrate is carried out, forming a protection film by plasma generated by a second gas containing a CxFy gas (x?1, y?4) and an inert gas; and evacuating a reaction product containing chromium generated in the etching.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: February 28, 2017
    Assignee: Tokyo Electron Limited
    Inventor: Toshiharu Wada
  • Patent number: 9580809
    Abstract: An article includes a substrate; and a coating disposed on the substrate that includes a microporous layer; a gradient in a density of a volume of the microporous layer, and a plurality of dendritic veins that are anisotropically disposed in the coating. A process for forming a coating includes disposing an activating catalyst on a substrate; introducing an activatable etchant; introducing an etchant oxidizer, performing an oxidation-reduction reaction between the substrate, the activatable etchant, and the etchant oxidizer in a presence of the activating catalyst, the oxidation-reduction reaction occurring in a liquid medium including the activatable etchant; and the etchant oxidizer, forming an etchant product comprising atoms from the substrate; removing a portion of the etchant product from the substrate; and forming a dendritic vein in the substrate to form the coating, the dendritic vein being anisotropically disposed in the coating.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: February 28, 2017
    Assignee: THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCE
    Inventor: Owen Hildreth
  • Patent number: 9583359
    Abstract: Stable aqueous polishing compositions that can selectively polish silicon nitride (SiN) films and nearly stop (or polish at very low rates) on silicon oxide films are provided herein. The compositions comprise an anionic abrasive, a nitride removal rate enhancer containing a carboxyl or carboxylate group, water, and optionally, an anionic polymer. The synergistic combination of anionic (negatively charged) abrasives and the nitride removal rate enhancer provide beneficial charge interactions with the dielectric films during CMP, a high SiN rate and selectivity enhancement (over oxide), and stable colloidal dispersed slurries.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: February 28, 2017
    Assignee: Fujifilm Planar Solutions, LLC
    Inventors: Abhudaya Mishra, Luling Wang