Abstract: A blanket stop layer is conformally formed on a layer with a large step height. A first chemical mechanical polishing process is performed to remove the blanket stop layer atop the layer in the raised region. A second chemical mechanical polishing process is performed to planarize the wafer using the blanket stop layer as a stop layer when the layer is lower than or at a same level as the blanket stop layer or using the layer as a stop layer when the blanket stop layer is lower than or at a same level as the layer, or a selective dry etch is performed to remove the layer in the raised region. Thus, the layer in the raised region can be easily removed without occurrence of dishing in the non-raised region which is protected by the blanket stop layer.

Abstract: Methods and systems for temperature enhanced chucking and dechucking of resistive substrates in a plasma processing apparatus are described herein. In certain embodiments, methods and systems incorporate modulating a glass carrier substrate temperature during a plasma etch process to chuck and dechuck the carrier at first temperatures elevated relative to second temperatures utilized during plasma etching. In embodiments, one or more of plasma heat, lamp heat, resistive heat, and fluid heat transfer are controlled to modulate the carrier substrate temperature between chucking temperatures and process temperatures with each run of the plasma etch process.

Abstract: A method of fabricating a multilayer printed circuit board includes forming a first circuit-forming pattern and a via-forming pattern on a first carrier, and forming a first insulation layer; repeatedly forming inner circuit patterns and inner insulation layers over the first insulation layer by forming circuit-forming patterns and imprinting, and forming inner vias connecting the inner circuit patterns positioned on different insulation layers; forming a second circuit-forming pattern on a second carrier and inserting the first circuit-forming pattern and the second circuit-forming pattern respectively into the first insulation layer and a second insulation layer; removing the first carrier and the second carrier; forming circuit-forming grooves by removing the first circuit-forming pattern and the second circuit-forming pattern, and forming via-forming indentations connected with the circuit-forming grooves; and forming outer circuit patterns and outer vias by filling the circuit-forming grooves and the via

Abstract: A manufacturing method of a tip type probe includes the steps of: forming on a substrate an etching mask of a shape similar to a shape of a top surface of a truncated pyramid; forming the truncated pyramid by subjecting the substrate to isotropic etching using the etching mask as a mask member; stopping the isotropic etching when an area of the top surface reaches an area capable of generating near-field light; and forming a metal film on at least some of the side surfaces of the truncated pyramid by allowing film forming particles to enter into a space between the etching mask and the side surfaces and adhere onto the truncated pyramid. The directivity of the film forming particles is controlled so that the metal film has a thickness that is reduced gradually from a bottom of the truncated pyramid toward the top surface.

Abstract: Techniques for fabricating nanowire-based devices are provided. In one aspect, a method for fabricating a semiconductor device is provided comprising the following steps. A wafer is provided having a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer. Nanowires and pads are etched into the SOI layer to form a ladder-like structure wherein the pads are attached at opposite ends of the nanowires. The BOX layer is undercut beneath the nanowires. The nanowires and pads are contacted with an oxidizing gas to oxidize the silicon in the nanowires and pads under conditions that produce a ratio of a silicon consumption rate by oxidation on the nanowires to a silicon consumption rate by oxidation on the pads of from about 0.75 to about 1.25. An aspect ratio of width to thickness among all of the nanowires may be unified prior to contacting the nanowires and pads with the oxidizing gas.

Abstract: According to one embodiment, a semiconductor device manufacturing method includes collectively etching layers of a multilayered film including silicon layers and silicon oxide films alternately stacked on a semiconductor substrate. The etching gas of the etching contains at least two types of group-VII elements and one of a group-III element, a group-IV element, a group-V element, and a group-VI element, the energy of ions entering the semiconductor substrate when performing the etching is not less than 100 eV, and an addition ratio of the group-III element, the group-IV element, the group-V element, the group-VI element, and the group-VII element to the group-VII element is 0.5 (inclusive) to 3.0 (inclusive).

Abstract: A method of manufacturing a SiC substrate which has a first principal surface and a second principal surface, includes the step of removing, by a vapor phase etching process, at least a portion of a work-affected layer which is formed by mechanical flattening or cutting on the first principal surface of the SiC substrate.

Abstract: A method for producing surface features and an etch masking method. A combination is provided of a block copolymer and additional material. The block copolymer includes a first block of a first polymer covalently bonded to a second block of a second polymer. The additional material is miscible with the first polymer. A film is formed of the combination directly onto a surface of a first layer. Nanostructures of the additional material self-assemble within the first polymer block. The film of the combination and the first layer are etched. The nanostructures have an etch rate lower than an etch rate of the block copolymer and lower than an etch rate of the first layer. The film is removed and features remain on the surface of the first layer. Also included is an etch masking method where the nanostructures mask portions of the first layer from said etchant.

Abstract: The invention provides a systems and methods for creating Double Pattern (DP) structures on a patterned wafer in real-time using Dual Pattern Contact-Etch (DPCE) processing sequences and associated Contact-Etch-Multi-Input/Multi-Output (CE-MIMO) models. The DPCE processing sequences can include one or more contact-etch procedures, one or more measurement procedures, one or more contact-etch modeling procedures, and one or more contact-etch verification procedures. The CE-MIMO model uses dynamically interacting behavioral modeling between multiple layers and/or multiple contact-etch procedures. The multiple layers and/or the multiple contact-etch procedures can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created during Double Patterning (DP) procedures.

Abstract: Disclosed is a plasma processing device that provides an object to be treated with plasma treatment. A wafer as an object to be treated, which is attached on the upper surface of adhesive sheet held by a holder frame, is mounted on a stage. In a vacuum chamber that covers the stage therein, plasma is generated, by which the wafer mounted on the stage undergoes plasma treatment. The plasma processing device contains a cover member made of dielectric material. During the plasma treatment on the wafer, the holder frame is covered with a cover member placed at a predetermined position above the stage, at the same time, the wafer is exposed from an opening formed in the center of the cover member.

Abstract: A combination, composition and associated method for chemical mechanical planarization of a tungsten-containing substrate are described herein which afford tunability of tungsten/dielectric selectivity and low selectivity for tungsten removal in relation to dielectric material. Removal rates for both tungsten and dielectric are high and stability of the slurry (e.g., with respect to pH drift over time) is high.

Abstract: The process comprises the following steps: a) a first element (3) or a plurality of said first elements (3) is/are machined in a first silicon wafer (1) keeping said elements (3) joined together via material bridges (5); b) step a) is repeated with a second silicon wafer (2) in order to machine a second element (4), differing in shape from that of the first element (3), or a plurality of said second elements (4); c) the first and second elements (3, 4) or the first and second wafers (1, 2) are applied, face to face, with the aid of positioning means (6, 7); d) the assembly formed in step c) undergoes oxidation; and e) the parts (10) are separated form the wafers (1, 2). Micromechanical timepiece parts obtained according to the process.

Abstract: Methods for etching high-k material at high temperatures are provided. In one embodiment, a method etching high-k material on a substrate may include providing a substrate having a high-k material layer disposed thereon into an etch chamber, forming a plasma from an etching gas mixture including at least a halogen containing gas into the etch chamber, maintaining a temperature of an interior surface of the etch chamber in excess of about 100 degree Celsius while etching the high-k material layer in the presence of the plasma, and maintaining a substrate temperature between about 100 degree Celsius and about 250 degrees Celsius while etching the high-k material layer in the presence of the plasma.

Abstract: A method for chemical mechanical polishing of a substrate is provided, comprising: providing a substrate, wherein the substrate comprises polysilicon and at least one of silicon oxide and silicon nitride; providing a chemical mechanical polishing composition, comprising, as initial components: water; an abrasive; and an alkyl aryl polyether sulfonate compound, wherein the alkyl aryl polyether sulfonate compound has a hydrophobic portion having an alkyl group bound to an aryl ring and a nonionic acyclic hydrophilic portion having 4 to 100 carbon atoms; providing a chemical mechanical polishing pad with a polishing surface; moving the polishing surface relative to the substrate; dispensing the chemical mechanical polishing composition onto the polishing surface; and, abrading at least a portion of the substrate to polish the substrate; wherein at least some of the polysilicon is removed from the substrate; and, wherein at least some of the at least one of silicon oxide and silicon nitride is removed from the su

Abstract: A method for chemical mechanical polishing of a substrate is provided, comprising: providing a substrate, wherein the substrate comprises polysilicon, silicon oxide and silicon nitride; providing a chemical mechanical polishing composition, comprising, as initial components: water; an abrasive; an alkyl aryl polyether sulfonate compound, wherein the alkyl aryl polyether sulfonate compound has a hydrophobic portion having an alkyl group bound to an aryl ring and a nonionic acyclic hydrophilic portion having 4 to 100 carbon atoms; and a substance according to formula I wherein each of R1, R2, R3, R4, R5, R6 and R7 is a bridging group having a formula —(CH2)n—, wherein n is an integer selected from 1 to 10; providing a chemical mechanical polishing pad with a polishing surface; moving the polishing surface relative to the substrate; dispensing the chemical mechanical polishing composition onto the polishing surface; and, abrading at least a portion of the substrate to polish the substrate; wherein at least s

Abstract: A method of processing a substrate having a processing target layer and an organic film serving as a mask layer includes a mineralizing process of mineralizing the organic film. The mineralizing process includes an adsorption process for allowing a silicon-containing gas to be adsorbed onto a surface of the organic film; and an oxidation process for oxidizing the adsorbed silicon-containing gas to be converted into a silicon oxide film. A monovalent aminosilane is employed as the silicon-containing gas.

Abstract: Embodiments of the present invention relate to systems and methods for designing and manufacturing hard masks used in the creation of patterned magnetic media and, more particularly, patterned magnetic recording media used in hard disk drives (e.g., bit patterned media (BPM)). In some embodiments, the hard mask incorporates at least one layer of Ta (tantalum) and at least one layer of C (carbon) and is used during ion implantation of a pattern onto magnetic media. The hard mask can be fabricated with a high aspect ratio to achieve small feature sizes while maintaining its effectiveness as a mask, is robust enough to withstand the ion implantation process, and can be removed after the ion implantation process with minimal damage to the magnetic media.

Abstract: A method for chemical mechanical polishing of a substrate is provided, comprising: providing a substrate, wherein the substrate comprises polysilicon and at least one of silicon oxide and silicon nitride; providing a chemical mechanical polishing composition, comprising, as initial components: water; an abrasive; and an acyclic organosulfonic acid compound, wherein the acyclic organosulfonic acid compound has an acyclic hydrophobic portion having 6 to 30 carbon atoms and a nonionic acyclic hydrophilic portion having 10 to 300 carbon atoms; providing a chemical mechanical polishing pad with a polishing surface; moving the polishing surface relative to the substrate; dispensing the chemical mechanical polishing composition onto the polishing surface; and, abrading at least a portion of the substrate to polish the substrate; wherein at least some of the polysilicon is removed from the substrate; and, wherein at least some of the at least one of silicon oxide and silicon nitride is removed from the substrate.

Abstract: Fabrication methods disclosed herein provide for a nanoscale structure or a pattern comprising a plurality of nanostructures of specific predetermined position, shape and composition, including nanostructure arrays having large area at high throughput necessary for industrial production. The resultant nanostracture patterns are useful for nanostructure arrays, specifically sensor and catalytic arrays.

Abstract: Provided are a plasma processing apparatus and a plasma processing method, by which plasma damage is reduced during processing. At the time of performing desired plasma processing to a substrate (5), a process chamber (2) is supplied with an inert gas for carrying in and out the substrate (5), pressure fluctuation in the process chamber (2) is adjusted to be within a prescribed range, and plasma (20) of the inert gas supplied in the process chamber (2) is generated. The density of the plasma (20) in the transfer area of the substrate (5) is reduced by controlling plasma power to be in a prescribed range, and the substrate (5) is carried in and out to and from a supporting table (4).