Patents Examined by Allan Olsen
  • Patent number: 8758638
    Abstract: A method for the removal of copper oxide from a copper and dielectric containing structure of a semiconductor chip is provided. The copper and dielectric containing structure may be planarized by chemical mechanical planarization (CMP) and treated by the method to remove copper oxide and CMP residues. Annealing in a hydrogen (H2) gas and ultraviolet (UV) environment removes copper oxide, and a pulsed ammonia plasma removes CMP residues.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: June 24, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Weifeng Ye, Victor Nguyen, Mei-Yee Shek, Mihaela Balseanu, Li-Qun Xia, Derek R. Witty
  • Patent number: 8753527
    Abstract: A plasma etching method uses a plasma etching apparatus including a process chamber, a susceptor, a microwave supplying portion, a gas supplying portion, an evacuation apparatus, a bias electric power supplying portion that supplies alternating bias electric power to the susceptor, and a bias electric power control portion that controls the alternating bias electric power, wherein the bias electric power control portion controls the alternating bias electric power so that supplying and disconnecting the alternating bias electric power to the susceptor are alternately repeated to allow a ratio of a time period of supplying the alternating bias electric power with respect to a total time period of supplying the alternating bias electric power and disconnecting the alternating bias electric power to be 0.1 or more and 0.5 or less.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: June 17, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Tetsuya Nishizuka, Masahiko Takahashi, Toshihisa Ozu
  • Patent number: 8747682
    Abstract: According to one embodiment, a pattern formation method is disclosed. The method includes forming a plurality of regions on a foundation and the plurality of the regions correspond to different pattern sizes. The method includes separating each of a plurality of block copolymers from another one of the plurality of the block copolymers and segregating the each of the plurality of the block copolymers into a corresponding one of the regions. The method includes performing a phase separation of the each of the block copolymers of each of the regions. The method includes selectively removing a designated phase of each of the phase-separated block copolymers to form a pattern of the each of the block copolymers and the pattern has a different pattern size for the each of the regions.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: June 10, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Matsunaga, Tomoya Oori, Eishi Shiobara, Yukiko Sato, Yoshihisa Kawamura
  • Patent number: 8741163
    Abstract: A method is provided for producing a composite body made of at least one self-supporting surface and at least one element connected to the surface in a coating process. The method includes providing a negative mold including the at least one element of the composite body, selectively ablating a surface of the negative mold to be coated with the at least one self-supporting surface by a defined first thickness so that the at least one element stands out from the surface as a projection at least in areas, depositing one or more layers for forming the at least one self-supporting surface having a defined second thickness, wherein an elevation forms in the area of the projection of the at least one element, leveling the coated surface, wherein the elevation is removed, and selectively removing at least parts of the negative mold.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: June 3, 2014
    Inventor: Werner Suedes
  • Patent number: 8734656
    Abstract: A capacitor forming method includes forming an electrically conductive support material over a substrate, forming an opening through at least the support material to the substrate, and, after forming the opening, forming a capacitor structure contacting the substrate and the support material in the opening. The support material contains at least 25 at % carbon. Another capacitor forming method includes forming a support material over a substrate, forming an opening through at least the support material to the substrate, and, after forming the opening, forming a capacitor structure contacting the substrate and the support material in the opening. The support material contains at least 20 at % carbon. The support material has a thickness and the opening has an aspect ratio 20:1 or greater within the thickness of the support material.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: May 27, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Mark Kiehlbauch
  • Patent number: 8734663
    Abstract: A method for removing species from a substrate includes arranging a purge ring in a chamber proximate to a pedestal. The purge ring includes an inlet portion and an exhaust portion. The inlet portion defines an inlet plenum and an inlet baffle. The inlet baffle includes a continuous slit that is substantially continuous around a peripheral arc not less than about 270°. The exhaust portion includes an exhaust channel that is located substantially opposite the inlet baffle. The method further includes supplying ozone to the inlet plenum; at least partially defining a ring hole space having a periphery using the inlet portion and the exhaust portion; conveying gas from the inlet plenum into the ring hole space using the inlet baffle; conveying gas and other matter out of a purge space using the exhaust portion; and inhibiting deposition of material evolved from the substrate during curing using the purge ring.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: May 27, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Eugene Smargiassi, Stephen Yu-Hong Lau, George D. Kamian, Ming Xi
  • Patent number: 8728945
    Abstract: A method of uniformly shrinking hole and space geometries by forming sidewalls of an ALD film deposited at low temperature on a photolithographic pattern.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: May 20, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Steven Alan Lytle
  • Patent number: 8721918
    Abstract: A method for purifying fluoride etching solution is provided. The method begins with a reaction by hydroxide gas or solution to achieve a balance pH condition for the fluoride etching solution. Subsequently, the treated etching solution can be fed by constant velocity pump to a basic anion exchange resin column(s). The basic anion exchange resins remove various contaminants resulting in a saleable product to a wide range of industrial applications. The final solution is collected in a finished product storage tank. The degree of purification by basic anion exchange resin can be verified, if needed at all, thereby making ammonium fluoride (AF), ammonium bifluoride (ABF), anhydrous hydrogen fluoride (AHF) and fluoride mixture to meet the application of industries or different market's application. Further, the ion exchange resins can be regenerated as needed to extend the useful life and system capacity.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: May 13, 2014
    Assignee: Asia Union Electronical Chemical Corp.
    Inventors: Curtis Douglas Dove, Kehchyn Ho
  • Patent number: 8715782
    Abstract: In a surface processing method for processing a surface of a member made of silicon carbide (SiC) and having a fragmental layer on a surface thereof, the surface of the member having the fragmental layer is modified into a dense layer to reduce the number of particles generated from the surface of the member when the member is applied to a plasma processing apparatus. Here, the SiC of the surface of the member is recrystallized by heating the fragmental layer.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: May 6, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Naoyuki Satoh, Nobuyuki Nagayama, Keiichi Nagakubo
  • Patent number: 8703002
    Abstract: A plasma processing apparatus includes a first radio frequency (RF) power supply unit for applying a first RF power for generating a plasma from a processing gas to at least one of a first and a second electrode which are disposed facing each other in an evacuable processing chamber. The first RF power supply unit is controlled by a control unit so that a first phase at which the first RF power has a first amplitude for generating a plasma and a second phase at which the first RF power has a second amplitude for generating substantially no plasma are alternately repeated at predetermined intervals.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: April 22, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Tatsuo Matsudo, Shinji Himori, Noriaki Imai, Takeshi Ohse, Jun Abe, Takayuki Katsunuma
  • Patent number: 8691101
    Abstract: A method for manufacturing an ejection element substrate, which is provided with a flow-channel-forming member having an ejection orifice for ejecting a liquid and a liquid flow channel that is communicated with the ejection orifice, a substrate having a supply port for supplying the liquid to the liquid flow channel, and a filter structure formed in the bottom of the supply port, includes: forming the supply port by forming a through-hole by etching the substrate from a second face of the substrate on the side opposite to a first face of the substrate, on which the flow-channel-forming member is disposed; providing a resinous protection film on the side face and the bottom of the supply port; and forming a minute opening in the resinous protection film in the bottom of the supply port by carrying out a laser processing from the side of the second face.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: April 8, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Souta Takeuchi, Hirokazu Komuro, Sadayoshi Sakuma
  • Patent number: 8685263
    Abstract: Disclosed herein is a method of fabricating a cliché capable of preventing a printing roller from touching a bottom surface of the cliché. The method of fabricating the cliché includes forming a mask thin film pattern having a multilayer structure and a photoresist pattern on a base substrate, forming a resistant reinforcement inducing layer to cover the photoresist pattern, thereby transforming the photoresist pattern into a resistant reinforced photoresist pattern, and forming groove patterns having different depths from each other by etching the base substrate using the resistant reinforced photoresist pattern and the mask thin film pattern having the multilayer structure as masks.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: April 1, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Jun-Hee Lee, Jeong-Hoon Lee
  • Patent number: 8679359
    Abstract: The present invention is directed to a method and apparatus for etching various metals that may be used in semiconductor or integrated circuit processing through the use of non-halogen gases such as hydrogen, helium, or combinations of hydrogen and helium with other gases such as argon. In one exemplary embodiment of the present invention, in a reaction chamber, a substrate having a metal interconnect layer deposited thereon is exposed to a plasma formed of non-halogen gas. The plasma generated is maintained for a certain period of time to provide for a desired or expected etching of the metal. In some embodiments, the metal interconnect layer may be copper, gold or silver.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: March 25, 2014
    Assignee: Georgia Tech Research Corporation
    Inventors: Fangyu Wu, Dennis W. Hess, Galit Levitin
  • Patent number: 8679985
    Abstract: A dry etching method for a silicon nitride film capable of improving throughput is provided. A dry etching method for dry-etching a silicon nitride film 103 includes dry-etching the silicon nitride film 103 without generating plasma by using a processing gas containing at least a hydrogen fluoride gas (HF gas) and a fluorine gas (F2 gas), with respect to a processing target object 100 including the silicon nitride film 103.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: March 25, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Eiichi Nishimura, Yusuke Shimizu
  • Patent number: 8673785
    Abstract: A gas distribution system for supplying different gas compositions to a chamber, such as a plasma processing chamber of a plasma processing apparatus is provided. The gas distribution system can include a gas supply section, a flow control section and a switching section. The gas supply section provides first and second gases, typically gas mixtures, to the flow control section, which controls the flows of the first and second gases to the chamber. The chamber can include multiple zones, and the flow control section can supply the first and second gases to the multiple zones at desired flow ratios of the gases. The gas distribution system can continuously supply the first and second gases to the switching section and the switching section is operable to switch the flows of the first and second gases, such that one of the first and second process gases is supplied to the chamber while the other of the first and second gases is supplied to a by-pass line, and then to switch the gas flows.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: March 18, 2014
    Assignee: Lam Research Corporation
    Inventors: Zhisong Huang, Jose Tong Sam, Eric H. Lenz, Rajinder Dhindsa, Reza Sadjadi
  • Patent number: 8673165
    Abstract: Embodiment of the present invention provides a method of forming a semiconductor device in a sidewall image transfer process with multiple critical dimensions. The method includes forming a multi-level dielectric layer over a plurality of mandrels, the multi-level dielectric layer having a plurality of regions covering the plurality of mandrels, the plurality of regions of the multi-level dielectric layer having different thicknesses; etching the plurality of regions of the multi-level dielectric layer into spacers by applying a directional etching process, the spacers being formed next to sidewalls of the plurality of mandrels and having different widths corresponding to the different thicknesses of the plurality of regions of the multi-level dielectric layer; removing the plurality of mandrels in-between the spacers; and transferring bottom images of the spacers into one or more layers underneath the spacers.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sudharshanan Raghunathan, Sivananda Kanakasabapathy, Ryan O. Jung, Allen H Gabor, Sean D. Burns, Erin Catherine McLellan
  • Patent number: 8673788
    Abstract: A method of fabricating a semiconductor device is illustrated. A substrate having a plurality of trenches is provided. The plurality of trenches include trenches having differing widths. A first layer is formed on the substrate including in the plurality of trenches. Forming the first layer creates an indentation in the first layer in a region overlying a trench (e.g., wide trench). A second layer is formed in the indentation. The first layer is etched while the second layer remains in the indentation. The second layer may protect the region of indentation from further reduction in thickness. In an embodiment, the first layer is polysilicon and the second layer is BARC of photoresist.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: March 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hsiu Cheng, Shih-Hao Wu, Chih-Hsien Hsu, Chia-Chi Chung, Wei-Yueh Tseng
  • Patent number: 8669185
    Abstract: A method of tailoring conformality of a film deposited on a patterned surface includes: (I) depositing a film by PEALD or pulsed PECVD on the patterned surface; (II) etching the film, wherein the etching is conducted in a pulse or pulses, wherein a ratio of an etching rate of the film on a top surface and that of the film on side walls of the patterns is controlled as a function of the etching pulse duration and the number of etching pulses to increase a conformality of the film; and (III) repeating (I) and (II) to satisfy a target film thickness.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: March 11, 2014
    Assignee: ASM Japan K.K.
    Inventors: Shigeyuki Onizawa, Woo-Jin Lee, Hideaki Fukuda, Kunitoshi Namba
  • Patent number: 8668833
    Abstract: A method of forming a discrete nanostructured element at one or more predetermined locations on a substrate is presented. The method includes forming a mask member over the substrate. A window is formed in the mask member at each of one or more locations at which it is required to form the nanostructured element thereby to expose a portion of a surface of the substrate. A portion of the substrate exposed by the window at the one or more locations is removed to form one or more recesses in the substrate. The method further includes forming a layer of a nanostructure medium over a surface of the recess and annealing the structure thereby to form the nanostructured element in each of the one or more recesses. The nanostructured element includes a portion of the nanostructure medium and has an external dimension along at least two substantially orthogonal directions of less than substantially 100 nm.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: March 11, 2014
    Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd., National University of Singapore
    Inventors: Han Guan Chew, Fei Zheng, Wee Kiong Choi, Tze Haw Liew
  • Patent number: 8664120
    Abstract: In a semiconductor device manufacturing method, on a film to be processed, a mask material film is formed which has pattern openings for a plurality of contact patterns and connection openings for connecting adjacent pattern openings in such a manner that the connection between them is constricted in the middle. Then, a sidewall film is formed on the sidewalls of the individual openings in the mask material film, thereby not only making the diameter of the pattern openings smaller but also separating adjacent pattern openings. Then, the film to be processed is selectively etched with the mask material film and sidewall film as a mask, thereby making contact holes.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: March 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinya Watanabe