Abstract: Various embodiments of the present disclosure are directed towards a ferroelectric memory device. The ferroelectric memory device includes a pair of source/drain regions disposed in a semiconductor substrate. A gate dielectric is disposed over the semiconductor substrate and between the source/drain regions. A first conductive structure is disposed on the gate dielectric. A ferroelectric structure is disposed on the first conductive structure. A second conductive structure is disposed on the ferroelectric structure, where both the first conductive structure and the second conductive structure have an overall electronegativity that is greater than or equal to an overall electronegativity of the ferroelectric structure.

Abstract: A semiconductor structure is provided. The semiconductor structure includes nanostructures stacked over a substrate and spaced apart from one another, gate dielectric layers wrapping around the nanostructures respectively, nitride layers wrapping around the gate dielectric layers respectively, oxide layers wrapping around the nitride layers respectively, work function layers wrapping around the oxide layers respectively, and a metal fill layer continuously surrounding the work function layers.

Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate, depositing a metal-rich metal silicide layer on the source/drain region, depositing a silicon-rich metal silicide layer on the metal-rich metal silicide layer, and forming a contact plug on the silicon-rich metal silicide layer. This disclosure also describes a semiconductor device including a fin structure on a substrate, a source/drain region on the fin structure, a metal-rich metal silicide layer on the source/drain region, a silicon-rich metal silicide layer on the metal-rich metal silicide layer, and a contact plug on the silicon-rich metal silicide layer.

Abstract: A device includes plural semiconductor fins, a gate structure, an interlayer dielectric (ILD) layer, and an isolation dielectric. The gate structure is across the semiconductor fins. The ILD surrounds the gate structure. The isolation dielectric is at least between the semiconductor fins and has a thermal conductivity greater than a thermal conductivity of the ILD layer.

Abstract: Embodiments include an electronic system and methods of forming an electronic system. In an embodiment, the electronic system may include a package substrate and a die coupled to the package substrate. In an embodiment, the electronic system may also include an integrated heat spreader (IHS) that is coupled to the package substrate. In an embodiment the electronic system may further comprise a thermal interface pad between the IHS and the die. In an embodiment the die is thermally coupled to the IHS by a liquid metal thermal interface material (TIM) that contacts the thermal interface pad.

Abstract: A method may include thinning a silicon wafer to a particular thickness. The particular thickness may be based on a passband frequency spectrum of an adjustable optical filter. The method may also include covering a surface of the silicon wafer with an optical coating. The optical coating may filter an optical signal and may be based on the passband frequency spectrum. The method may additionally include depositing a plurality of thermal tuning components on the coated silicon wafer. The plurality of thermal tuning components may adjust a passband frequency range of the adjustable optical filter by adjusting a temperature of the coated silicon wafer. The passband frequency range may be within the passband frequency spectrum. The method may include dividing the coated silicon wafer into a plurality of silicon wafer dies. Each silicon wafer die may include multiple thermal tuning components and may be the adjustable optical filter.

Abstract: A method of fabricating a display device includes forming a circuit layer on a base layer, forming a first preliminary electrode and a second preliminary electrode on the circuit layer, forming a photoresist layer on the first preliminary electrode and the second preliminary electrode, patterning the photoresist layer to form a photoresist pattern, treating a region of each of the first preliminary electrode and the second preliminary electrode to form a first electrode and a second electrode having regions of lower and higher electrical resistance, and disposing a light-emitting element on the first electrode and the second electrode at regions having lower electrical resistance.

Abstract: A method for removing boron is provided, which includes (a) mixing a carbon source material and a silicon source material in a chamber to form a solid state mixture, (b) heating the solid state mixture to a temperature of 1000° C. to 1600° C., and adjusting the pressure of the chamber to 1 torr to 100 torr. The method also includes (c) conducting a gas mixture of a first carrier gas and water vapor into the chamber to remove boron from the solid state mixture, and (d) conducting a second carrier gas into the chamber.

Abstract: Methods and devices are described herein for random cut patterning. A first metal line and a second metal line are formed within a cell of a substrate and extend in a vertical direction. A third metal line and a fourth metal line are formed within the cell and are perpendicular to the first metal line and the second metal line, respectively. A first circular region at one end of the first metal line is formed using a first patterning technique and a second circular region at one end of the second metal line is formed using a second patterning technique. The first circular region is laterally extended using a second patterning technique to form the third metal line and the second circular region is laterally extended using the second patterning technique to form the fourth metal line.

Abstract: In a described example, an apparatus includes: a package substrate including a die pad configured for mounting a semiconductor die, a first lead connected to the die pad, and a second lead and a third lead; and a semiconductor die including a temperature sensor mounted on the die pad. The semiconductor die includes a first metallization layer being a metallization layer closest to the active surface of the semiconductor die, and successive metallization layers overlying the previous metallization layer, the metallization layers including a respective conductor layer in a dielectric material for the particular metallization layer and conductive vias; and the temperature sensor formed of the conductor layer in an uppermost metallization layer and coupled to the second lead and to the third lead. The semiconductor die includes a high voltage ring formed in the uppermost metallization layer, spaced from and surrounding the temperature sensor.

Abstract: A method of fabricating a display device includes forming a circuit layer on a base layer, forming a first preliminary electrode and a second preliminary electrode on the circuit layer, forming a photoresist layer on the first preliminary electrode and the second preliminary electrode, patterning the photoresist layer to form a photoresist pattern, treating a region of each of the first preliminary electrode and the second preliminary electrode to form a first electrode and a second electrode having regions of lower and higher electrical resistance, and disposing a light-emitting element on the first electrode and the second electrode at regions having lower electrical resistance.

Abstract: A semiconductor structure includes at least one stacked fin structure, a gate and a source/drain. At least one stacked fin structure is located on a substrate, wherein the stacked fin structure includes a first fin layer and a second fin layer, and a fin dielectric layer is sandwiched by the first fin layer and the second fin layer. The gate is disposed over the stacked fin structure. The source/drain is disposed directly on the substrate and directly on sidewalls of the whole stacked fin structure. The present invention provides a semiconductor process formed said semiconductor structure.

Abstract: The present disclosure relates to a heat sink pedestal including a composite material. The composite material may include at least one layer of a thermally conductive primary material and at least one layer of a thermally conductive secondary material. The composite material may include a conductivity ratio of lateral thermal conductivity (Kz) to planar thermal conductivity (Kx, Ky) of the composite material of at least 0. The heat sink pedestal may be conformable to a shape of a semiconductor chip.

Abstract: A quantum dot and its preparation method and application. The method includes the steps of forming a compound quantum dot core first, then adding a precursor of a metal element M2 to be alloyed into the reaction system containing the compound quantum dot core. The metal element M2 undergoes cation exchange with a metal element M1 in the existing compound quantum dot core, thereby forming a quantum dot with an alloy core. In this method, the distribution of alloyed components is not only adjusted by changing the feeding ratio of the metal elements and the non-metal elements, but also by a more real-time, more direct, and more precise adjustments through various reaction condition parameters of the actual reaction process, thereby achieving a more precise composition and energy level distribution control for alloyed quantum dots.

Abstract: This semiconductor device includes: a semiconductor substrate of a first conductive type; a first impurity layer of a second conductive type that is formed on a surface of the semiconductor substrate; a second impurity layer of the first conductive type that is formed to surround the first impurity layer on the surface of the semiconductor substrate; an insulating film that covers at least the first impurity layer; a first resistive element that is spiral-shaped and is provided on the insulating film; a second resistive element that is provided on an outer side of the first impurity layer in a planar view of the semiconductor substrate; and a first wiring that couples an end portion of the first resistive element on an outer peripheral side thereof and the second resistive element to each other.

Abstract: A power semiconductor module includes a plurality of power semiconductor chips. A housing accommodates the power semiconductor chips. A first module electrode on a first side of the housing electrically is connected to a first chip electrode of the power semiconductor chips. A second module electrode on a second side of the housing electrically is connected to a second chip electrode. A surge arrester arrangement with a surge arrester is accommodated in the housing such that a first electrode of the surge arrester arrangement is provided at the first side of the housing and a second electrode of the surge arrester arrangement is provided at the second side of the housing. The power semiconductor chips are arranged in an annular region in the housing and the surge arrester arrangement is arranged within the annular region.

Abstract: Disclosed embodiments include multiple thermal-interface material at the interface between an integrated heat spreader and a heat sink. A primary thermal-interface material has flow qualities and a secondary thermal-interface material has containment and adhesive qualities. The integrated heat spreader has a basin form factor that contains the primary thermal-interface material.

Abstract: A display device includes a substrate, a first electrode extending in a first direction on the substrate, a first partition wall extending in the first direction on a central portion of the first electrode, a second electrode extending in parallel with the first electrode on the substrate, a second partition wall extending in the first direction on a central portion of the second electrode, and a plurality of light-emitting diodes electrically connected between the first electrode and the second electrode.

Abstract: A support substrate has a mounting face with a metal heat transfer layer. Holes are provided to extend at least partially through the metal heat transfer layer. Metal heat transfer elements are disposed in the holes of the metal heat transfer layer of the support substrate. An electronic integrated circuit (IC) chip has a rear face that is fixed to the mounting face of the support substrate via a layer of adhesive material. The metal heat transfer elements disposed in the holes of the metal layer of the support substrate extend to protrude, relative to the mounting face of the support substrate, into the layer of adhesive material.

Abstract: A bus assembly includes a planar first bus, a second bus including a first planar bus section on the first bus and a second planar bus section connected to the first planar bus section and offset from the first planar bus section, and a third bus comprising a third planar bus section disposed between the first bus and the second planar bus section, and a fourth planar bus section connected to the third planar bus section, offset from third planar bus section, and disposed on the first planar bus section.