Patents Examined by Allan R. Wilson
  • Patent number: 11329035
    Abstract: Attach a smart chip to a carrier, and attach a memory chip to the carrier in communication with the smart chip. The memory chip has a larger footprint than the smart chip, overlies the smart chip, and is attached to the carrier by connections around the periphery of the smart chip. Removably attach an energy storage device (ESD) to the carrier and electrically connect the ESD to the carrier via a flex bridge.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: May 10, 2022
    Assignee: International Business Machines Corporation
    Inventors: Frank Robert Libsch, Ghavam G. Shahidi
  • Patent number: 11329138
    Abstract: Self-aligned gate endcap (SAGE) architectures having gate endcap plugs or contact endcap plugs, or both gate endcap plugs and contact endcap plugs, and methods of fabricating SAGE architectures having such endcap plugs, are described. In an example, a first gate structure is over a first of a plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A first gate endcap isolation structure is laterally between and in contact with the first gate structure and the second gate structure and has an uppermost surface co-planar with an uppermost surface of the first gate structure and the second gate structure. A second gate endcap isolation structure is laterally between and in contact with first and second lateral portions of the first gate structure and has an uppermost surface below an uppermost surface of the first gate structure.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Sairam Subramanian, Christopher Kenyon, Sridhar Govindaraju, Chia-Hong Jan, Mark Liu, Szuya S. Liao, Walid M. Hafez
  • Patent number: 11315906
    Abstract: A semiconductor arrangement includes at least two switching devices of a first type electrically coupled in parallel between a first terminal and a second terminal, and at least two switching devices of a second type electrically coupled in parallel between the second terminal and a third terminal. The switching devices of the first type and the switching devices of the second type are arranged in a power semiconductor module that has first and second longitudinal sides and first and second narrow sides. The switching devices of the first type and the switching devices of the second type are arranged next to each other in at least one row extending in a first horizontal direction that is parallel to the first and second longitudinal sides, such that within each of the at least one rows no more than two switching devices of the same type are arranged in direct succession.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: April 26, 2022
    Assignee: Infineon Technologies AG
    Inventor: Daniel Domes
  • Patent number: 11310913
    Abstract: The invention relates to a semiconductor component (2), comprising a semiconductor chip (3), a housing (5) and a connection point arrangement (10) having at least two rows (14, 16) of planar connection points (12), which are arranged on a bottom side of the housing (5) and can be electrically connected by means of connections to corresponding contacts of a contact arrangement having at least two rows, which contact arrangement is arranged on a printed circuit board, wherein the geometry of the contact arrangement corresponds to the geometry of the connection point arrangement (10), a first distance is specified between two adjacent first connection points (14A) of a first row (14) of the connection point arrangement (10) and a second distance is specified between two adjacent second connection points (16A) of a second row (16) of the connection point arrangement (10), and the second connection points (16A) of the second row (16) are offset to the first connection points (14A) of the first row (14).
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: April 19, 2022
    Assignee: Robert Bosch GmbH
    Inventors: Guenter Gera, Klaus Kosbi, Lars Vollmer, Matthias Lausmann
  • Patent number: 11309282
    Abstract: The present disclosure provides a method for manufacturing a semiconductor package. The method includes steps of providing semiconductor wafer having a plurality of device chips disposed thereon, wherein each of the plurality of device chips has an active area and an inactive area arranged around the active area; forming a plurality of the openings, wherein each of the plurality of openings is formed in a back surface of the semiconductor wafer and forms an opening into the inactive area; and disposing a protecting material within the openings and over the back surface of the semiconductor wafer.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: April 19, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 11302609
    Abstract: Radio frequency (RF) power dies having flip-chip architectures are disclosed, as are power amplifier modules (PAMs) containing such RF power dies. Embodiment of the PAM include a module substrate and an RF power die, which is mounted to a surface of the module substrate in an inverted orientation. The RF power die includes, in turn, a die body having a frontside and an opposing backside, a transistor having active regions formed in the die body, and a frontside layer system formed over the die body frontside. The frontside layer system contains patterned metal layers defining first, second, and third branched electrode structures, which are electrically coupled to the active regions of the transistor. A frontside input/output interface is formed in an outer terminal portion of the frontside layer system and contains first, second, and third bond pads electrically coupled to the first, second, and third branched electrode structures, respectively.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: April 12, 2022
    Assignee: NXP USA, Inc.
    Inventors: Ibrahim Khalil, Charles John Lessard, Jeffrey Kevin Jones
  • Patent number: 11302634
    Abstract: Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Lifang Xu, Jian Li, Graham R. Wolstenholme, Paolo Tessariol, George Matamis, Nancy M. Lomeli
  • Patent number: 11302599
    Abstract: A heat dissipation device may be formed as a thermally conductive structure having at least one thermal isolation structure extending at least partially through the thermally conductive structure. The heat dissipation device may be thermally connected to a plurality of integrated circuit devices, such that the at least one thermal isolation structure is positioned between at least two integrated circuit devices. The heat dissipation device allows for heat transfer away from each of the plurality of integrated circuit devices, such as in a z-direction within the thermally conductive structure, while substantially preventing heat transfer in either the x-direction and/or the y-direction within the thermally isolation structure, such that thermal cross-talk between integrated circuit devices is reduced.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: April 12, 2022
    Assignee: Intel Corporation
    Inventors: Feras Eid, Adel Elsherbini, Johanna Swan
  • Patent number: 11289390
    Abstract: Provided with an insulation circuit board in which a circuit layer is joined to one side of a ceramic substrate and a metal layer made of aluminum or aluminum alloy is joined to the other side of the ceramic substrate, and a heat sink joined to the metal layer; the heat sink has a first metal layer made of copper joined to the metal layer, a ceramic board material joined to the first metal layer at an opposite side to the metal layer, and a second metal layer made of copper or copper alloy joined to an opposite side of the ceramic board material to the first metal layer; and a thickness T1 of the first metal layer is 0.3 mm to 3.0 mm inclusive and equal to or more than a thickness T2 of the second metal layer.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: March 29, 2022
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Ryohei Yumoto, Tomoya Oohiraki, Takeshi Kitahara, Yoshiyuki Nagatomo
  • Patent number: 11289399
    Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a substrate, a semiconductor package, a thermal conductive gel, a thermal conductive film, and a heat spreader. The semiconductor package has an uneven top surface. The thermal conductive gel covers the uneven top surface of the semiconductor package. The thermal conductive film is over the uneven top surface of the semiconductor package. A thermal conductivity of the thermal conductive film is higher than a thermal conductivity of the thermal conductive gel. The heat spreader is disposed over the thermal conductive film.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pu Wang, Chin-Fu Kao, Szu-Wei Lu
  • Patent number: 11282770
    Abstract: A leadless packaged semiconductor device includes a metal substrate having at least a first through-hole aperture having a first outer ring and a plurality of cuts through the metal substrate to define spaced apart metal pads on at least two sides of the first through-hole aperture. A semiconductor die that has a back side metal (BSM) layer on its bottom side and a top side with circuitry coupled to bond pads is mounted top side up on the first outer ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the first through-hole aperture that provides a die attachment that fills a bottom portion of the first through-hole aperture. Bond wires are between metal pads and the bond pads. A mold compound is also provided including between adjacent ones of the metal pads.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: March 22, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Stassen Cook, Nazila Dadvand, Sreenivasan Koduri
  • Patent number: 11282792
    Abstract: A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the sec
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: March 22, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Kun Jee, Hae-Jung Yu, Sangwon Kim, Un-Byoung Kang, Jongho Lee, Dae-Woo Kim, Wonjae Lee
  • Patent number: 11276649
    Abstract: Devices and methods are provided in which a magnetic sensitive semiconductor chip, such as a magnetoresistive random-access memory (MRAM) chip, is shielded from magnetic interference by a magnetic shielding layer. A device includes a housing that defines an exterior surface. A semiconductor chip is disposed within the housing, and the semiconductor chip is spaced apart from the exterior surface of the housing. A magnetic shielding layer is spaced apart from the semiconductor chip by a distance less than 5 mm.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: March 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Tien-Wei Chiang, Chia-Hsiang Chen, Meng-Chun Shih, Ching-Huang Wang
  • Patent number: 11276624
    Abstract: A semiconductor device includes: a semiconductor substrate; a power device formed in the semiconductor substrate; a metal bilayer formed over the semiconductor substrate, the metal bilayer including a discontinuous metal layer formed on and in contact with a continuous base metal layer; and one or more contact pads formed in the metal bilayer or in a metallization layer above the metal bilayer. The discontinuous metal layer includes a plurality of metal blocks which are laterally spaced apart from one another and which form a heat sink structure over the power device. The continuous base metal layer is configured to laterally spread heat energy from the power device to the plurality of metal blocks. Methods of producing the semiconductor device are also described.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: March 15, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Michael Nelhiebel, Heiko Assmann, Olaf Heitzsch, Jakob Kriz, Sven Lanzerstorfer, Rainer Pelzer, Werner Robl, Bernhard Weidgans, Johannes Zechner
  • Patent number: 11264318
    Abstract: Provided is a semiconductor device free from chipping of a thin semiconductor element during transportation. The semiconductor device includes: a thin semiconductor element including a front-side electrode on the front side of the semiconductor element, and including a back-side electrode on the back side of the semiconductor element; a metallic member formed on at least one of the front-side electrode and the back-side electrode, the metallic member having a thickness equal to or greater than the thickness of the semiconductor element; and a resin member in contact with the lateral side of the metallic member and surrounding the periphery of the metallic member, with a part of the front side of the semiconductor element being exposed.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: March 1, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yoshinori Yokoyama, Jun Fujita, Toshiaki Shinohara, Hiroshi Kobayashi
  • Patent number: 11257934
    Abstract: A method of forming a semiconductor structure includes forming a substrate, the substrate having a first portion with a first height and second recessed portions with a second height less than the first height. The method also includes forming embedded source/drain regions disposed over top surfaces of the second recessed portions of the substrate, and forming one or more fins from a portion of the substrate disposed between the embedded source/drain regions, the one or more fins providing channels for fin field-effect transistors (FinFETs). The method further includes forming a gate stack disposed over the one or more fins, and forming inner oxide spacers disposed between the gate stack and the source/drain regions.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: February 22, 2022
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, ChoongHyun Lee, Shogo Mochizuki
  • Patent number: 11239147
    Abstract: In some embodiments, a semiconductor device includes a semiconductor die including a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a metallization structure located on the first surface. The metallization structure includes a first conductive layer on the first surface, a first insulating layer on the first conductive layer, a second conductive layer on the first insulating layer, a second insulating layer on the second conductive layer and a third conductive layer on the second insulting layer. The third conductive layer includes at least one source pad electrically coupled to the source electrode, at least one drain pad electrically coupled to the drain electrode and at least one gate pad electrically coupled to the gate electrode.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: February 1, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Blank, Gerhard Noebauer
  • Patent number: 11239151
    Abstract: A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: February 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: In-gyum Kim, Ha-young Kim, Tae-joong Song, Jong-hoon Jung, Gi-young Yang, Jin-young Lim
  • Patent number: 11239271
    Abstract: An imaging device includes a plurality of light-receiving elements arranged in a two-dimensional matrix shape. Each of the light-receiving elements includes a first electrode, a photoelectric conversion layer, and a second electrode. The photoelectric conversion layer has a laminated structure in which a first compound semiconductor layer having a first conductivity type and a second compound semiconductor layer having a second conductivity type that is a reverse conductivity type to the first conductivity type are laminated from a side of the first electrode. The second compound semiconductor layer has been removed in a region between the light-receiving elements. The first electrode and the first compound semiconductor layer are shared by the light-receiving elements. An impurity concentration of a first compound semiconductor layer near the first electrode is lower than that of a first compound semiconductor layer near the second compound semiconductor layer.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: February 1, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Shiro Uchida, Akiko Honjo, Tomomasa Watanabe, Hideshi Abe
  • Patent number: 11239312
    Abstract: The present invention is directed to a semiconductor chip comprising a high voltage device and a low voltage device disposed thereon. The chip may be formed in several different configurations. For example, the semiconductor chip may include a NPN bipolar transistor, PNP bipolar transistor, a diode, an N channel DMOS transistor and the like. the first doped well being configured as a base of the DMOS transistor, a P channel DMOS transistor and the like. These and other embodiments are described in further detail below.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: February 1, 2022
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventor: Hideaki Tsuchiko