Patents Examined by Allan R. Wilson
  • Patent number: 11004803
    Abstract: A method includes placing a plurality of functional dies over a carrier, placing a plurality of dummy dies over the carrier, encapsulating the plurality of functional dies and the plurality of dummy dies in an encapsulant, and forming redistribution lines over and interconnecting the plurality of functional dies. The redistribution lines, the plurality of functional dies, the plurality of dummy dies, and the encapsulant in combination form a reconstructed wafer. The plurality of functional dies are in a center region of the reconstructed wafer, and the plurality of dummy dies are in a peripheral region of the reconstructed wafer, with the peripheral region encircling the center region. The reconstructed wafer is de-bonded from the carrier. The reconstructed wafer is bonded to a package component selected from the group consisting essentially of an interposer, a package substrate, a printed circuit board, a thermal module, and combinations thereof.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu
  • Patent number: 10998366
    Abstract: An image sensing apparatus includes a first substrate structure, a second substrate structure, and a memory chip. The first substrate structure includes a pixel region having a photoelectric conversion element. The second substrate structure includes a first surface connected to the first substrate structure and a second surface opposite the first surface, and also includes a circuit region to drive the pixel region. The memory chip is mounted on the second surface of the second substrate structure. The first substrate structure and the second substrate structure are electrically connected by first connection vias passing through the first substrate structure. The second substrate structure and the memory chip are electrically connected by second connection vias passing through a portion of the second substrate structure. The first connection vias and the second connection vias are at different positions on a plane.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: May 4, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung Hyun Yoon, Doo Won Kwon, Kwan Sik Kim, Tae Young Song, Min Jun Choi
  • Patent number: 10985202
    Abstract: Provided is a solid-state imaging apparatus, an electronic device, and a driving method for obtaining an output signal irrespective of temperature-induced changes in characteristics. The solid-state imaging apparatus includes a pixel array section including a first pixel that has a first photoelectric converting section and obtains an output signal with logarithmic characteristics, and a second pixel that obtains a temperature detection signal for detecting temperature, the first and the second pixels being arranged in a matrix pattern, and a correcting section that corrects the output signal on the basis of temperature information obtained from the temperature detection signal.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: April 20, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Yoshiaki Tashiro
  • Patent number: 10985296
    Abstract: Embodiments of a display device including barrier layer coated quantum dots and a method of making the barrier layer coated quantum dots are described. Each of the barrier layer coated quantum dots includes a core-shell structure and a hydrophobic barrier layer disposed on the core-shell structure. The hydrophobic barrier layer is configured to provide a distance between the core-shell structure of one of the quantum dots with the core-shell structures of other quantum dots that are in substantial contact with the one of the quantum dots. The method for making the barrier layer coated quantum dots includes forming reverse micro-micelles using surfactants and incorporating quantum dots into the reverse micro-micelles. The method further includes individually coating the incorporated quantum dots with a barrier layer and isolating the barrier layer coated quantum dots with the surfactants of the reverse micro-micelles disposed on the barrier layer.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: April 20, 2021
    Assignee: Nanosys, Inc.
    Inventors: Jason Hartlove, Veeral Hardev, Shihai Kan, Jian Chen, Jay Yamanaga, Christian Ippen, Wenzhuo Guo, Charles Hotz, Robert Wilson
  • Patent number: 10985144
    Abstract: Disclosed is a light emitting apparatus including: first and second substrates having light transmissive property and flexibility arranged to face each other; a plurality of light emitting element groups arranged along a predetermined straight line between the first and second substrates and each of the light emitting element groups includes a first light emitting element and a second light emitting element; and a conductor pattern formed on the first substrate and including respective individual line patterns individually connected to the first and second light emitting elements and a common line pattern commonly connected to the first and second light emitting elements. The individual line patterns are routed to one side and the other side of the straight line centered on at least a part of the common line pattern.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: April 20, 2021
    Assignee: Toshiba Hokuto Electronics Corporation
    Inventor: Tomotsugu Jingi
  • Patent number: 10978434
    Abstract: A system-in-package includes a package substrate that at least partially surrounds an embedded radio-frequency integrated circuit chip and a processor chip mated to a redistribution layer. A wide-band phased-array antenna module is mated to the package substrate with direct interconnects from the radio-frequency integrated circuit chip to antenna patches within the antenna module. Additionally, fan-out antenna pads are also coupled to the radio-frequency integrated circuit chip.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Boon Ping Koh, Kooi Chi Ooi
  • Patent number: 10978621
    Abstract: A light emitting element, used behind a display, comprises LED chips emitting blue light and separated red and green phosphor layers on the LED chip, the layers receiving the emitted blue light and respectively converting the same into precise colors for the display. A portion of the light directly from the LED chip is also combined with the converted light and passed on as lighting for the display. Partial absorption of green light by the red phosphor and red light by the green phosphor, occurring when the red and green phosphor layers are overlapped, is avoided. Light conversion efficiency of the green and red phosphor layers is thereby improved. A light emitting assembly, a display device, and a method for making the light emitting assembly are also disclosed.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: April 13, 2021
    Assignees: Interface Technology (ChengDu) Co., Ltd., INTERFACE OPTOELECTRONICS (SHENZHEN) CO., LTD., GENERAL INTERFACE SOLUTION LIMITED
    Inventors: Syun-Long Ye, Wen-Hsiao Huang, Ta-Jen Huang
  • Patent number: 10968096
    Abstract: Microelectromechanical sensor with an out-of-plane detection has a cross sensitivity in a first direction in the plane with a value of ST, the sensor comprising a support, a mass suspended from the support by beams stressed by bending, in such a way that the inertial mass is capable of moving with respect to the support about an axis of rotation contained in a plane of the sensor, a stress gauge suspended between the mass and the support. The bending beams have a dimension tf in the out-of-plane direction and the mass has a dimension tM in the out-of-plane direction such that t f = 3 4 ? ( t M - 2 ? l arm ? S T ) . Larm is the distance between the centre of gravity of the mass and the centre of the bending beams projected onto the first direction.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: April 6, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Loic Joet, Patrice Rey
  • Patent number: 10971375
    Abstract: A method, comprises: providing a laminar support member, having a front surface, arranging on the front surface at least one semiconductor die having a front surface and a back surface, with the back surface thereof towards the front surface of the support member and with the front surface thereof having die pads, arranging at the front surface of the support member sidewise of the at least one semiconductor die a plurality of electrically-conductive bodies, the electrically-conductive bodies arranged at respective recesses in the support member, wherein the electrically-conductive bodies protrude from the plane away from the front surface of the support member, providing a filling of molding material over the laminar support member between the at least one semiconductor die and the electrically-conductive bodies, and providing electrically-conductive lines between selected ones of the die pads of the semiconductor die and selected ones of the plurality of electrically-conductive bodies.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: April 6, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Federico Giovanni Ziglioli
  • Patent number: 10971523
    Abstract: The present disclosure provides a pixel array and a fabrication method thereof. The pixel array includes a plurality of gate lines and a plurality of data lines which are arranged intersected and insulated and a pixel unit disposed at a position where each of the plurality of gate lines and each of the plurality of data lines are intersected. The pixel unit includes a thin film transistor (TFT). The width-to-length ratios of channels of the TFTs are sequentially increased in such a manner that the width-to-length ratios of the channels of the TFTs in the pixel units positioned in a same row (and/or a same column) are sequentially increased along a scanning direction of the gate line coupled to gate electrodes of the TFTs in the same row (and/or along a data writing direction of the data line coupled to the source electrodes of the TFTs in the same column).
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: April 6, 2021
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Tongshang Su, Dongfang Wang, Jun Cheng, Jun Liu, Qinghe Wang, Guangyao Li, Liangchen Yan
  • Patent number: 10964776
    Abstract: This disclosure relates to a pixel defining structure, a display panel, a method of manufacturing the same, and a display device. The pixel defining structure includes: a first pixel defining layer with a first opening, located on a substrate, wherein the first pixel defining layer includes a first portion formed by a first hydrophilic-hydrophobic material and a second portion formed by a second hydrophilic-hydrophobic material, projections of the first portion and the second portion on a surface of the substrate are substantially not overlapped, a side surface of the first pixel defining layer facing the first opening includes a first side surface formed by the first hydrophilic-hydrophobic material and a second side surface formed by the second hydrophilic-hydrophobic material, and the first hydrophilic-hydrophobic material has a different hydrophilicity and hydrophobicity from that of the second hydrophilic-hydrophobic material.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: March 30, 2021
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Chunjing Hu, Wenjun Hou
  • Patent number: 10964913
    Abstract: A display device may include a hole, a display element, a switching element, a groove, a planarization layer, and a cover layer. The switching element may be electrically connected to the display element. The encapsulation layer may cover the display element. The groove may be located between the hole and the display element. A portion of the planarization layer may be located between a first edge of the planarization layer and a second edge of the planarization and may be located in the groove. The first edge of the planarization layer may be located closer to the display element than the second edge of the planarization layer. The cover layer may at least partially cover the first edge of the planarization layer.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: March 30, 2021
    Inventors: Dongjin Moon, Yeri Jeong, Inyoung Han
  • Patent number: 10957639
    Abstract: An electronic component includes a part incorporating a transistor provided with a control electrode and with first and second electrodes. The electronic component includes first, second, and third electrical connection terminals extending on a connection face of the part incorporating the transistor, the first electrical connection terminal being electrically linked with the first electrode, the second electrical connection terminal being electrically linked with the second electrode and the third electrical connection terminal being electrically linked with the control electrode. The electronic component includes a first set of electrically conductive fingers and a second set of electrically conductive fingers, the fingers of the first and second sets of fingers being interdigitated, at the level of the connection face, to form at least a part of a capacitive component. The fingers of the first set of fingers are electrically linked to the first electrical connection terminal.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: March 23, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Benoit Thollin, Thibault Catelain
  • Patent number: 10957812
    Abstract: Disclosed are a display device and a method of manufacturing a display device. The method of a display device according to an exemplary embodiment of the present disclosure includes: a first transferring step of transferring a plurality of LEDs disposed on a wafer onto a plurality of donors; and a second transferring step of transferring the plurality of LEDs transferred onto the plurality of donors onto a display panel, in which in the second transferring step, an area where one of the plurality of donors overlaps the display panel partially overlaps an area where the other one of the plurality of donors overlaps the display panel. Therefore, the plurality of LEDs having different wavelengths is uniformly transferred to reduce a boundary caused by the difference in wavelengths and improve color uniformity.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: March 23, 2021
    Assignee: LG Display Co., Ltd.
    Inventor: ChungHwan An
  • Patent number: 10957689
    Abstract: Provided is a semiconductor apparatus capable of enhancing the withstand voltage while suppressing the enlargement of the chip area. Provided is semiconductor apparatus including: a first terminal to which a high frequency signal is supplied; a second terminal from which the high frequency signal is output; first, second and third switch elements electrically connected in series between the first terminal and the second terminal; a first capacitor provided between the first terminal and a first node between the first switch element and the second switch element; and a second capacitor provided between the first terminal and a second node between the second switch element and the third switch element, in which the capacitance of the first capacitor is greater than the capacitance of the second capacitor.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: March 23, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Kenji Noguchi, Toshiyuki Koimori, Hiroaki Nagano, Masaya Uemura, Megumi Nakayama
  • Patent number: 10957832
    Abstract: A light emitting semiconductor (LES) device having desirable thermal performance characteristics is disclosed. The LES device includes an insulating substrate layer having a plurality of vias formed therein and at least one LES chip mounted on the insulating substrate layer, with each of the LES chips(s) including an active surface including a light emitting area configured to emit light therefrom and a back surface positioned on a top surface of the insulating substrate layer and including connection pads thereon. A conductor layer is positioned on a bottom surface of the insulating substrate layer and in the vias, the conductor layer in direct contact with the connection pads of the LES chip(s) so as to be electrically and thermally connected thereto. An encapsulant is positioned adjacent the top surface of the insulating substrate layer and surrounding at least part of the LES chip(s), the encapsulant comprising a light transmitting material.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: March 23, 2021
    Assignee: General Electric Company
    Inventors: Christopher James Kapusta, Risto Ilkka Sakari Tuominen, Kaustubh Ravindra Nagarkar
  • Patent number: 10950688
    Abstract: Provided herein is a module for packaging semiconductors comprising: at least one PDC comprising parallel internal electrodes of alternating polarity with a paraelectric dielectric between adjacent internal electrodes wherein the paraelectric dielectric has a permittivity above 10 to no more than 300; and wherein the PDC forms a capacitor couple with at least one semiconductor.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: March 16, 2021
    Assignee: KEMET Electronics Corporation
    Inventors: John Bultitude, Lonnie G. Jones, Allen Templeton, Philip M. Lessner
  • Patent number: 10950738
    Abstract: A chip package is provided. the chip package includes a substrate having an upper surface, a lower surface, and a sidewall surface that is at an edge of the substrate. The substrate includes a sensing device adjacent to the upper surface of the substrate to sense a light source. The chip package also includes a first color filter layer disposed on the upper surface of the substrate to shield the light source. The first color filter layer includes an opening, so that the first color filter layer surrounds the sensing device via the opening. In addition, the chip package includes a redistribution layer disposed on the lower surface of the substrate. A method of forming the chip package is also provided.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: March 16, 2021
    Assignee: XINTEC INC.
    Inventors: Shu-Ming Chang, Tsang-Yu Liu
  • Patent number: 10930592
    Abstract: A packaged assembly and a method of producing the packaged assembly is disclosed. The packaged assembly includes a redistribution layer (RDL), an integrated circuit (IC), one or more memory modules, and an interposer comprising a plurality of vias from a list of through-silicon-vias (TSVs), through-mold-via (TMVs), and plated-through-hold-via (PTHs). In some implementations, the IC is electrically and mechanically attached to a first side of the RDL. In some implementations, the one or more memory modules and the interposer are disposed on a second side of the RDL. The packaged assembly also includes a mold having a mold material encapsulating the IC, the one or more memory modules, the interposer, and the RDL to form the packaged assembly. In some implementations, the IC is electrically conductively connected an external circuit board via a series of electrical connections between the IC, the RDL, the vias, and the external circuit board.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: February 23, 2021
    Assignee: Google LLC
    Inventors: Nam Hoon Kim, Woon Seong Kwon, Teckgyu Kang
  • Patent number: 10930563
    Abstract: A method for fabricating a stacked nanosheet semiconductor device includes forming nanosheet stacks including alternating silicon layers and silicon germanium layers on a substrate. The method includes patterning a gate structure on the nanosheet stacks and forming a source and drain on the stacks. The method further includes growing a first epitaxial layer on the source and drain. The method includes etching an interlayer dielectric on the first epitaxial layer. The method includes etching a portion of the first epitaxial layer forming a channel and growing a second epitaxial layer and etching a portion of the interlayer etching a portion of the first liner, forming a pFET. The method includes forming an nFET. The method includes the pFET and the nFET being disposed adjacent to one another vertically and a drain of the pFET and a drain of the nFET being electrically connected.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: February 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Heng Wu, Peng Xu