Abstract: In an embodiment, a semiconductor package includes at least one die pad, a plurality of outer contacts, a first semiconductor device and a second semiconductor device. The second semiconductor device includes a first transistor device having a source electrode, a gate electrode, a drain electrode, a front surface, and a rear surface. A front metallization is positioned on the front surface and a rear metallization on the rear surface of the second semiconductor device. The front metallization includes a first power contact pad coupled to the source electrode and mounted on the at least one die pad. The rear metallization includes a second power contact pad electrically coupled to the drain electrode, and an auxiliary lateral redistribution structure electrically insulated from the second power contact pad and the drain electrode. The first semiconductor device is electrically coupled to the auxiliary lateral redistribution structure.

Abstract: An integrated circuit structure includes: a field-effect transistor including a semiconductor region including a semiconductor material having a bandgap less than or equal to that of silicon, a semiconductor source and a semiconductor drain, the semiconductor region being between the semiconductor source and the semiconductor drain, a gate electrode, a gate dielectric between the semiconductor region and the gate electrode, a source contact adjacent to the semiconductor source, and a drain contact adjacent to the semiconductor drain; and a resistive switch or a capacitor electrically connected to the drain contact. One of the source contact and the drain contact includes a threshold switching region, to be a selector for the resistive switch or the capacitor. In some embodiments, the threshold switching region includes a threshold switching oxide or a threshold switching chalcogenide, and the resistive switch or the capacitor is part of a resistive memory cell or capacitive memory cell.

Abstract: A device comprises an array comprising rows and columns of elevationally-extending transistors. An access line interconnects multiple of the elevationally-extending transistors along individual of the rows. The transistors individually comprise an upper source/drain region, a lower source/drain region, and a channel region extending elevationally there-between. The channel region comprises an oxide semiconductor. A transistor gate is operatively laterally-proximate the channel region and comprises a portion of an individual of the access lines. Intra-row-insulating material is longitudinally between immediately-intra-row-adjacent of the elevationally-extending transistors. Inter-row-insulating material is laterally between immediately-adjacent of the rows of the elevationally-extending transistors. At least one of the intra-row-insulating material and the inter-row-insulating material comprises void space. Other embodiments, including method embodiments, are disclosed.

Abstract: A heat sink for an integrated circuit chip. The heat sink includes a base plate and a plurality of fins connected to the base plate. The base plate includes a first segment, a second segment, and a third segment that are sequentially connected; and the first segment and the third segment extend obliquely upward relative to the second segment.

Abstract: The present disclosure describes a method to form a fin field effect transistor (finFET) and a nano-sheet transistor on a substrate. The method can include forming first and second vertical structures over a substrate, where each of the first and the second vertical structures can include a buffer region and a first channel layer formed over the buffer region. The method can further include disposing a masking layer over the first channel layer of the first and second vertical structures, removing a portion of the first vertical structure to form a first recess, forming a second channel layer in the first recess, forming a second recess in the second channel layer, and disposing an insulating layer in the second recess.

Abstract: A package structure and method of forming the same are provided. The package structure includes a die, a redistribution structure and a conductive pad. The redistribution structure is disposed on and electrically connected to the die. The redistribution structure includes a dielectric film, a conductive line, an adhesive layer and a conductive via. The dielectric film has a first surface and a second surface opposite to each other. The conductive line and the adhesive layer are located between the first surface of the dielectric film and the die. The conductive line is electrically connected to the die, and the adhesive layer laterally surrounds the conductive line. The conductive via penetrates through the dielectric film and the adhesive layer to electrically connect to the conductive line. The conductive pad is electrically connected to the die through the redistribution structure.

Abstract: The power converter includes a semiconductor module including a first semiconductor element and a second semiconductor element connected in series, a multilayer substrate including a first wire connected to a first signal terminal of the first semiconductor element, a second wire connected to a second signal terminal of the first semiconductor element, a third wire connected to a third signal terminal of the second semiconductor element, and a fourth wire connected to a fourth signal terminal of the second semiconductor element, a first external connection terminal to which the first wire and the second wire are connected, and a second external connection terminal to which the third wire and the fourth wire are connected, the first and third wires being formed on a first layer with an insulating region interposed therebetween, the second and fourth wires being formed on a second layer with an insulating region interposed therebetween.

Abstract: An electronic module comprises a sealing part 90, a rear surface-exposed conductor 10, 20, 30, a rear surface-unexposed conductor 40, 50 and a second connector 70 for electrically connecting an electronic element 15, 25 to the rear surface-unexposed conductor 40, 50. The rear surface-unexposed conductor 40, 50 is positioned on a front surface side compared with the rear surface-exposed part 12, 22, 32. The second connection tip part 72 is positioned on a rear surface side compared with the second connection base part 71. A distance H in a thickness direction between a rear surface side end part of the second connection base part 71 and a rear surface side end part of the second connection tip part 72 is larger than a width W of the second connection tip part 72 of the second connector 70.

Abstract: An embodiment of the present disclosure provides an array substrate, a display panel, and a display device, relating to the field of display technology. The array substrate includes a plurality of sub-pixel regions. The sub-pixel regions include at least one white sub-pixel region and a sub-pixel region adjacent to the white sub-pixel region. A signal line is disposed between the white sub-pixel region and the sub-pixel region adjacent thereto. At most a first data line is disposed between the white sub-pixel region and the adjacent sub-pixel region. The first data line is used to provide a data signal to a sub-pixel electrode in the white sub-pixel region. The signal line transmits a signal of a different type than the data signal.

Abstract: An object of the present invention is to provide a semiconductor nanoparticle exhibiting excellent air durability, a semiconductor nanoparticle-containing dispersion liquid containing the semiconductor nanoparticle, and a film containing the semiconductor nanoparticle. In the semiconductor nanoparticle of the present invention, zinc, sulfur, and indium are detected by energy dispersive X-ray analysis, and a molar ratio Zn/In of zinc to indium which is acquired by the energy dispersive X-ray analysis satisfies Expression (1a).

Abstract: A semiconductor package structure includes a base material, at least one semiconductor chip, an encapsulant, a depression structure, a redistribution layer and at least one conductive via. The semiconductor chip is disposed on the base material. The encapsulant is disposed on the base material and covers the at least one semiconductor chip. The encapsulant has an outer side surface. The depression structure is disposed adjacent to and exposed from of the outer side surface the encapsulant. The redistribution layer is disposed on the encapsulant. The conductive via is disposed in the encapsulant and electrically connects the semiconductor chip and the redistribution layer.

Abstract: A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes alternately stacking first semiconductor layers and second semiconductor layers over a substrate, patterning the first semiconductor layers and the second semiconductor layers into a fin structure, removing the first semiconductor layers of the fin structure thereby forming gaps between the second semiconductor layers of the fin structure, forming a gate dielectric layer wrapping around the second semiconductor layers, forming a barrier material on the gate dielectric layer. At least a portion of the barrier material is oxidized to form a first barrier oxide. The method for forming the semiconductor structure also includes etching away the first barrier oxide, forming a work function layer to wrap around the second semiconductor layers, and forming a metal fill layer over the work function layer.

Abstract: An integrated circuit chip includes a circuit structure, a grounding structure, a bonding layer between the circuit structure and the grounding structure. The circuit structure includes a first substrate, an FEOL structure, and a BEOL structure. The grounding structure includes a second substrate and a grounding conductive layer. The integrated circuit chip includes a first penetrating electrode portion connected to the grounding conductive layer based on extending through the first substrate, the FEOL structure, the BEOL structure, and the bonding layer such that the first penetrating electrode portion is isolated from direct contact with the integrated circuit portion in a horizontal direction extending parallel to an active surface of the first substrate. An integrated circuit package and a display device each include the integrated circuit chip.

Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a first ferromagnetic layer and a second ferromagnetic layer. A bottom electrode via overlies a substrate. A bottom electrode overlies the bottom electrode via. A data storage layer overlies the bottom electrode. The first ferromagnetic layer overlies the data storage layer and has a first magnetization pointing in a first direction. The second ferromagnetic layer overlies the bottom electrode via and has a second magnetization pointing in a second direction orthogonal to the first direct.

Abstract: A phase-change storage element including, in a first portion, a stack of amorphous layers, the thickness of each layer in the stack being smaller than or equal to 5 nm.

Abstract: An aluminum alloy member is made of an aluminum alloy having a Mg concentration set in a range of 0.4 mass % or more and 7.0 mass % or less and a Si concentration set to less than 1 mass %, the aluminum alloy member and a copper member are bonded to each other through solid-phase diffusion, and a compound layer made up of a first intermetallic compound layer that is disposed on the aluminum alloy member side and made of a ? phase of an intermetallic compound of Cu and Al, a second intermetallic compound layer that is disposed on the copper member side and made of a ?2 phase of an intermetallic compound of Cu and Al, and a Cu—Al—Mg layer provided between the first intermetallic compound layer and the second intermetallic compound layer is provided in a bonding interface between the aluminum alloy member and the copper member.

Abstract: A power module which includes a power semiconductor module chip, a driver chip and a charge storage element. The power semiconductor module chip is configured by forming an IGBT having a trench gate structure including a dummy trench gate, and a freewheeling diode for returning excess carrier of the emitter of the IGBT to the collector of the IGBT, in the same chip. The drive chip is used for driving the IGBT on/off. The power module is configured by packaging the power semiconductor module chip and the drive chip. The charge storage element that is connected between the gate and emitter of a dummy IGBT which can be pseudo-formed in order that the dummy trench gate be used in screening examinations.

Abstract: A static random access memory (SRAM) cell includes a four-contact polysilicon pitch (4Cpp) fin field effect transistor (FinFET) architecture including a first bit-cell and a second bit cell. The SRAM cell includes a first bit line and a first complementary bit line, wherein the first bit line and the first complementary bit line are shared by the first and second bit-cells of the SRAM cell. The SRAM cell includes a first word line connected to the first bit cell, and a second word line connected to the second bit cell.

Abstract: Provided is a display apparatus. The display apparatus includes an active area and a bezel area, the display apparatus comprising semiconductor patterns disposed in a third area of the bezel area, an insulating layer disposed on the semiconductor patterns and includes contact holes and dummy holes, a power supply electrode disposed in the third area of the bezel area, overlaps the semiconductor patterns with the insulating layer therebetween, and is connected to the semiconductor patterns through the contact holes, dummy gate lines disposed between the semiconductor patterns and the power supply electrode, overlap the semiconductor pattern to form a first compensation capacitance and overlap the power supply electrode to form a second compensation capacitance, and a dummy semiconductor patterns disposed in the third area of the bezel area, and are connected to the power supply electrode through the dummy holes.

Abstract: A display device includes a plurality of scan lines and a plurality of data lines; and a plurality of pixels connected with the scan lines and the data lines, wherein at least one pixel of the plurality of pixels includes a pixel circuit having at least one transistor, an insulating layer covering the pixel circuit, a first electrode disposed on the insulating layer and electrically connected to the pixel circuit, a second electrode disposed on the insulating layer and spaced apart from the first electrode, and a light-emitting element electrically connected to the first electrode and the second electrode.