Abstract: Embodiments related to transistors and integrated circuits having aluminum indium phosphide subfins and germanium channels, systems incorporating such transistors, and methods for forming them are discussed.

Abstract: A charger includes a thermal conductive plate for heat dissipation, and a transistor. The transistor includes a drain terminal of a first pulsating voltage level, and a source terminal of a second pulsating voltage level. The second pulsating voltage level is lower than the first pulsating voltage level. The source terminal is disposed closer to the thermal conductive plate than the drain terminal.

Abstract: The present invention provides an automated modular system and method for production of biopolymers including DNA and RNA. The system and method automates the complete production process for biopolymers. Modular equipment is provided for performing production steps with the individual modules arrange in a linear array. Each module includes a control system and can be rack mounted. One side of the array of modules provides connections for power, gas, vacuum and reagents and is accessible to technicians. On the other side of the array of modules a robotic transport system is provided for transporting materials between module interfaces. The elimination of the requirement for human intervention at multiple steps in the production process significantly decreases the costs of biopolymer production and reduces unnecessary complexity and sources of quality variation.

Abstract: A photoelectric conversion device includes a first semiconductor substrate including a photoelectric conversion unit for generating a signal charge in accordance with an incident light, and a second semiconductor substrate including a signal processing unit for processing an electrical signal on the basis of the signal charge generated in the photoelectric conversion unit. The signal processing unit is situated in an orthogonal projection area from the photoelectric conversion unit to the second semiconductor substrate. A multilayer film including a plurality of insulator layers is provided between the first semiconductor substrate and the second semiconductor substrate. The thickness of the second semiconductor substrate is smaller than 500 micrometers. The thickness of the second semiconductor substrate is greater than the distance from the second semiconductor substrate and a light-receiving surface of the first semiconductor substrate.

Abstract: A light emitting element, a method of manufacturing a light emitting element, and a display device including a light emitting element are provided. A method of manufacturing a light emitting element includes: preparing a lower panel including a substrate and a first sub conductive semiconductor layer on the substrate; forming a first mask layer including at least one mask pattern on at least a part of the lower panel to be spaced apart from each other and an opening region in which the mask patterns are spaced apart from each other; laminating a first conductive semiconductor layer, an active material layer, and a second conductive semiconductor layer on the first mask layer to form an element laminate; etching the element laminate in a vertical direction to form an element rod; and removing the mask pattern to separate the element rod from the lower panel.

Abstract: A semiconductor device may include: an upper conductive plate, a middle conductive plate, and a lower conductive plate that are stacked on each other; a first semiconductor chip located between the upper conductive plate and the middle conductive plate and electrically connected to both the upper conductive plate and the middle conductive plate; and a second semiconductor chip located between the middle conductive plate and the lower conductive plate and electrically connected to both the middle conductive plate and the lower conductive plate, wherein one of an area of the upper conductive plate and an are of the lower conductive plate may be smaller than an area of the middle conductive plate, and another of the area of the upper conductive plate and the area of the lower conductive plate may be larger than the area of the middle conductive plate.

Abstract: The present invention provides a flexible touch display and a display device. The flexible touch display includes a base, a light emitting portion, a first inorganic encapsulation layer, a first insulating layer, multiple first sensing electrodes, and multiple second sensing electrodes. The light emitting portion includes a pixel defining layer and multiple pixels. The first sensing electrodes are arranged spaced apart from each other on the first insulating layer. Each second sensing electrode and each first sensing electrode have a width less than or equal to a width of a bank of the pixel defining layer.

Abstract: A semiconductor device with redistribution layers on partial encapsulation is disclosed and may include providing a carrier with a non-photosensitive protection layer, forming a pattern in the non-photosensitive protection layer, providing a semiconductor die with a contact pad on a first surface, and bonding the semiconductor die to the non-photosensitive protection layer such that the contact pad aligns with the pattern formed in the non-photosensitive protection layer. A second surface opposite to the first surface of the semiconductor die, side surfaces between the first and second surfaces of the semiconductor die, and a portion of a first surface of the non-photosensitive protection layer may be encapsulated with an encapsulant. The carrier may be removed leaving the non-photosensitive protection layer bonded to the semiconductor die. A redistribution layer may be formed on the contact pad and a second surface of the non-photosensitive protection layer opposite to the first surface.

Abstract: A display may have an array of pixels. Each pixel may have a light-emitting diode such as an organic light-emitting diode. The organic light-emitting diodes may each have an anode that is coupled to a thin-film transistor pixel circuit for controlling the anode. Transparent windows may be formed in the display. The windows may be formed by replacing data storage capacitors and other pixel circuit structures in a subset of the pixels with transparent window structures, by selectively removing portions of light-emitting diode anodes, and by shifting anodes. An array of electrical components such as an array of light sensors may be aligned with the transparent windows and may be used to measure light passing through the transparent windows.

Abstract: A light-emitting element in which a first member having a light-emitting diode layer formed therein, and a second member having a drive circuit layer formed therein, are stacked and bonded to each other, wherein the light-emitting diode layer and the drive circuit layer are electrically connected by an electrode; the second member includes a light-shielding portion different from the electrode; the light-shielding portion is disposed so as to cover at least part of a first pixel and a second pixel demarcated by an isolation structure provided in the light-emitting diode layer; and a layer that forms the light-emitting diode layer in the first pixel and a layer that forms the light-emitting diode layer in the second pixel are shared.

Abstract: Present disclosure relates to IC devices with thermal mitigation structures in the form of metal structures provided in a semiconductor material of a substrate on which active electronic devices are integrated (i.e., front-end metal structures). In one aspect, an IC device includes a substrate having a first face and a second face, where at least one active electronic device is integrated at the first face of the substrate. The IC device further includes at least one front-end metal structure that extends from the first face of the substrate into the substrate to a depth that is smaller than a distance between the first face and the second face. Providing front-end metal structures may enable improved cooling options because such structures may be placed in closer vicinity to the active electronic devices, compared to conventional thermal mitigation approaches.

Abstract: Provided is an array substrate and a preparation method thereof and a display device, to improve performance and yield of display products. An embodiment of the present disclosure provides an array substrate, where the array substrate is divided into a display area and a surrounding area arranged outside the display area; the array substrate includes: a substrate, electroluminescent devices and an encapsulation layer disposed on the substrate in the display area, the encapsulation layer configured to encapsulate the electroluminescent device, and a touch function layer disposed on the encapsulation layer; the touch function layer includes a touch lead extending from the display area to the surrounding area; and the array substrate further includes: a thickness compensation layer located in the surrounding area and disposed between the substrate and the touch lead layer.

Abstract: Provided is an electro-optical device including a plurality of pixel electrodes arranged in a display region, a first transistor that captures a pulse supplied to a source node by using a clock signal supplied to a gate node and outputs the pulse from the drain node, a second transistor to which the pulse output from the drain node is input, and a capacitance element having one end coupled to the drain node and another end held at a predetermined potential. In the capacitance element, an interlayer insulating film is sandwiched between a first peripheral electrode formed of a same layer as the plurality of pixel electrodes and a wiring formed of a predetermined electrode layer, and the wiring includes a portion overlapping the second transistor in plan view.

Abstract: A display panel, a fabrication method thereof, and a display device are disclosed. The display panel includes: a substrate; a pixel defining layer located on the substrate, the pixel defining layer including: a plurality of openings and a bank enclosing each opening, the bank including a notch; and a first electrode, located at a bottom of each opening and extending into the notch, wherein with respect to a plane where the substrate is located, a height of the first electrode is less than or equal to a maximum height of the notch.

Abstract: A method of patterning quantum dots, a device using same, and a system thereof are provided. By providing a base between a plurality of upper electrodes and a plurality of lower electrodes, coating a quantum dot solution on an upper surface of the base, and powering the upper electrodes and the lower electrodes to form an electric field between the upper electrodes and the lower electrodes, the quantum dot solution is gathered between the upper electrodes and the lower electrodes according to an electric field distribution. Subsequently, the quantum dot solution can be deposited into a film by evaporation of a solvent, thereby obtaining a patterned quantum dot thin film on the base.

Abstract: An array substrate, a manufacturing method thereof, a display panel and a display device are disclosed. The array substrate includes a base substrate, a light shielding layer, an active layer of a thin film transistor, and an insulating layer. The light shielding layer includes light transmission holes on the base substrate. The active layer of the thin film transistor is located on the side of the light shielding layer away from the base substrate. An insulating layer is located on the base substrate. The insulating layer includes a first through hole in communication with the light transmission hole.

Abstract: A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die.

Abstract: A high-voltage semiconductor device includes a substrate, a body region, a well region, a bulk region, a source, a drain, an isolation region, a gate structure, and a resistor. The body region and the well region are disposed in the substrate. The bulk region and the source are disposed in the body region. The drain is disposed in the well region. The isolation region is disposed on the well region. The isolation region is disposed between the drain and the source. The gate structure is disposed on the substrate. The gate structure extends onto a portion of the isolation region. The resistor is disposed on the isolation region. The resistor is electrically connected to the bulk region and the drain, or the resistor is electrically connected to the drain and/or the source.

Abstract: A structure includes: a ? silicon nitride crystal phase; and a Y2MgSi2O5N crystal phase. The structure gives a X-ray diffraction pattern by a ?-2? method, the pattern having a ratio of a peak intensity of a (22-1) plane of the Y2MgSi2O5N crystal phase to a peak intensity of a (200) plane of the ? silicon nitride crystal phase, the peak intensity of the (200) plane being determined at a position of 2?=27.0±1°, the peak intensity of the (22-1) plane being determined at a position of 2?=30.3±1°, and the ratio being 0.001 or more and 0.01 or less.

Abstract: What is provided is a method of manufacturing an insulating circuit board with a heatsink including an insulating circuit board and a heatsink, the heatsink being bonded to the metal layer side of the insulating circuit board, the metal layer being formed of aluminum, and a bonding surface of the heatsink with the insulating circuit board being formed of an aluminum alloy having a solidus temperature of 650° C. or lower. This method includes a high alloy element concentration portion forming step (S02) of forming a high alloy element concentration portion and a heatsink bonding step (S03) of bonding the heatsink, in which a ratio tb/ta of a thickness tb of the brazing material layer to a thickness to of the core material in the clad material is in a range of 0.1 to 0.3.