Patents Examined by Allen L Parker
  • Patent number: 11387212
    Abstract: The present application discloses a method for transferring a plurality of micro light emitting diodes (micro LEDs) to a target substrate. The method includes providing a first substrate having an array of the plurality of micro LEDs; providing a target substrate having a bonding layer having a plurality of bonding contacts; applying the plurality of bonding contacts with an electrical potential; aligning the plurality of micro LEDs with the plurality of bonding contacts having the electrical potential; and transferring the plurality of micro LEDs in the first substrate onto the target substrate.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: July 12, 2022
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Guan Huang, Yijie Huo, Fang Liu
  • Patent number: 11380581
    Abstract: A method of fabricating an interconnect structure of a semiconductor device is provided having a first conductive line and forming a second conductive line over the first conductive line. A via opening is formed in the second conductive line, and the via opening is aligned over the first conductive line. The via opening is filled with a conductive material to form an interconnect via and an upper portion of the interconnect via forms a portion of the second conductive line.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: July 5, 2022
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Andre P. Labonte, Catherine B Labelle, Chanro Park
  • Patent number: 11374043
    Abstract: A photodetecting device includes a semiconductor substrate, a plurality of avalanche photodiodes each having a light receiving region, the avalanche photodiodes being arranged in a matrix at the semiconductor substrate, and a plurality of through-electrodes electrically connected to corresponding light receiving regions. The plurality of through-electrodes are arranged for each area surrounded by four mutually adjacent avalanche photodiodes of the plurality of avalanche photodiodes. Each of the light receiving regions has, when viewed from a direction perpendicular to a first principal surface of the semiconductor substrate, a polygonal shape including a pair of first sides opposing each other in a row direction and extending in a column direction and four second side opposing four through-electrodes surrounding the light receiving region and extending in directions intersecting with the row direction and the column direction. The length of the first side is shorter than the length of the second side.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: June 28, 2022
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Atsushi Ishida, Terumasa Nagano, Takashi Baba
  • Patent number: 11374207
    Abstract: An optoelectronic assembly comprising an optoelectronic component, which comprises a specularly reflective surface and comprising a radiation cooler in direct physical contact with the optoelectronic component. The radiation cooler is arranged above the specularly reflective surface.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: June 28, 2022
    Assignee: Pictiva Displays International Limited
    Inventors: Dominik Pentlehner, Richard Baisl
  • Patent number: 11373979
    Abstract: Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: June 28, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Mung Suan Heng, Kok Chua Tan, Vince Chan Seng Leong, Mark S. Johnson
  • Patent number: 11363715
    Abstract: A lighting device including a light-emitter including light emitting elements, and a support having a first surface that carries a wiring line electrically connecting element electrodes of the light emitting elements and a light emitting surface, and a substrate including a base substrate, a conductor formed on a first surface of the base substrate, an adhesive member formed on a second surface of the base substrate, and a through-hole penetrating the substrate. A space is formed between the substrate and the light-emitter to communicate with a bottomed hole formed in a location of the through-hole as a result of adhering an adhesive surface of the adhesive member to a surface of the light-emitter having the wiring line formed thereon. The wiring line is connected to the conductor via a filler filling the bottomed hole, and the space is located outside an opening of the bottomed hole.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: June 14, 2022
    Assignee: NICHIA CORPORATION
    Inventors: Eiko Minato, Yumiko Kameshima, Koji Taguchi, Masaaki Katsumata
  • Patent number: 11362208
    Abstract: A semiconductor device includes a semiconductor substrate having a source region and a drain region, a first insulator between the source region and the drain region, a gate electrode having a first end on a side thereof closer to the source region than the drain region on a portion of the semiconductor substrate that is not covered with the first insulator, and having a second end on the first insulator closer to the drain region than the source region, and a second insulator that is continuous with the second end of the gate electrode and having a portion which is on the first insulator where the first insulator is not covered with the gate electrode, is on an end of the drain region, and is in contact with the gate electrode, the first insulator, and the drain region.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: June 14, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Hirofumi Kawai
  • Patent number: 11348927
    Abstract: The present disclosure provides example embodiments relating to conductive features, and methods of forming the conductive features, that have differing dimensions. In an embodiment, a structure includes a substrate, a dielectric layer over the substrate, and first and second conductive features through the dielectric layer to first and second source/drain regions, respectively, on the substrate. The first conductive feature has a first length along a longitudinal axis of the first conductive feature and a first width perpendicular to the first length. The second conductive feature has a second length along a longitudinal axis of the second conductive feature and a second width perpendicular to the second length. The longitudinal axis of the first conductive feature is aligned with the longitudinal axis of the second conductive feature. The first width is greater than the second width, and the first length is less than the second length.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: May 31, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yu-Lien Huang
  • Patent number: 11342444
    Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Gang Chen, Tai-Chun Huang, Ming-Chang Wen, Shu-Yuan Ku, Fu-Kai Yang, Tze-Liang Lee, Yung-Cheng Lu, Yi-Ting Fu
  • Patent number: 11324117
    Abstract: A lighting device including a light-emitter including light emitting elements, and a support having a first surface that carries a wiring line electrically connecting element electrodes of the light emitting elements and a light emitting surface, and a substrate including a base substrate, a conductor formed on a first surface of the base substrate, an adhesive member formed on a second surface of the base substrate, and a through-hole penetrating the substrate. A space is formed between the substrate and the light-emitter to communicate with a bottomed hole formed in a location of the through-hole as a result of adhering an adhesive surface of the adhesive member to a surface of the light-emitter having the wiring line formed thereon. The wiring line is connected to the conductor via a filler filling the bottomed hole, and the space is located outside an opening of the bottomed hole.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: May 3, 2022
    Assignee: NICHIA CORPORATION
    Inventors: Eiko Minato, Yumiko Kameshima, Koji Taguchi, Masaaki Katsumata
  • Patent number: 11315901
    Abstract: A method for bonding a first substrate to a second substrate on mutually facing contact surfaces of the substrates, wherein the first substrate is mounted on a first chuck and the second substrate is mounted on a second chuck, and wherein a plate is arranged between the second substrate and the second chuck, wherein the second substrate with the plate is deformed with respect to the second chuck before and/or during the bonding. Furthermore, the present invention relates to a corresponding device and a corresponding plate.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: April 26, 2022
    Assignee: EV Group E. Thallner GmbH
    Inventors: Dominik Zinner, Thomas Wagenleitner, Jurgen Markus Suss, Thomas Plach, Jurgen Mallinger
  • Patent number: 11309300
    Abstract: A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: April 19, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kil-soo Kim
  • Patent number: 11302534
    Abstract: A semiconductor structure and a fabrication method are provided. The fabrication method includes forming a first dielectric layer on a base substrate, the first dielectric layer containing an opening exposing a surface portion of the base substrate; forming an initial gate dielectric layer on the surface portion of the base substrate and on a sidewall surface of the opening in the first dielectric layer; forming a gate dielectric layer by removing a portion of the initial gate dielectric layer from the sidewall surface of the opening, such that a top surface of the gate dielectric layer on the sidewall surface is lower than a top surface of the first dielectric layer; forming a gate electrode on the gate dielectric layer to fill the opening, a portion of the gate electrode being formed on a portion of the sidewall surface of the first dielectric layer; and forming a second dielectric layer on the gate electrode and on the first dielectric layer.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: April 12, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 11289651
    Abstract: A memory cell with a hard mask and a sidewall spacer of different material is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A hard mask disposed over the top electrode. A sidewall spacer extends upwardly along sidewalls of the switching dielectric, the top electrode, and the hard mask. The hard mask and the sidewall spacer have different etch selectivity. A method for manufacturing the memory cell is also provided.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Hsueh Yang, Shih-Chang Liu, Yuan-Tai Tseng
  • Patent number: 11282850
    Abstract: A semiconductor memory device includes: a first and a second electrodes aligned in a first direction; a first semiconductor layer provided between the first and the second electrodes; a second semiconductor layer provided between the first semiconductor layer and the second electrode; a first charge accumulating layer provided between the first electrode and the first semiconductor layer; and a second charge accumulating layer provided between the second electrode and the second semiconductor layer. At least one of the first and the second charge accumulating layers include: a first and a second regions including nitrogen, aluminum, and oxygen and having different positions in a second direction; and a third region provided between the first and the second regions in the second direction. Oxygen is not included in the third region or a concentration of oxygen in the third region is lower than that in the first and the second regions.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: March 22, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Akira Takashima, Tsunehiro Ino, Ayaka Suko
  • Patent number: 11282801
    Abstract: A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: March 22, 2022
    Assignee: EV GROUP E. THALLNER GMBH
    Inventors: Viorel Dragoi, Markus Wimplinger
  • Patent number: 11271021
    Abstract: An array substrate, a fabrication method thereof, and a display device are provided. The fabrication method includes forming a first conductive layer and a second conductive layer on both of a first area and a second area of a substrate; forming a bonding pin in the first area to electrically connect with a driving chip, wherein the second conductive layer is located at a side of the first conductive layer away from the substrate; and removing the second conductive layer in the second area, forming a conductive electrode in the second area to electrically connect with a light-emitting element by a connection member.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: March 8, 2022
    Assignee: TCL China Star Optoelectronics Technology Co., Ltd.
    Inventors: Xin Zhang, Xiaobo Hu
  • Patent number: 11270955
    Abstract: A multi-layer package substrate includes a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer. The second build-up layer includes a top metal layer with a surface configured for attaching at least one integrated circuit (IC) die. The first build-up layer includes a bottom metal layer and a first microvia extending through the first dielectric layer, and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia. A barrier ring that has a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second microvia positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: March 8, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jaimal Mallory Williamson, Guangxu Li
  • Patent number: 11264540
    Abstract: A light emitting diode includes a light emitting structure including first and second conductive type semiconductor layers and an active layer disposed therebetween, a second hole formed through the active layer and the second conductive type semiconductor layer, and exposing the first conductive type semiconductor layer, a reflective metal layer contacting a portion of the light emitting structure, a cover metal layer contacting at least a portion of the reflective metal layer, a first insulation layer covering the reflective metal layer and the cover metal layer, an electrode layer disposed on the first insulation layer, the electrode layer covering the first insulation layer and filling the second hole, an electrode pad disposed on the light emitting structure, and a first hole formed through the first conductive type semiconductor layer and corresponding to the cover metal layer, in which the electrode pad overlaps the cover metal layer.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: March 1, 2022
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Joon Hee Lee, Mi Hee Lee
  • Patent number: 11257955
    Abstract: The disclosure provides a thin film transistor, an array substrate, and a method for fabricating the same. An embodiment of the disclosure provides a method for fabricating a thin film transistor, the method including: forming a gate, a gate insulation layer, and an active layer above an underlying substrate successively; forming a patterned hydrophobic layer above the active layer, wherein the hydrophobic layer includes first pattern components, and orthographic projections of the first pattern components onto the underlying substrate overlap with a orthographic projection of a channel area at the active layer onto the underlying substrate; and forming a source and a drain above the hydrophobic layer, wherein the source and the drain are located respectively on two sides of a channel area, and in contact with the active layer.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: February 22, 2022
    Assignees: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventors: Qinghe Wang, Luke Ding, Leilei Cheng, Jun Bao, Tongshang Su, Dongfang Wang, Guangcai Yuan