Abstract: A vertical memory device includes a channel extending vertically on a substrate. A charge storage structure is disposed on a sidewall of the channel. Gate electrodes are spaced apart from each other vertically and surround the charge storage structure. A first insulation pattern includes an air gap between the gate electrodes. The charge storage structure includes a tunnel insulation layer, a charge trapping pattern, and a first blocking pattern sequentially stacked horizontally. The charge storage structure includes charge trapping patterns spaced apart from each other vertically. Each of the charge trapping patterns faces one of the gate electrodes horizontally. A length in the first direction of an outer sidewall of each of the charge trapping patterns facing the first blocking pattern is less than that of an inner sidewall thereof facing the tunnel insulation layer.

Abstract: A vacuumizing device includes a vacuum chamber, a bonding fixture and a vacuumizing system. The bonding fixture is disposed in the vacuum chamber and includes a substrate table provided with a plurality of grooves for retention of the substrate by suction. The vacuumizing system is disposed in communication with both the vacuum chamber and grooves. During vacuumizing by the vacuumizing system, a vacuum value in the grooves is smaller than or equal to a vacuum value in the vacuum chamber. In the vacuumizing device and methods, the vacuumizing system is used to vacuumize the grooves in the substrate table and the vacuum chamber so that the vacuum value in the grooves is always smaller than or equal to that in the vacuum chamber. As a result, the substrates are firmly retained on the substrate table without warping, thereby improving the quality of substrate bonding.

Abstract: Embodiments of structure and methods for forming a memory device are provided. In an example, a memory device includes a substrate, a stack above the substrate, a channel structure, and a source contact structure each extending vertically through the memory stack. The source contact structure includes (i) a plurality of first source contact portions each extending vertically and laterally separated from one another and (ii) a second source contact portion extending vertically over and in contact with the plurality of first source contact portions, the second source contact portion being laterally continuous.

Abstract: A semiconductor memory device includes a substrate, a first conductor layer, and a first insulator layer. The substrate includes a first region on which memory cells are provided, a second region on which a control circuit of the memory cells is provided, and a third region separating the first region and the second region. The first conductor layer is above the second region of the substrate. The first insulator layer is above the second and third regions of the substrate. The first insulator layer includes a first portion that is above the first conductor layer and extends along a surface direction of the substrate, and a second portion that is continuous with the first portion and extends along a thickness direction of the substrate from the first portion toward a surface of the substrate in the third region.

Abstract: A light emitting device includes: a plurality of element structural bodies, each including: a substrate, a light emitting element mounted on or above the substrate, and a light-transmissive member disposed on or above the light emitting element, wherein at least three of the plurality of element structural bodies are disposed along a first direction; a first covering member that covers lateral surfaces of the substrate, the light emitting element, and the light-transmissive member of each of the plurality of element structural bodies; and a support member that covers a lateral surface of the first covering member, wherein at least a portion of the support member is disposed lateral to the plurality of element structural bodies and extends along the first direction. A rigidity of the support member is greater than a rigidity of the first covering member.

Abstract: In a method of forming patterns, first and second upper reverse patterns are formed on a lower reverse layer. A buffer layer is formed to fill first opening portions provided by the first upper reverse pattern. A shield pattern is formed to cover a second region of the buffer layer. An etching process is performed using the shield pattern and the first upper reverse pattern as an etching mask to form first lower reverse patterns providing second openings overlapping first openings, a buffer layer pattern and a second lower reverse pattern overlapping the shield pattern. A hard mask layer is formed and etched to separate hard mask layer first patterns filling the first and second openings. An etching process is performed using the hard mask layer first patterns and the second upper reverse patterns as etching masks to form third lower reverse patterns overlapping the second upper reverse pattern.

Abstract: A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises a cavity therein that comprises a stair-step structure. Sidewalls of the cavity and steps of the stair-step structure are lined with an insulator material. Insulative material is formed in the cavity radially inward of the insulator material. An upper portion of the insulative material is removed from the cavity to leave the insulative material in a bottom of the cavity over the stair-step structure. After the removing, insulating material is formed in the cavity above the insulative material. Other embodiments, including structure independent of method, are disclosed.

Abstract: The invention provides an image sensor, the image sensor includes a substrate, a first circuit layer located on the substrate, and at least one nanowire photodiode located on the first circuit layer and electrically connected to the first circuit layer, the nanowire photodiode comprises a lower material layer and an upper material layer with a P-N junction between the lower material layer and the upper material layer, the lower material layer includes perovskite material.

Abstract: A structure includes a semiconductor substrate, and a polycrystalline resistor region over the semiconductor substrate. The polycrystalline resistor region includes a semiconductor material in a polycrystalline morphology. A dopant-including polycrystalline region is between the polycrystalline resistor region and the semiconductor substrate.

Abstract: An electronic device can include a housing that includes an optically transparent component. First and second light emitters can be positioned in the internal volume defined by the housing. A light detector can be positioned in the internal volume and can be optically isolated from the first and second light emitters within the internal volume. An opaque material can be disposed on the optically transparent component and can be positioned to inhibit light emitted from the second light emitter from reaching the light detector and to allow light emitted from the first light emitter to reach the light detector.

Abstract: A method for producing a transistor includes producing on a substrate provided with a semiconductor surface layer in which an active area can be formed, a gate block arranged on the active area. Lateral protection areas are formed against lateral faces of the gate block. Source and drain regions based on a metal material-semiconductor material compound are formed on either side of the gate and in the continuation of a portion located facing the gate block. Insulating spacers are formed on either side of the gate resting on the regions based on a metal material-semiconductor material compound.

Abstract: The present disclosure is generally directed to semiconductor structures and methods that improve breakdown characteristics in finFET device designs, while retaining cost effectiveness for integration into the process flow. The semiconductor structure includes an extended lightly-doped-drain (LDD) region formed on a source/drain structure. The extended LDD regions provide extra separation between source and drain regions, which in turn provides for an increased source to drain resistance. The increased source to drain resistance improves the breakdown voltage of the semiconductor device, and significantly reduces its susceptibility to latch-up. The source to drain resistance may be tuned by adjusting the length of epi block regions, and may also be tuned by selecting desired doping profiles for the LDD and source/drain regions. The length of epi block regions may also be adjusted to maintain high uniformity of epitaxial growth in the S/D regions.

Abstract: Methods of selectively depositing films on substrates are described. A passivation film is deposited on a metal surface before deposition of a dielectric material. Also described is exposing a substrate surface comprising a metal surface and a dielectric surface to a docking precursor to form a passivation film.

Abstract: According to one embodiment, an optical sensor device includes an insulating substrate, a first conductive layer and an optical sensor element disposed between the insulating substrate and the first conductive layer. The optical sensor element is electrically connected to the first conductive layer and covered by the first conductive layer. The optical sensor element includes a first semiconductor layer formed of an oxide semiconductor and controls an amount of charge flowing to the first conductive layer according to an amount of incident light to the first semiconductor layer.

Abstract: A semiconductor package including a semiconductor chip, an interposer on the semiconductor chip, and a molding layer covering at least a portion of the semiconductor chip and at least a portion of the interposer may be provided. The interposer includes a interposer substrate and a heat dissipation pattern penetrating the interposer substrate and electrically insulated from the semiconductor chip. The heat dissipation pattern includes a through electrode disposed in the interposer substrate and an upper pad disposed on an upper surface of the interposer substrate and connected to the through electrode. The molding layer covers at least a portion of a sidewall of the upper pad and the upper surface of the interposer substrate. At least a portion of an upper surface of the upper pad is not covered by the molding layer.

Abstract: A semiconductor module includes a semiconductor device, and a cooling device. The semiconductor device includes a semiconductor chip and a circuit board for mounting the chip. The cooling device includes a top plate mounted in the semiconductor device and having a side wall connected thereto, a bottom plate connected to the side wall, and a refrigerant circulating portion, defined by the top plate, the side wall, and the bottom plate and has a substantially rectangular shape with a cross section parallel to a main surface of the top plate having long and short sides. The circuit board is a substantially rectangular laminated circuit board including an insulating plate having an upper surface with a circuit layer and a lower surface with a metal layer. In a plan view, at least one corner of the metal layer at least partially overlaps with the slope portion of the side wall.

Abstract: A method for forming a semiconductor device is provided. The method includes the following steps: providing a semiconductor substrate; forming a pad layer on the semiconductor substrate; forming a first passivation layer on the pad layer; forming a second passivation layer on the first passivation layer, wherein the second passivation layer comprises polycrystalline silicon; forming an oxide layer on the second passivation layer; forming a nitride layer on the oxide layer; removing a portion of the oxide layer and a portion of the nitride layer to expose a portion of the second passivation layer; removing the portion of the second passivation layer that has been exposed to expose a portion of the first passivation layer; and removing the portion of the first passivation layer that has been exposed to expose a portion of the pad layer.

Abstract: A semiconductor device includes a channel structure arranged on a substrate and extending in a first direction perpendicular to a top surface of the substrate, the channel structure including a channel layer and a gate insulating layer; a plurality of insulating layers arranged on the substrate and surrounding the channel structure, the plurality of insulating layers spaced apart from each other in the first direction; a plurality of first gate electrodes surrounding the channel structure; and a plurality of second gate electrodes surrounding the channel structure. Between adjacent insulating layers from among the plurality of insulating layers are arranged a first gate electrode from among the plurality of first gate electrodes spaced apart along the first direction from a second gate electrode from among the plurality of second gate electrodes.

Abstract: A semiconductor device includes a lower structure; a stack structure including gate layers and interlayer insulating layers and having an opening; a vertical structure in the opening; a contact structure on the vertical structure; and a conductive line on the contact structure. The vertical structure includes an insulating core region, a channel semiconductor layer covering side and lower surfaces of the insulating core region, data storage patterns between the channel semiconductor layer and the gate layers and spaced apart from each other, a first dielectric layer, and a second dielectric layer. At least a portion of the first dielectric layer is between the data storage patterns and the gate layers, at least a portion of the second dielectric layer is between the data storage patterns and the channel semiconductor layer, and the insulating core region includes first convex portions having increased widths in regions facing the gate layers.

Abstract: An electronic component mounting package includes: an insulating base body including a principal face and a recess which opens in the principal face; and a metallic pattern including a plurality of metallic layers lying across a side face of the recess and the principal face. The metallic pattern includes, as an inner layer, at least one metallic layer selected from a tungsten layer, a nickel layer, and a gold layer, and an aluminum layer as an outermost layer. The metallic pattern includes an exposed portion corresponding to a part of the metallic layer constituting the inner layer which part is exposed at the principal face.