Patents Examined by Allen L Parker
  • Patent number: 11018311
    Abstract: An electronic device includes a first electrode and a second electrode facing each other, an emission layer comprising a plurality of quantum dots, wherein the emission layer is disposed between the first electrode and the second electrode; a first charge auxiliary layer disposed between the first electrode and the emission layer; and an optical functional layer disposed on the second electrode on a side opposite the emission layer, wherein the first electrode includes a reflecting electrode, wherein the second electrode is a light-transmitting electrode, wherein a region between the optical functional layer and the first electrode comprises a microcavity structure, and a refractive index of the optical functional layer is greater than or equal to a refractive index of the second electrode.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: May 25, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae Young Chung, Eun Joo Jang, Oul Cho, Hyun A Kang, Tae Hyung Kim, Yun Sung Woo, Jeong Hee Lee
  • Patent number: 11018150
    Abstract: A semiconductor memory device includes a first electrode film, a second electrode film separated from the first electrode film in a first direction, a third electrode film separated from the second electrode film in the first direction, a fourth electrode film separated from the third electrode film in the first direction, and a first and a second semiconductor members extending in the first direction. The second electrode film includes a first conductive portion, an insulating portion, and a second conductive portion arranged along a second direction. The first semiconductor member pierces the first, third and fourth electrode films and the insulating portion of the second electrode film. The second semiconductor member pierces the first, third and fourth electrode films, and the first conductive portion or the second conductive portion of the second electrode film.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: May 25, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kotaro Fujii, Yasuhiro Uchiyama, Masaru Kito
  • Patent number: 11011480
    Abstract: Provided is a semiconductor device capable of improving relative accuracy of semiconductor elements and a yield of a semiconductor integrated circuit device. The semiconductor device includes a flat region formed on a surface of a semiconductor substrate, and having an outer peripheral shape formed by regional sides and regional chamfer portions; an outer peripheral region surrounding the flat region, and having a uniform height different from a height of the flat region; a plurality of semiconductor elements having similar shapes or the same shape, and formed on the flat region; and a wiring metal connecting the plurality of semiconductor elements via contact holes formed in a second insulating film on the semiconductor elements.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: May 18, 2021
    Assignee: ABLIC INC.
    Inventor: Hiroaki Takasu
  • Patent number: 11011455
    Abstract: A method for providing an electronic package structure includes providing a substrate having a die pad having a die pad top surface and an opposing die pad bottom surface, leads laterally spaced apart from the die pad, and a substrate encapsulant interposed between the die pad and the leads and includes a substrate top surface and an opposing substrate bottom surface. The substrate encapsulant is provided such that the die pad and the leads protrude outward from the substrate bottom surface. The method includes providing an electronic device having opposing major surfaces and a pair of opposing outer edges. The method includes connecting the electronic device to the substrate such that one major surface of the electronic device is spaced apart from the die pad top surface and upper surfaces of the leads, and the outer edges overlap an opposing pair of the leads.
    Type: Grant
    Filed: February 10, 2018
    Date of Patent: May 18, 2021
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Tae Kyung Hwang, Eun Sook Sohn, Won Joon Kang, Gi Jeong Kim
  • Patent number: 11011529
    Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells, with the memory cells individually comprising a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. A capacitor of the memory cell comprises first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. A horizontal longitudinally-elongated sense line is in individual of the memory-cell tiers. Individual of the second source/drain regions of individual of the transistors that are in the same memory-cell tier are electrically coupled to the horizontal longitudinally-elongated sense line in that individual tier of memory cells.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 11004760
    Abstract: A chip structure is provided. The chip structure includes: a first lower chip structure; and an upper chip structure on the first lower chip structure and having a pixel array region. The first lower chip structure includes: a first lower semiconductor substrate having a first side and a second side opposing each other; a first portion on the first side of the first lower semiconductor substrate; and a second portion on the second side of the first lower semiconductor substrate, the first portion of the first lower chip structure includes a gate wiring, the second portion of the first lower chip structure includes a second side wiring and a heating element, and the heating element is on the same plane as that of the second side wiring and has a length greater than that of the second side wiring.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: May 11, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo Hyun Park, Jae Choon Kim
  • Patent number: 10998226
    Abstract: A method of forming an interconnection structure includes following steps. A dielectric structure is deposited over a non-insulator structure. The dielectric structure is etched to form a via opening. A mask layer is formed over the dielectric structure. The mask layer is patterned. An anti-adhesion layer is deposited on a sidewall of the via opening after patterning the mask layer. The dielectric structure is etched to form a trench opening, wherein the patterned mask layer is used as an etch mask during forming the trench opening. A conductive structure is formed in the via opening and the trench opening.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10991854
    Abstract: A light-emitting element includes a semiconductor light-emitting stack including a first semiconductor layer, a second semiconductor layer formed on the first semiconductor layer, and an active layer formed therebetween; a first conductive layer disposed on the second semiconductor layer and electrically connecting the second semiconductor layer; a second conductive layer disposed on the second semiconductor layer and electrically connecting the first semiconductor layer; and a cushion part disposed on and directly contacts the first conductive layer, wherein in a top view, the cushion part is surrounded by and electrically isolated from the second conductive layer.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: April 27, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Tsung-Hsun Chiang, Chien-Chih Liao, Wen-Hung Chuang, Min-Yen Tsai, Bo-Jiun Hu
  • Patent number: 10991853
    Abstract: A carrier for an optoelectronic component includes a main body, wherein the main body includes a first electrically conductive heating layer arrangement, a first solder layer for soldering an optoelectronic component to the main body is arranged on a first side of the main body, the first electrically conductive heating layer arrangement is electrically insulated from the first solder layer and thermally connected to the first solder layer, and the first heating layer arrangement has an exposed portion on which molten solder of the first solder layer can flow to reduce an electrical resistance of the first heating layer arrangement.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: April 27, 2021
    Assignee: OSRAM OLED GmbH
    Inventors: Christoph Walter, Roland Enzmann, Markus Horn, Jan Seidenfaden
  • Patent number: 10991660
    Abstract: A semiconductor wafer is singulated to form a plurality of semiconductor packages. The semiconductor wafer has a semiconductor substrate, a metal layer, an adhesive layer, a rigid supporting layer, a passivation layer and a plurality of contact pads. A semiconductor package has a semiconductor substrate, a metal layer, an adhesive layer, a rigid supporting layer, a passivation layer and a plurality of contact pads. A thickness of the rigid supporting layer is larger than a thickness of the semiconductor substrate. A thickness of the metal layer is thinner than the thickness of the semiconductor substrate. An entirety of the rigid supporting layer may be made of a single crystal silicon material or a poly-crystal silicon material. The single crystal silicon material or the poly-crystal silicon material may be fabricated from a reclaimed silicon wafer. An advantage of using a reclaimed silicon wafer is for a cost reduction.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: April 27, 2021
    Assignee: ALPHA ANC OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Long-Ching Wang, Zhen Du, Bo Chen, Jun Lu, Yueh-Se Ho
  • Patent number: 10985055
    Abstract: An interconnection structure includes a non-insulator structure, a liner layer, a dielectric structure, a conductive structure and an anti-adhesion layer. The liner layer is present on the non-insulator structure and has an opening therein. The dielectric structure is present on the liner layer. The dielectric structure includes a via opening therein. The via opening has a sidewall. The conductive structure is present in the via opening of the dielectric structure and electrically connected to the non-insulator structure through the opening of the liner layer. The anti-adhesion layer is present between the sidewall of the via opening of the dielectric structure and the conductive structure.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: April 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10978660
    Abstract: An electronic device includes a first electrode and a second electrode facing each other, an emission layer comprising a plurality of quantum dots, wherein the emission layer is disposed between the first electrode and the second electrode; a first charge auxiliary layer disposed between the first electrode and the emission layer; and an optical functional layer disposed on the second electrode on a side opposite the emission layer, wherein the first electrode includes a reflecting electrode, wherein the second electrode is a light-transmitting electrode, wherein a region between the optical functional layer and the first electrode comprises a microcavity structure, and a refractive index of the optical functional layer is greater than or equal to a refractive index of the second electrode.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: April 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae Young Chung, Eun Joo Jang, Oul Cho, Hyun A Kang, Tae Hyung Kim, Yun Sung Woo, Jeong Hee Lee
  • Patent number: 10971588
    Abstract: A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact layer and a separation layer. The fin structure protrudes from an isolation insulating layer disposed over a substrate and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact layer is disposed on the first source/drain region. The separation layer is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact layer are in contact with a same face of the separation layer.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jyun Huang, Tung-Heng Hsieh, Bao-Ru Young
  • Patent number: 10964661
    Abstract: The present invention comprises: a spool (10); a clamper (22); a torch electrode (31); a high-voltage power source circuit (30); a non-bonding detection circuit (40); a first changeover switch (50) switching a connection between the spool (10) and the high-voltage power source circuit (30) or the non-bonding detection circuit (40); and a relay (53) turning on/off a connection between the clamper (22) and a spool side of the first changeover switch (50), and comprises a control part (60) that sets the first changeover switch (50) to the high-voltage power source circuit side and turns off the relay (53) to generate electric discharge, and that sets the first changeover switch (50) to the non-bonding detection circuit side and turns on the relay (53) to perform non-bonding detection. Due to this configuration, electric corrosion of a wire clamper can be suppressed and non-bonding detection can be carried out with a simple configuration.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: March 30, 2021
    Assignee: SHINKAWA LTD.
    Inventors: Junichi Abe, Hisashi Ueda, Yutaka Kondo
  • Patent number: 10964815
    Abstract: A semiconductor device includes a substrate, a gate disposed over the substrate, a source/drain disposed in the substrate at two sides of the gate, and an insulating layer disposed over sidewalls of the gate and at least a portion of a surface of the source/drain. In some embodiments, the insulating layer includes a first side facing the gate or the source, and includes a second side opposite to the first side. The insulating layer includes dopants, and a concentration of the dopants is reduced from the second side to the first side of the insulating layer.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hong-Nien Lin, Ming-Heng Tsai, Yong-Yan Lu, Chun-Sheng Liang, Jeng-Ya Yeh
  • Patent number: 10950733
    Abstract: Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: March 16, 2021
    Assignee: Google LLC
    Inventors: Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros, Han Wui Then, Gilbert Dewey, Marko Radosavljevic, Benjamin Chu-Kung, Niloy Mukherjee
  • Patent number: 10950612
    Abstract: A semiconductor memory device has a plurality of gates vertically stacked on a top surface of a substrate, a vertical channel filling a vertical hole that extends vertically through the plurality of gates, and a memory layer in the vertical hole and surrounding the vertical channel. The vertical channel includes a bracket-shaped lower portion filling part of a recess in the top of the substrate and an upper portion extending vertically along the vertical hole and connected to the lower channel. At least one end of an interface between the lower and upper portions of the vertical channel is disposed at a level not than that of the top surface of the substrate.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: March 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sunggil Kim, Sangsoo Lee, Seulye Kim, Hongsuk Kim, Jintae Noh, Ji-Hoon Choi, Jaeyoung Ahn, Sanghoon Lee
  • Patent number: 10950724
    Abstract: A semiconductor device includes a substrate with an upper surface and a lower surface, and first to third active patterns extending from the upper surface of the substrate. The first to third active patterns are arranged adjacent to each other in a first direction. The second active pattern is disposed between the first and third active patterns. The semiconductor device also includes a first gate electrode surrounding side surfaces of the first and second active patterns, and a second gate electrode surrounding side surfaces of the third active pattern. Each of the first to third active patterns includes a first impurity region, a channel region, and a second impurity region.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: March 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yeoncheol Heo, Sharma Deepak, Kwanyoung Chun
  • Patent number: 10943822
    Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Liang Chung, Che-Hao Tu, Kei-Wei Chen, Chih-Wen Liu, You-Shiang Lin, Yi-Ching Liang
  • Patent number: 10937817
    Abstract: An array substrate is provided. The array substrate includes a capacitor, which includes a plurality of metal electrodes arranged opposite to each other. The plurality of metal electrodes are spaced apart from each other in a horizontal direction parallel to a plane in which the array substrate is located, and an orthogonal projection of each of at least two of the plurality of metal electrodes of the capacitor on the plane in which the array substrate is located includes a curved portion.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 2, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Baoxia Zhang, Cuili Gai, Ling Wang