Abstract: A semiconductor memory structure includes a semiconductor layer, a conductive layer disposed over the semiconductor layer, a gate penetrating through the conductive layer and the semiconductor layer, and an interposing layer disposed between the gate and the conductive layer and between the gate and the semiconductor layer, wherein a pair of channel regions is formed in the semiconductor layer at two sides of the gate.

Abstract: A semiconductor device includes: a stack structure including a cell region and a contact region; a channel structure penetrating the cell region of the stack structure; trenches penetrating the contact region of the stack structure to different depths; and a stop structure penetrating the contact region of the stack structure, the stop structure being located between the trenches.

Abstract: A 3D semiconductor device including: a first level including a first single crystal layer, the first level including a plurality of first transistors and at least one first metal layer, where the at least one first metal layer overlays the first single crystal layer, and where the at least one first metal layer includes interconnects between the first transistors forming first control circuits; a second metal layer overlaying the at least one first metal layer; a second level overlaying the second metal layer, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors, where the second level includes a plurality of first memory cells, the first memory cells each including at least one of the second transistors, where the third level includes second memory cells, the second memory cells each including third transistors.

Abstract: A semiconductor device includes a stacked structure including conductive layers and gaps respectively interposed between the conductive layers, a channel layer passing through the stacked structure, a ferroelectric layer surrounding a sidewall of the channel layer, and first dielectric patterns interposed between the ferroelectric layer and the conductive layers, respectively. The gaps extending between the first dielectric patterns.

Abstract: A semiconductor device including a substrate that includes a cell array region and a peripheral circuit region; a cell transistor on the cell array region of the substrate; a peripheral transistor on the peripheral circuit region of the substrate; a first interconnection layer connected to the cell transistor; a second interconnection layer connected to the peripheral transistor; an interlayer dielectric layer covering the first interconnection layer; and a blocking layer spaced apart from the first interconnection layer, the blocking layer covering a top surface and a sidewall of the second interconnection layer.

Abstract: A non-volatile memory includes a substrate, a plurality of gate stacked strips and a plurality of contact plugs. The substrate includes a plurality of diffusion strips. The plurality of gate stacked strips are disposed over the diffusion strips, wherein each of the gate stacked strips includes a charge storage layer and a gate conductor layer stacked from bottom to top. The plurality of contact plugs are disposed on the diffusion strips between the gate stacked strips, wherein a sidewall of each of the gate conductor layer beside the contact plugs and above the diffusion strips has a step profile.

Abstract: A semiconductor memory device includes a substrate with a cell array region, a first interface region, and a second interface region, the cell array region being provided with active regions, bit lines on the cell array region and the second interface region, dielectric patterns on top surfaces of the bit lines and extending along the top surfaces of the bit lines and further extending onto the first interface region, a device isolation pattern on the substrate, and including a first portion on the cell array region and a second portion on the first interface region, the first portion defining the active regions, the second portion being provided with first recesses, and each first recess being disposed between two adjacent dielectric patterns, and first sacrificial semiconductor patterns disposed on the first interface region and in the first recesses. The first sacrificial semiconductor patterns include polycrystalline silicon.

Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.

Abstract: Disclosed is a semiconductor device having a memory cell which comprises a transistor having a control gate and a storage gate. The storage gate comprises an oxide semiconductor and is able to be a conductor and an insulator depending on the potential of the storage gate and the potential of the control gate. Data is written by setting the potential of the control gate to allow the storage gate to be a conductor, supplying a potential of data to be stored to the storage gate, and setting the potential of the control gate to allow the storage gate to be an insulator. Data is read by supplying a potential for reading to a read signal line connected to one of a source and a drain of the transistor and detecting the change in potential of a bit line connected to the other of the source and the drain.

Abstract: In an embodiment, a device includes: a first dielectric layer having a first sidewall; a second dielectric layer having a second sidewall; a word line between the first dielectric layer and the second dielectric layer, the word line having an outer sidewall and an inner sidewall, the inner sidewall recessed from the outer sidewall, the first sidewall, and the second sidewall; a memory layer extending along the outer sidewall of the word line, the inner sidewall of the word line, the first sidewall of the first dielectric layer, and the second sidewall of the second dielectric layer; and a semiconductor layer extending along the memory layer.

Abstract: A method for forming a magnetic memory device is disclosed. At least one magnetic tunneling junction (MTJ) stack is formed on the substrate. The MTJ stack comprises a reference layer, a tunnel barrier layer and a free layer. A top electrode layer is formed on the MTJ stack. A patterned sacrificial layer is formed on the top electrode layer. The MTJ stack is then subjected to a MTJ patterning process in a high-density plasma chemical vapor deposition (HDPCVD) chamber, thereby sputtering off the MTJ stack not covered by the patterned sacrificial layer. During the MTJ patterning process, sidewalls of layers or sub-layers of the MTJ stack are simultaneously passivated in the HDPCVD chamber by depositing a sidewall protection layer.

Abstract: A three-dimensional memory device includes a stacking structure, memory pillars, and conductive pillars. The stacking structure includes stacking layers stacked along a vertical direction, each stacking layer including a gate layer, a gate dielectric layer, and a channel layer. The gate layer, the gate dielectric layer, and the channel layer extend along a horizontal direction, and the gate dielectric layer is disposed between the gate layer and the channel layer. The memory pillars extend along the vertical direction and are laterally separated and in contact with the channel layer of each stacking layer. Each memory pillar comprises a first electrode, a second electrode, and a switching layer between the first and second electrodes. The conductive pillars extend along the vertical direction and are laterally separated and in contact with the channel layer of each stacking layer. The memory pillars and the conductive pillars are alternately arranged along the horizontal direction.

Abstract: The invention provides a microelectronic device comprising at least two memory cells each comprising a so-called selection transistor and a memory element associated with said selection transistor, each transistor comprising a channel in the form of a wire extending in a first direction (x), a gate bordering said channel, a source extending in a second direction (y), and a drain connected to the memory element, said transistors being stacked in a third direction (z) and each occupying a given altitude level in the third direction (z), the microelectronic device wherein the source and the drain are entirely covered by spacers projecting in the third direction (z) in a plane (xy). The invention also provides a method for manufacturing such a device.

Abstract: A new liner structure for improving memory cell design is disclosed that incorporates a boron nitride dielectric layer. An example memory device includes an array of memory cells with each of at least some of the memory cells having a stack of layers, the stack comprising at least one phase change layer. A dielectric layer is provisioned over one or more sidewalls of at least the phase change layer. The dielectric layer comprises both nitrogen and boron. The dielectric layer may be part of a liner structure that includes multiple layers, such as an alternating layer stack of boron nitride and silicon nitride. The dielectric layer can be deposited at low temperature (e.g., less than about 300° C.) while maintaining a low hydrogen content and a relatively high thermal conductivity.

Abstract: A memory cell includes: a resistive material layer comprising a first portion that extends along a first direction and a second portion that extends along a second direction, wherein the first and second directions are different from each other; a first electrode coupled to a bottom surface of the first portion of the resistive material layer; and a second electrode coupled to the second portion of the resistive material layer.

Abstract: A variable resistance memory device includes a first conductive line, a bipolar selection device on the first conductive line and electrically connected to the first conductive line, a second conductive line on the first conductive line and electrically connected to the bipolar selection device, a variable resistance layer on the second conductive line and electrically connected to the second conductive line, and a third conductive line on the variable resistance layer and electrically connected to the variable resistance layer.

Abstract: A multiple input device is disclosed. The multiple input device includes a semiconductor structure extending in a first direction, a first dielectric material surrounding a portion of the semiconductor structure, a floating gate on the first dielectric material and surrounding the portion of the semiconductor structure, and a second dielectric material on the floating gate and surrounding the portion of the semiconductor structure. The multiple input device also includes a plurality of control gates on the second dielectric material. At least one of the control gates extends vertically away from the semiconductor structure in a second direction and at least one of the control gates extends vertically away from the semiconductor structure in a third direction.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including a plurality of first transistors and at least one metal layer, where the at least one metal layer overlays the first single crystal layer, and where the at least one metal layer includes interconnects between the plurality of first transistors, the interconnects between the plurality of first transistors include forming first control circuits; a second level overlaying the at least one metal layer, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors, where the second level includes a plurality of first memory cells, the first memory cells each including at least one of the plurality of second transistors, where the third level includes a plurality of second memory cells, the second memory cells each including at least one of the plurality of third transistors, where at lea

Abstract: A nonvolatile memory device is provided. The device comprises a memory transistor. A first capacitor is coupled to the memory transistor. A second capacitor is coupled to the memory transistor. The second capacitor comprises a first electrode and a second electrode. The first capacitor and the second capacitor are connected to separate input terminals.

Abstract: A semiconductor memory device includes a select transistor and a floating gate transistor on a substrate. The select transistor includes a select gate, a select gate oxide layer and a drain doping region. The floating gate transistor includes a floating gate, a floating gate oxide layer, a source doping region, a first tunnel doping region and a second tunnel doping region under the floating gate, a first tunnel oxide layer on the first tunnel doping region, and a second tunnel oxide layer on the second tunnel doping region. The floating gate oxide layer is disposed between the first tunnel oxide layer and the second tunnel oxide layer. A lightly doped diffusion region surrounds the source doping region and the second tunnel doping region.