Abstract: A semiconductor memory device includes: a stacked structure including first and second select patterns spaced apart from each other in a first direction; a gate isolation layer extending in a second direction intersecting the first direction between the first and second select patterns; channel structures penetrating the stack structure; and first and second bit lines extending in the first direction, the first and second bit lines being adjacent to each other. The channel structures include: a first channel structure which penetrates the first select pattern and is spaced apart by a first distance from the gate isolation layer in the first direction; and a second channel structure which penetrates the second select pattern and is spaced apart by substantially the first distance from the gate isolation layer in the first direction. The first and second channel structures are respectively connected to the second and first bit lines.

Abstract: A memory device may be provided, including a base insulating layer, a bottom electrode arranged within the base insulating layer, a substantially planar switching layer arranged over the base insulating layer and a substantially planar top electrode arranged over the switching layer in a laterally offset position relative to the bottom electrode.

Abstract: A low-cost and low-voltage anti-fuse array includes a plurality of sub-memory arrays. In each sub-memory array, the anti-fuse transistor of all anti-fuse memory cells includes an anti-fuse gate commonly used by other anti-fuse transistors. These anti-fuse memory cells are arranged side by side between two adjacent bit-lines, wherein the anti-fuse memory cells in the same row are connected to different bit-lines, and all anti-fuse memory cells are connected to the same selection-line and different word-lines. The present invention utilizes the configuration of common source contacts to achieve a stable source structure and reduce the overall layout area, and meanwhile minimizes the types of control voltage to reduce leakage current.

Abstract: A nonvolatile memory device is provided. The device comprises a floating gate having a first finger and a second finger and an active region below the floating gate fingers. A first doped region is in the active region laterally displaced from the first floating gate finger on a first side. A second doped region is in the active region laterally displaced from the first floating gate finger on a second side. A third doped region is in the active region laterally displaced from the second floating gate finger and the second doped region.

Abstract: A microelectronic device comprises a stack structure, a stadium structure within the stack structure, and conductive contact structures. The stack structure comprises a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. Each of the tiers comprises one of the conductive structures and one of the insulative structures. The stadium structure comprises a forward staircase structure having steps comprising edges of the tiers, and a reverse staircase structure opposing the forward staircase structure and having additional steps comprising additional edges of the tiers. The conductive contact structures vertically extend to upper vertical boundaries of at least some of the conductive structures of the stack structure at the steps of the forward staircase structure and the additional steps of the reverse staircase structure, and are each integral and continuous with one of the conductive structures.

Abstract: Provided are a resistive random access memory and a method of manufacturing the same. The resistive random access memory includes a stacked structure and a bit line structure. The stacked structure is disposed on a substrate. The stacked structure includes a bottom electrode, a top electrode and a resistance-switching layer. The bottom electrode is disposed on the substrate. The top electrode is disposed on the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The bit line structure covers a top surface of the stacked structure and covers a portion of a sidewall of the stacked structure. The bit line structure is electrically connected to the stacked structure.

Abstract: A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.

Abstract: A MRAM device includes a magnetic tunnel junction containing a reference layer having a fixed magnetization direction, a free layer, and a nonmagnetic tunnel barrier layer located between the reference layer and the free layer, a negative-magnetic-anisotropy assist layer having negative magnetic anisotropy that provides an in-plane magnetization within a plane that is perpendicular to the fixed magnetization direction, and a first nonmagnetic spacer layer located between the free layer and the negative-magnetic-anisotropy assist layer.

Abstract: A method comprising forming a stack precursor comprising alternating first materials and second materials, the first materials and the second materials exhibit different melting points. A portion of the alternating first materials and second materials is removed to form a pillar opening through the alternating first materials and second materials. A sacrificial material is formed in the pillar opening. The first materials are removed to form first spaces between the second materials, the first materials formulated to be in a liquid phase or in a gas phase at a first removal temperature. A conductive material is formed in the first spaces. The second materials are removed to form second spaces between the conductive materials, the second materials formulated to be in a liquid phase or in a gas phase at a second removal temperature. A dielectric material is formed in the second spaces. The sacrificial material is removed from the pillar opening and cell materials are formed in the pillar opening.

Abstract: A semiconductor memory device includes a substrate including a peripheral circuit; an interconnection array disposed on the peripheral circuit; a cell stack structure disposed on the interconnection array, the cell stack structure including gate electrodes stacked in a vertical direction to form a cell step structure; and a dummy stack structure disposed on the interconnection array, the dummy stack structure including sacrificial layers stacked in the vertical direction to form a dummy step structure parallel to the cell step structure. The interconnection array includes a first lower conductive pattern including a center region overlapping with a slit between the cell step structure and the dummy step structure, a first region extending to overlap with the dummy step structure from the center region, and a second region extending to overlap with the cell step structure from the center region.

Abstract: A three-dimensional memory device includes a first word-line region including a first alternating stack of first word lines and continuous insulating layers, first memory stack structures vertically extending through the first alternating stack, a second word-line region comprising a second alternating stack of second word lines and the continuous insulating layers, second memory stack structures vertically extending through the second alternating stack, plural dielectric separator structures located between the first word-line region and the second word-line region, and at least one bridge region located between the plural dielectric separator structures and between the between the first word-line region and the second word-line region. The continuous insulating layers extend through the at least one bridge region between the first alternating stack in the first word-line region and the second alternating stack in the second word-line region.

Abstract: A nonvolatile memory device may be provided. The nonvolatile memory device comprises an active region, an n-well region and an isolation region separating the active region and the n-well region. A floating gate may be provided. The floating gate may be arranged over a portion of the active region and over a first portion of the n-well region. A first doped region in the active region may be laterally displaced from the floating gate on a first side and a second doped region in the active region may be laterally displaced from the floating gate on a second side opposite to the first side. A contact may be arranged over the n-well region, whereby the contact may be laterally displaced from a first corner of the floating gate over the first portion of the n-well region. A silicide exclusion layer may be arranged at least partially over the floating gate.

Abstract: A semiconductor memory device comprises: a semiconductor substrate comprising a first and a second surface; a first and a second electrode provided on a first surface side; a third and a fourth electrode provided on a second surface side; a first through-electrode connected to the first and the third electrode; a second through-electrode connected to the second and the fourth electrode; and a first insulating layer comprising a first and a second portion. The semiconductor substrate comprises: a first impurity region of N type facing a surface of the first through-electrode via the first portion; a second impurity region of N type facing a surface of the second through-electrode via the second portion; and a third impurity region of P type provided between the first and the second impurity region.

Abstract: A semiconductor memory includes: a substrate including a cell region, first and second peripheral circuit regions disposed on two sides of the cell region; first lines extending across the cell region and the first peripheral circuit region; second lines disposed over the first lines and extending across the cell region and the second peripheral circuit region; a contact plug disposed in the second peripheral circuit region and connected to the second line; third lines disposed over the second lines and respectively overlapping the second lines; and first memory cells disposed in the cell region and located at intersections of the first lines and the second lines between the first lines and the second lines, wherein a portion of the third line, located in the cell region contacts the second line, and another portion of the third line located over the contact plug is spaced apart from the second line.

Abstract: A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.

Abstract: A 3D memory device and a method of manufacturing the same, the device including a substrate including a cell and an extension region; a cell stack including insulation layers and word lines alternately stacked on the substrate; channel structures vertically passing through the cell stack; a word line separation layer vertically passing through the cell stack and extending lengthwise in a first direction; a contact plug vertically connected to the word lines on the extension region; and a bit line extending lengthwise in a second direction on the channel structures, wherein each of the word lines includes an inner pattern including polysilicon; and an outer pattern including metal, the outer pattern surrounds an outer surface of the inner pattern, the channel structures vertically pass through the inner pattern, and the contact plug is on the outer pattern.

Abstract: There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes a first select group and a second select group isolated from each other by an isolation insulating layer; an upper gate stack structure extending to overlap with the first select group, the isolation insulating layer, and the second select group; channel structures extending to penetrate the first select group, the second select group, and the upper gate stack structure; and a vertical connection structure spaced apart from the first select group, the second select group, and the upper gate stack structure, the vertical connection structure extending in parallel to the channel structures.

Abstract: Provided is a flash memory includes a gate stack structure, a channel pillar, a first conductive pillar, a second conductive pillar, and a gate dielectric layer. The gate stack structure includes a plurality of gate layers electrically insulated from each other. Each gate layer includes a ferroelectric portion disposed between a sidewall of a first portion and a sidewall of a second gate portion. A thickness of the second gate portion is smaller than a thickness of the first gate portion. A channel pillar penetrates the gate stack structure. The first and second conductive pillars are disposed in the channel pillar. The first and second conductive pillars are separated from each other, and are each connected to the channel pillar. The gate dielectric layer is disposed between another sidewall of the first gate portion and the channel pillar.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over at least one source layer, and groups of memory opening fill structures vertically extending through the alternating stack. Each memory opening fill structure can include a vertical stack of memory elements and a vertical semiconductor channel. A plurality of source-side select gate electrodes can be laterally spaced apart by source-select-level dielectric isolation structures. Alternatively or additionally, the at least one source layer may include a plurality of source layers. A group of memory opening fill structures can be selected by selecting a source layer and/or by selecting a source-level electrically conductive layer.

Abstract: A low-voltage anti-fuse element is provided with a first gate dielectric layer and a first gate sequentially disposed on a substrate. A first ion-doped region is formed in the substrate on one side of the first gate. The first gate includes a body portion and a sharp corner portion extending and gradually reducing from one side of the body portion both adjacent to the first gate dielectric layer. During the operation, the principle of higher density of charges at sharp corners is utilized. When the write voltage is applied between the first gate and the first ion-doped region, a portion of the first gate dielectric layer below the sharp corner portion is liable to break down. Therefore, the breakdown voltage is reduced to achieve the purpose of reducing current consumption, while decreasing the gate area, the element size and production costs.