Abstract: Resistive processing unit including: a plurality of transistors each having a lithium-doped region, wherein the plurality of transistors are arranged in an array to provide resistance; at least one first transmission line electrically connected to a source region of each transistor in at least one column of the array; at least one second transmission line electrically connected to a drain region of each transistor in at least one row of the array; and at least one third transmission line electrically connected to a gate region of the plurality of transistors in at least one row of the array; wherein application of an electrical voltage to the at least one first transmission line, the at least one second transmission line or the at least one third transmission line mobilizes lithium ions in the lithium region, thereby affecting a channel resistance of at least one transistor in the plurality of transistors.

Abstract: A memory cell including a two-terminal re-writeable non-volatile memory element having at least two layers of conductive metal oxide (CMO), which, in turn, can include a first layer of CMO including mobile oxygen ions, and a second layer of CMO formed in contact with the first layer of CMO to cooperate with the first layer of CMO to form an ion obstruction barrier. The ion obstruction barrier is configured to inhibit transport or diffusion of a subset of mobile ion to enhance, among other things, memory effects and cycling endurance of memory cells. At least one layer of an insulating metal oxide that is an electrolyte to the mobile oxygen ions and configured as a tunnel barrier is formed in contact with the second layer of CMO.

Abstract: An electronic device includes a semiconductor memory, wherein the semiconductor memory may include: a cell mat disposed over a substrate, the cell mat including a plurality of memory cells; an insulating layer disposed over the cell mat; a conductive pattern disposed over the insulating layer, the conductive pattern overlapping a first portion of the cell mat without overlapping a second portion of the cell mat; and a shielding layer disposed in the insulating layer, the shielding layer overlapping at least the second portion of the cell mat, the shielding layer being capable of blocking plasma.

Abstract: A memory device includes a semiconductor substrate, a first conductive layer, a plurality of second conductive layers, a plurality insulating layers, at least one contact plug and at least one dummy plug. The first conductive layer is disposed on the semiconductor substrate. The insulating layers are disposed on the first conductive layer. The second conductive layers are alternatively stacked with the insulating layers and insulated from the first conductive layer. The contact plug passes through the insulating layers and the second conductive layers, insulates from the second conductive layers and electrically contacts to the first conductive layer. The dummy plug, corresponds to the at least one contact plug, passes through the insulating layers and the second conductive layers, and insulates from the second conductive layers and the first conductive layer.

Abstract: Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described.

Abstract: The disclosed technology relates generally to spintronics, and more particularly to a magnetic majority gate device. In one aspect, a magnetic majority gate device includes a magnetic propagation layer and at least one input transducer. The magnetic propagation layer includes a plurality of magnetic buses configured to guide propagating magnetic domain walls along longitudinal directions corresponding to elongated directions of the magnetic buses. The plurality of magnetic buses includes a plurality of input magnetic buses, where each of the input magnetic buses has a corresponding input site configured to receive a corresponding input magnetic domain wall. At least one input transducer at a corresponding input site is configured to convert a digital input electrical signal into an input magnetic domain wall, such that a magnetization state of the input magnetic domain wall corresponds to a digital logic state of the digital input electrical signal.

Abstract: A method of fabricating a resistive memory array includes forming a plurality of insulators and a conductive structure on a first substrate, performing a resistor-forming process to transform the insulators into a plurality of resistors, polishing the conductive structure to expose a plurality of contact points respectively electrically connected to the resistors, providing a second substrate having a plurality of transistors and a plurality of interconnect pads, bonding respectively the interconnect pads and the contact points, and removing the first substrate from the resistors and the conductive structure.

Abstract: Described herein are multi-deck memory devices with an inverted deck. For example, in one embodiment a memory device includes a first deck of memory cells including layers of material, including a layer of storage material and a layer of selector material, and a second deck of memory cells over the first deck of memory cells, the second deck comprising layers of material in an order opposite relative to the first deck. In one such embodiment, conductive bitlines located between the first and second decks are common to both decks. Inverting the second deck can enable operating the decks symmetrically despite accessing the decks with opposite polarity voltages.

Abstract: A semiconductor memory device includes free magnetic pattern on a substrate, a reference magnetic pattern on the free magnetic pattern, the reference magnetic pattern including a first pinned pattern, a second pinned pattern, and an exchange coupling pattern between the first and second pinned patterns, a tunnel barrier pattern between the reference magnetic pattern and the free magnetic pattern, a polarization enhancement magnetic pattern between the tunnel barrier pattern and the first pinned pattern, and an intervening pattern between the polarization enhancement magnetic pattern and the first pinned pattern, wherein the first pinned pattern includes first ferromagnetic patterns and anti-ferromagnetic exchange coupling patterns which are alternately stacked.

Abstract: A memory device according to an embodiment includes a first conductive layer, a second conductive layer; and a first metal oxide layer provided between the first conductive layer and the second conductive layer. The first metal oxide layer includes titanium oxide, the first metal oxide layer has a first region and a second region, a mole fraction of anatase titanium oxide in the titanium oxide of the first region is a first mole fraction, and a mole fraction of anatase titanium oxide in the titanium oxide of the second region is a second mole fraction lower than the first mole fraction.

Abstract: Systems and methods for providing a phase change memory that includes a phase change material, such as a chalcogenide material, in series with a heating element that comprises multiple thermal interfaces are described. The multiple thermal interfaces may cause the heating element to have a reduced bulk thermal conductivity or a lower heat transfer rate across the heating element without a corresponding reduction in electrical conductivity. The phase change material may comprise a germanium-antimony-tellurium compound or a chalcogenide glass. The heating element may include a plurality of conducting layers with different thermal conductivities. In some cases, the heating element may include two or more conducting layers in which the conducting layers comprise the same electrically conductive material or compound but are deposited or formed using different temperatures, carrier gas pressures, flow rates, and/or film thicknesses to create thermal interfaces between the two or more conducting layers.

Abstract: A memory cell comprising includes a silicon-on-insulator (SOI) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (SOI) substrate, and a charge injector region. The floating body transistor is configured to have more than one stable state through an application of a bias on the charge injector region.

Abstract: Embodiments of the present invention provide systems and methods for the fabrication of a crossbar array fabrication of resistive random access memory (RRAM) cells. The array structure contains large grain copper and its alloy or silver and its alloy. A metal cap and spacer are used to protect copper or silver from chemical modifications during memory cell patterning.

Abstract: A semiconductor device comprises four SRAM cells in four quadrants of a region of the semiconductor device, wherein the four SRAM cells include FinFET transistors comprising gate features engaging fin active lines, and the fin active lines of the four SRAM cells have reflection symmetry with respect to an imaginary line dividing the four quadrants along a first direction.

Abstract: There is provided a non-volatile memory device which can enhance the reliability of a memory device by using an ovonic threshold switch (OTS) selection element including a multilayer structure. The non-volatile memory device includes a first electrode and a second electrode spaced apart from each other, a selection element layer between the first electrode and the second electrode, which is closer to the second electrode rather than to the first electrode, and which includes a first chalcogenide layer, a second chalcogenide layer, and a material layer disposed between the first and second chalcogenide layers. The first chalcogenide layer including a first chalcogenide material, and the second chalcogenide layer including a second chalcogenide material. A memory layer between the first electrode and the selection element layer includes a third chalcogenide material which is different from the first and second chalcogenide materials.

Abstract: A storage element includes a storage layer, a fixed magnetization layer, a spin barrier layer, and a spin absorption layer. The storage layer stores information based on a magnetization state of a magnetic material. The fixed magnetization layer is provided for the storage layer through a tunnel insulating layer. The spin barrier layer suppresses diffusion of spin-polarized electrons and is provided on the side of the storage layer opposite the fixed magnetization layer. The spin absorption layer is formed of a nonmagnetic metal layer causing spin pumping and provided on the side of the spin barrier layer opposite the storage layer. A direction of magnetization in the storage layer is changed by passing current in a layering direction to inject spin-polarized electrons so that information is recorded in the storage layer and the spin barrier layer includes at least a material selected from oxides, nitrides, and fluorides.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a horizontal layer, which can be formed over a lower-interconnect-level dielectric material layer overlying a substrate. Structural integrity of insulating layers vertically spaced from one another by backside recesses during replacement of sacrificial material layers with electrically conductive layers can be enhanced by forming electrically inactive laterally-insulated support structures concurrently with formation of laterally-insulated conductive via structures that vertically extend through each layer in the alternating stack and through the horizontal layer and to lower-interconnect-level metal interconnect structures. Alternatively or additionally, the structural integrity of insulating layers during the replacement process can be enhanced by M×N array of semiconductor-containing support structures that extend through staircase region and having same materials as memory stack structures.

Abstract: A resistive memory device includes an alternating stack of insulating layers and electrically conductive layers. Sidewalls of the electrically conductive layers are laterally recessed relative to sidewalls of the insulating layers to define laterally recessed regions. Discrete clam-shaped barrier material portions are located within the laterally recessed regions. Middle electrodes include a protrusion portion embedded within a respective one of the discrete clam shaped barrier material portions and a vertically-extending portion located outside the laterally recessed regions and having a greater vertical extent than the embedded portion. A resistive memory material layer contacts the vertically-extending portion of each of the middle electrodes. A vertical conductive line contacts the resistive memory material layer.

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

Abstract: A magnetoresistive random access memory device includes a free layer, a tunnel barrier layer, an insulation barrier layer, a pinned layer, and a vertical polarizer structure. The tunnel barrier layer and the insulation barrier layer directly contacts different surfaces of the free layer. The pinned layer structure contacts the tunnel barrier layer and includes at least one pinned layer. The vertical polarizer structure contacts the insulation barrier layer and includes a plurality of magnetization multi-layered structures sequentially stacked. Each magnetization multi-layered structure includes a non-magnetic layer and a magnetic layer sequentially stacked. The pinned layer and the magnetic layer have magnetization directions anti-parallel to each other.