Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.

Abstract: Solid-state memory having a non-linear current-voltage (I-V) response is provided. By way of example, the solid-state memory can be a selector device. The selector device can be formed in series with a non-volatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the non-volatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.

Abstract: The present disclosure provides a static random access memory (SRAM) cell comprising a first inverter including a first pull-up (PU) device, a first pull-down (PD) device, and a second PD device; a second inverter cross-coupled to the first inverter, the second inverter including a second PU device, a third PD device, and a fourth PD device; first and second pass gate (PG) devices coupled to the first inverter to form a first port; and third and fourth PG devices coupled to the second inverter to form a second port. The first and second PG devices, the first PD device of the first inverter, and the third PD device of the second inverter are configured on a first active region. The third and fourth PG devices, the second PD device of the first inverter, and the fourth PD device of the second inverter are configured on a second active region.

Abstract: Electronic devices have a semiconductor memory unit including a magnetization compensation layer in a contact plug. One implementation of the semiconductor memory unit includes a variable resistance element having a stacked structure of a first magnetic layer, a tunnel barrier layer, and a second magnetic layer, and a contact plug arranged in at least one side of the variable resistance element and comprising a magnetization compensation layer. Another implementation includes a variable resistance element having a stacked structure of a first magnetic layer having a variable magnetization, a tunnel barrier layer, and a second magnetic layer having a pinned magnetization; and a contact plug arranged at one side of and separated from the variable resistance element to include a magnetization compensation layer that produces a magnetic field to reduce an influence of a magnetic field of the second magnetic layer on the first magnetic layer.

Abstract: A layout design usable for manufacturing a memory cell includes a first and second active area layout pattern associated with forming a first and second active area, an isolation region outside the first and second active area, a first polysilicon layout pattern associated with forming a first polysilicon structure, a second polysilicon layout pattern associated with forming a second polysilicon structure, a first interconnection layout pattern associated with forming a first interconnection structure, and a second interconnection layout pattern associated with forming a second interconnection structure. The first active area does not overlap the second active area. The first polysilicon layout pattern overlaps the first active area layout pattern. The second polysilicon layout pattern overlaps the first active area layout pattern and the second active area layout pattern. The first interconnection layout pattern overlaps the second active area layout pattern.

Abstract: Providing for fabrication, construction, and/or assembly of a resistive random access memory (RRAM) cell is described herein. The RRAM cell can exhibit a non-linear current-voltage relationship. When arranged in a memory array architecture, these cells can significantly mitigate sneak path issues associated with conventional RRAM arrays.

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

Abstract: A nonvolatile semiconductor memory device is provided with a magnetoresistive effect element formed on a substrate, and an insulating film formed above the substrate to cover the magnetoresistive effect element. The insulating film is formed of a silicon nitride, and has a portion of a higher nitrogen concentration than a surface portion thereof.

Abstract: A memory device includes n (n being an integer of 2 or more) resistance change films being series connected to each other. Each of the resistance change films is a superlattice film in which plural pairs of a first crystal layer made of a first compound and a second crystal layer made of a second compound are alternately stacked. An average composition of the entire resistance change film or an arrangement pitch of the first crystal layers and the second crystal layers are mutually different among the n resistance change films.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of first planes and a plurality of second planes which are disposed over a substrate and alternately stacked in a vertical direction over the substrate, where each of the first planes includes a plurality of first lines which extends in a first direction parallel to the substrate and each of the second planes includes a plurality of second lines which extends in a second direction parallel to the substrate and intersecting with the first direction, a plurality of variable resistance patterns which is interposed between each of the first planes and each of the second planes, each of the variable resistance patterns being disposed at a cross point between a first line and a corresponding second lines, and an air-gap which is disposed between neighboring variable resistance patterns.

Abstract: A memory device includes an array of floating gate memory cells. Adjacent memory cells are separated by a plurality of air gaps that electrically decouple respective active regions of adjacent memory cells from one another. Additionally, the air gaps electrically decouple an active region of a memory cell from a floating gate of an adjacent memory cell.

Abstract: Roughly described, a memory device has a multilevel stack of conductive layers. Vertically oriented pillars each include series-connected memory cells at cross-points between the pillars and the conductive layers. SSLs run above the conductive layers, each intersection of a pillar and an SSL defining a respective select gate of the pillar. Bit lines run above the SSLs. The pillars are arranged on a regular grid which is rotated relative to the bit lines. The grid may have a square, rectangle or diamond-shaped unit cell, and may be rotated relative to the bit lines by an angle ? where tan(?)=±X/Y, where X and Y are co-prime integers. The SSLs may be made wide enough so as to intersect two pillars on one side of the unit cell, or all pillars of the cell, or sufficiently wide as to intersect pillars in two or more non-adjacent cells.

Abstract: A method of fabricating a resistive memory array includes forming a plurality of insulators and a conductive structure on a first substrate, performing a resistor-forming process to transform the insulators into a plurality of resistors, polishing the conductive structure to expose a plurality of contact points respectively electrically connected to the resistors, providing a second substrate having a plurality of transistors and a plurality of interconnect pads, bonding respectively the interconnect pads and the contact points, and removing the first substrate from the resistors and the conductive structure.

Abstract: A magnetic cell core includes at least one stressor structure proximate to a magnetic region (e.g., a free region or a fixed region). The magnetic region may be formed of a magnetic material exhibiting magnetostriction. During switching, the stressor structure may be subjected to a programming current passing through the magnetic cell core. In response to the current, the stressor structure may alter in size. Due to the size change, the stressor structure may exert a stress upon the magnetic region and, thereby, alter its magnetic anisotropy. In some embodiments, the MA strength of the magnetic region may be lowered during switching so that a lower programming current may be used to switch the magnetic orientation of the free region. In some embodiments, multiple stressor structures may be included in the magnetic cell core. Methods of fabrication and operation and related device structures and systems are also disclosed.

Abstract: A memory device includes a semiconductor body having a first conductivity type, a first terminal in the semiconductor body having a second conductivity type, a channel region having the first conductivity type surrounding the first terminal, and a second terminal having the second conductivity type surrounding the channel region. A connector is in contact with the first terminal, and can be connected to a bit line in an overlying patterned conductor layer. Memory material is disposed over the channel region, and can include a dielectric charge storage structure. A control gate surrounds the first terminal and is disposed over the memory material. A conductive line surrounds the control gate and is in contact with the second terminal. The control gate and the conductive line can be ring shaped.

Abstract: An electronic device including a semiconductor memory unit that includes a cell structure having two memory cells, which share one selector, wherein the cell structure includes first electrodes, variable resistance patterns and second electrodes which are symmetrically disposed on both sides of the selector.

Abstract: A phase change memory cell includes a first circuit and a second circuit. The first circuit includes a first electrode, a carbon nanotube wire and a second electrode electrically connected in series; wherein the first circuit is adapted to write data into the phase change memory cell or reset the phase change memory cell. The second circuit includes a third electrode, a phase change layer, the carbon nanotube wire, and the first electrode or the second electrode electrically connected in series, wherein the second circuit is adapted to read data from the phase change memory cell or reset the phase change memory cell, the carbon nanotube wire includes a bending portion, the third electrode is spaced from the bending portion, and the phase change layer covers the bending portion of the carbon nanotube wire.

Abstract: A three-dimensional integrated circuit non-volatile memory array includes a memory array with first and second NAND memory cell string stacks having opposite orientations, where each NAND memory cell string includes a plurality of transistors and a source line contact connected in series between a bit line and string extension region which extends from the source line contact and past a first self-aligned SSL gate electrode located on a peripheral end of the NAND memory cell string, and also includes a string select transistor formed with a second self-aligned SSL connected in series between the bit line and the plurality of transistors, where the first and second self-aligned SSL gate electrodes are shared between adjacent NAND memory cell strings having opposite orientations.

Abstract: A memory includes a three-dimensional array including a plurality of levels is described. Each level includes a bit line pad, a source line pad, and a plurality of strips of semiconductor material extending between the bit line pad and the source line pad. The source line pad includes at least one n-type region and at least one p-type region. The memory includes word lines coupled to the plurality of strips in the plurality of levels. The memory includes data storage elements between the word lines and the strips of semiconductor material, whereby memory cells are disposed at cross-points of the strips and the word lines. The memory also includes circuitry coupled to the n-type region and the p-type region of the source line pad, configured to selectively enable current flow in the strips extending from the source line pad and one of the n-type region and the p-type region.

Abstract: Variable resistance memory devices and methods of forming the same are disclosed. The devices may include an additional barrier layer that is a portion of a variable resistance layer and that is formed before forming a horizontal electrode layer. Due to the presence of the additional barrier layer, it may be possible to cure loss or damage of the variable resistance layer.