Patents Examined by Allison P. Bernstein
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Patent number: 9620711Abstract: An electronic device includes a semiconductor unit. The semiconductor unit includes a first electrode and a second electrode spaced apart from each other in a first direction; and a first material layer interposed between the first electrode and the second electrode and having a variable resistance characteristic or a threshold switching characteristic, wherein the first electrode, or the second electrode, or both includes a plurality of sub-electrodes and a plurality of second material layers that are alternately arranged in the first direction, and wherein each of the second material layers has a thickness that is sufficiently small to enable the second material layers to exhibit an ohmic-like behavior for a current flowing therein at an operating current of the semiconductor unit.Type: GrantFiled: June 11, 2015Date of Patent: April 11, 2017Assignee: SK HYNIX INC.Inventor: Hyung-Dong Lee
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Patent number: 9614007Abstract: Some embodiments include a memory array having a first memory cell adjacent to a second memory cell along a lateral direction. The second memory cell is vertically offset relative to the first memory cell. Some embodiments include a memory array having a series of data/sense lines extending along a first direction, a series of access lines extending along a second direction, and memory cells vertically between the access lines and data/sense lines. The memory cells are arranged in a grid having columns along the first direction and rows along the second direction. Memory cells in a common column and/or row as one another are arranged in two alternating sets, with a first set having memory cells at a first height and a second set having memory cells at a second height vertically offset relative to the first height. Some embodiments include methods of forming memory arrays.Type: GrantFiled: July 20, 2015Date of Patent: April 4, 2017Assignee: Micron Technology, Inc.Inventors: Mattia Boniardi, Andrea Redaelli
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Patent number: 9614006Abstract: Some embodiments include vertical stacks of memory units, with individual memory units each having a memory element, a wordline, a bitline and at least one diode. The memory units may correspond to cross-point memory, and the diodes may correspond to band-gap engineered diodes containing two or more dielectric layers sandwiched between metal layers. Tunneling properties of the dielectric materials and carrier injection properties of the metals may be tailored to engineer desired properties into the diodes. The diodes may be placed between the bitlines and the memory elements, or may be placed between the wordlines and memory elements. Some embodiments include methods of forming cross-point memory arrays. The memory arrays may contain vertical stacks of memory unit cells, with individual unit cells containing cross-point memory and at least one diode.Type: GrantFiled: September 25, 2015Date of Patent: April 4, 2017Assignee: Micron Technology, Inc.Inventor: Chandra Mouli
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Patent number: 9607686Abstract: A semiconductor memory device includes data path circuits and control circuits alternately disposed along a first direction. A first metal layer is disposed on the data path circuits and control circuits. Each of data path circuits includes a memory cells disposed in rows along the first direction and columns along a second direction crossing the first direction and a read/write circuit disposed at an end of the columns of memory cells. At least one pair of adjacent columns of memory cells has an electrical separation between the gate polysilicon layer the pair of adjacent memory cell columns—that is, gate conductor layer of the adjacent memory columns are electrically distinct. A word line in the first metal layer is segmented along the first direction into separately addressable portions.Type: GrantFiled: August 26, 2015Date of Patent: March 28, 2017Assignee: Kabushiki Kaisha ToshibaInventor: Yukihiro Fujimoto
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Patent number: 9599587Abstract: An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.Type: GrantFiled: September 5, 2014Date of Patent: March 21, 2017Assignee: NXP USA, INC.Inventors: Patrice M. Parris, Weize Chen, Richard J. De Souza, Md M. Hoque, John M. McKenna
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Patent number: 9595604Abstract: Provided is an electronic element that functions as a switch or memory without using metal nanoparticle. The electronic element includes: one electrode 5A and an other electrode 5B arranged to have a nanogap therebetween; and halide ion 6 provided between the electrodes 5A and 5B; and on one of the electrodes.Type: GrantFiled: March 9, 2014Date of Patent: March 14, 2017Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCYInventors: Yutaka Majima, Toshiharu Teranishi, Yasuo Azuma, Masanori Sakamoto, Shinya Kano, Daniel Eduardo Hurtado Salinas
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Patent number: 9595562Abstract: A memory cell structure, a method of manufacturing a memory, and a memory apparatus that conform a memory cell structure of an MRAM, which reduces resistance of drawn wiring to be connected to an MTJ, reduces an area of a memory cell, and avoids performance degradation of the MTJ due to heat are provided. A memory cell includes: a transistor with a first diffusion layer formed in a bottom portion of a concave portion, and a second diffusion layer formed in upper end portions of two opposing sidewall portions of the concave portion, to form channels at portions between the first and second diffusion layers in the two sidewall portions; and a memory element that is disposed below the first diffusion layer. The first diffusion layer is electrically connected to the memory element via a contact formed after the silicon substrate is thinned.Type: GrantFiled: October 10, 2014Date of Patent: March 14, 2017Assignee: Sony CorporationInventors: Taku Umebayashi, Shunichi Sukegawa, Takashi Yokoyama, Masanori Hosomi, Yutaka Higo
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Patent number: 9590171Abstract: An electronic device in accordance with this technology includes semiconductor memory. The semiconductor memory may include a magnetization-pinned layer configured to include a first magnetic layer, a second magnetic layer, and a non-magnetic layer interposed between the first magnetic layer and the second magnetic layer, a free magnetization layer spaced apart from the magnetization-pinned layer, a tunnel barrier layer interposed between the magnetization-pinned layer and the free magnetization layer, and a magnetic spacer configured to come in contact with a side of the first magnetic layer and at least part of a side of the second magnetic layer.Type: GrantFiled: March 14, 2014Date of Patent: March 7, 2017Assignee: SK hynix Inc.Inventors: Jin-Ho Lee, Ki-Seon Park
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Patent number: 9588890Abstract: The disclosed technology provides an electronic device includes a semiconductor memory that includes a first contact plug over a substrate; an interlayer dielectric layer located over the first contact plug and having a hole which exposes at least a portion of the first contact plug; a first electrode layer formed along a sidewall and a bottom surface of the hole to be in contact with the first contact plug; a variable resistance layer over the first electrode layer and structured to include (1) a first portion that extends along the sidewall of the hole in a direction perpendicular to the substrate and exhibits a variable resistance and (2) a second portion that is parallel to the bottom surface of the hole and does not exhibit a variable resistance, and a second electrode layer formed over the variable resistance layer.Type: GrantFiled: January 16, 2015Date of Patent: March 7, 2017Assignee: SK hynix Inc.Inventor: In-Hoe Kim
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Patent number: 9583695Abstract: A magnetic logic unit (MLU) cell includes a first magnetic tunnel junction and a second magnetic tunnel junction, each magnetic tunnel junction including a first magnetic layer having a first magnetization, a second magnetic layer having a second magnetization, and a tunnel barrier layer between the first and second layer. A field line for passing a field current such as to generate an external magnetic field is adapted to switch the first magnetization. The first magnetic layer is arranged such that the magnetic tunnel junction magnetization varies linearly with the generated external magnetic field. An MLU amplifier includes a plurality of the MLU cells. The MLU amplifier has large gains, extended cut off frequencies and improved linearity.Type: GrantFiled: September 12, 2013Date of Patent: February 28, 2017Assignee: CROCUS TECHNOLOGY SAInventors: Ioan Lucian Prejbeanu, Bernard Dieny, Kenneth MacKay, Bertrand Cambou
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Patent number: 9577182Abstract: A magnetoresistance effect element and a magnetic memory having thermal stability expressed by a thermal stability factor of 70 or more even with a fine junction size. The magnetoresistance effect element includes a first magnetic layer of an invariable magnetization direction forming a reference layer, a second magnetic layer of a variable magnetization direction forming a recording layer, and a first non-magnetic layer disposed between the first and second magnetic layers in a thickness direction of the first and second magnetic layers. At least one of the first and second magnetic layers has the following relationship between D (nm) and t (nm): D<0.9t+13, where D is a junction size corresponding to the length of a longest straight line on an end surface perpendicular to the thickness direction, and t is a layer thickness. The junction size is 30 nm or less.Type: GrantFiled: October 20, 2014Date of Patent: February 21, 2017Assignee: TOHOKU UNIVERSITYInventors: Shoji Ikeda, Hideo Sato, Shunsuke Fukami, Michihiko Yamanouchi, Fumihiro Matsukura, Hideo Ohno, Shinya Ishikawa
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Patent number: 9570516Abstract: A method for fabricating 3-D cross-point memory arrays, and more particularly to fabricating phase change memory (PCM) and resistive RAM (ReRAM or RRAM) 3-D memory arrays having a cell size footprint of 4F2. The method for forming a plurality of layers of memory cells using a limited number of photolithographic patterning steps is applicable to memory devices having single or multiple storage bits per cell, such as cells having anywhere from one to eight bits per cell or more. These bits are stacked three dimensionally and include memory cells based on phase change material, on resistive change material, on magnetic field alignment, on mechanical switching, and on other memory cells based on other information storage technologies.Type: GrantFiled: December 11, 2015Date of Patent: February 14, 2017Assignee: HGST, Inc.Inventor: Daniel Robert Shepard
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Patent number: 9553207Abstract: A nonvolatile memory (“NVM”) bitcell includes a capacitor, a transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is used to program and erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The transistor is used to read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read, write, and/or erase operations.Type: GrantFiled: September 25, 2013Date of Patent: January 24, 2017Assignee: Synopsys, Inc.Inventors: Andrew E. Horch, Troy N. Gilliland
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Patent number: 9548093Abstract: A magnetic memory element includes a first magnetic unit, a second magnetic unit, a third magnetic unit, a read/write unit, a first electrode, a second electrode, a third electrode, a first current source, the second current source. The third magnetic unit is connected to one end in the first direction of the first magnetic unit and one end in the first direction of the second magnetic unit. The read/write unit includes a nonmagnetic layer and a pinned layer. The nonmagnetic layer is connected to the third magnetic unit. The pinned layer is connected to the nonmagnetic layer. The first current source causes a current to flow between the third electrode and at least one of the first electrode or the second electrode. The second current source causes a current to flow between the first electrode and the second electrode.Type: GrantFiled: May 27, 2015Date of Patent: January 17, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Takuya Shimada, Hirofumi Morise, Shiho Nakamura, Tsuyoshi Kondo, Yasuaki Ootera, Michael Arnaud Quinsat
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Patent number: 9548119Abstract: A memory cell comprising includes a silicon-on-insulator (SOI) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (SOI) substrate, and a charge injector region. The floating body transistor is configured to have more than one stable state through an application of a bias on the charge injector region.Type: GrantFiled: January 15, 2015Date of Patent: January 17, 2017Assignee: Zeno Semiconductor, IncInventors: Jin-Woo Han, Yuniarto Widjaja
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Patent number: 9548444Abstract: Memory cells including cell cores having free regions are disclosed. The free regions exhibit a strain that affects a magnetization orientation within the cell core. A stressor structure may exert a stress upon at least a portion of the cell core to effect the strain state of the free region. Also disclosed are semiconductor device structures and systems including such memory cells as well as methods for forming such memory cells.Type: GrantFiled: April 13, 2015Date of Patent: January 17, 2017Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Wayne I. Kinney
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Patent number: 9543311Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.Type: GrantFiled: February 18, 2015Date of Patent: January 10, 2017Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: Marc Mantelli, Stephan Niel, Arnaud Regnier, Francesco La Rosa, Julien Delalleau
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Patent number: 9543153Abstract: An integrated circuit arranged on a silicon-on-insulator (SOI) substrate region is provided. The SOI substrate region is made up of a handle wafer region, an oxide layer arranged over the handle wafer region, and a silicon layer arranged over the oxide layer. A recess extends downward from an upper surface of the silicon layer and terminates in the handle wafer region, thereby defining a recessed handle wafer surface and sidewalls extending upwardly from the recessed handle wafer surface to meet the upper surface of the silicon layer. A first semiconductor device is disposed on the recessed handle wafer surface. A second semiconductor device is disposed on the upper surface of the silicon layer.Type: GrantFiled: July 16, 2014Date of Patent: January 10, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Kai-Shyang You
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Patent number: 9542979Abstract: A memory structure includes N array regions and N page buffers coupled to the N array regions, respectively. N is an integer ?2. Each of the N array regions includes a 3D array of a plurality of memory cells. The memory cells have a lateral distance d between two adjacent memory cells on a horizontal cell plane of the 3D array. Each of the N array regions further includes a plurality of conductive lines. The conductive lines are disposed over and coupled to the 3D array. The conductive lines have a pitch p, and p/d=? to ½. The N array regions and the N page buffers are arranged on one line along an extension direction of the conductive lines.Type: GrantFiled: August 25, 2015Date of Patent: January 10, 2017Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventor: Shih-Hung Chen
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Patent number: 9543002Abstract: The transistor layer is disposed above or below the memory layer and includes a transistor. The wiring line layer connects the memory layer and the transistor layer. The memory cell array comprises a plurality of select gate lines connected to gates of a plurality of the select transistors aligned in a third direction. The wiring line layer comprises: a first connecting wiring line connected to a first select gate line of the plurality of select gate lines and extending in the third direction; and a second connecting wiring line connected to a second select gate line adjacent in a second direction to the first select gate line. This second connecting wiring line at least comprises: a first portion extending in the third direction; and a second portion extending from the first portion to a layer below the first connecting wiring line.Type: GrantFiled: August 31, 2015Date of Patent: January 10, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Toshiharu Tanaka
