Abstract: A first and second patterned circuit layer are formed on a first surface and a second surface of a base material. A first adhesive layer is formed on the first patterned circuit layer. A portion of the first surface is exposed by the first patterned circuit layer. The metal reflection layer covers the first insulation layer and a reflectance thereof is greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer, and the first adhesive layer is disposed between the first patterned circuit layer and the first insulation layer. A transparent adhesive layer and a protection layer are formed on the metal reflection layer. The transparent adhesive layer is disposed between the metal reflection layer and the protection layer. The protection layer comprises a transparent polymer. The light transmittance is greater than or equal to 80%.

Abstract: The present invention is directed to provide a semiconductor module capable of achieving miniaturization and reduced manufacturing cost while suppressing surge voltage generated when switching the semiconductor elements. A semiconductor module includes a negative terminal and a positive terminal. The negative terminal has a negative fastening portion for fastening a negative polarity-side external terminal, a negative connection portion connected to a laminated substrate, and a negative intermediate portion arranged between the negative fastening portion and the negative connection portion. The positive terminal has a positive fastening portion for fastening a positive polarity-side external terminal, positive connection portions connected to the laminated substrate, and a positive intermediate portion facing the negative intermediate portion with a predetermined gap and arranged between the positive fastening portion and the positive connection portions.

Abstract: A neurostimulation system is disclosed herein. The neurostimulation system includes an implantable pulse generator and an implantable therapy lead configured to be electrically coupled to the implantable pulse generator. The implantable therapy lead includes a flexible paddle electrode array with flexible electrodes. Each flexible electrode has a segmented configuration having first and second electrode segments and a flexible bridge or living hinge joining together the first and second electrode segments.

Abstract: The output voltage of an MRAM is increased by means of an Fe(001)/MgO(001)/Fe(001) MTJ device, which is formed by microfabrication of a sample prepared as follows: A single-crystalline MgO (001) substrate is prepared. An epitaxial Fe(001) lower electrode (a first electrode) is grown on a MgO(001) seed layer at room temperature, followed by annealing under ultrahigh vacuum. A MgO(001) barrier layer is epitaxially formed on the Fe(001) lower electrode (the first electrode) at room temperature, using a MgO electron-beam evaporation. A Fe(001) upper electrode (a second electrode) is then formed on the MgO(001) barrier layer at room temperature. This is successively followed by the deposition of a Co layer on the Fe(001) upper electrode (the second electrode). The Co layer is provided so as to increase the coercive force of the upper electrode in order to realize an antiparallel magnetization alignment.

Abstract: The present disclosure discusses a method of manufacturing an implantable neural electrode. The method includes cutting a metal layer to form a plurality of electrode sites, contact pads and metal traces connecting the electrode sites to the contact pads. A first silicone layer including a mesh is formed and coupled to the metal layer. A second silicone layer is formed and laminated to the first silicone layer coupled with the metal layer. Holes are formed in the first or second silicone layer exposing the contact pads and electrode sites. Wires are welded to the exposed contact pads and a third layer of silicone is overmolded over the contact pads and wires.

Abstract: The invention relates to a method for producing a semiconductor component comprising a radiation-emitting optical semiconductor chip or a plurality of radiation-emitting optical semiconductor chips, said method comprising: applying the radiation-emitting optical semiconductor chip or the plurality of radiation-emitting optical semiconductor chips to a deformable flat support deforming the support; and permanently fixing the deformation.

Abstract: In a circuit module, lead frames include top surfaces facing a main surface of a substrate and bottom surfaces exposed from an insulating seal. The lead frames include pad portions including portions of the top surfaces and connected to metal posts, and lead portions including the bottom surfaces. The pad portions completely overlap the metal posts.

Abstract: A semiconductor device package includes a multilayer substrate including atop layer, a bottom layer and an intermediate layer between the top layer and the bottom layer. The package also includes one or more semiconductor dies embedded in the intermediate layer and conductive connector means to provide a conductive connection from the one or more dies. The conductive connector means extend through the top layer to provide connection means for one or more devices mounted on or adjacent the top layer.

Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

Abstract: The main technical problem solved by the present disclosure is to provide a circuit board preparation method. The method includes: obtaining a to-be-processed plate comprising an insulating layer, a first copper layer, a second copper layer opposite to the first copper layer, a blind metalized hole, and a first tab facing the blind metalized hole; obtaining a white insulating material; laminating the white insulating material to a surface of the insulating layer, a surface of the first copper layer, a surface of the first tab, and a surface of the second copper layer to form a first white insulating medium layer and a second white insulating medium layer opposite to the first while insulating medium layer; and performing surface polishing for the first white insulating medium layer and grinding the first white insulating medium layer until the first tab is exposed to form a first white reflective layer.

Abstract: The present application provides a display panel and a manufacturing method thereof. The display panel includes an array substrate, a light emitting layer, and a water and oxygen adsorption layer. The light emitting layer is disposed on the array substrate. The light emitting layer includes a pixel definition structure and a plurality of light emitting parts, the pixel definition structure includes a plurality of grooves, and the light emitting parts are disposed in the grooves. The water and oxygen adsorption layer includes a plurality of water and oxygen adsorption parts, the water and oxygen adsorption parts are disposed on the pixel definition structure, and a surface of the water and oxygen adsorption parts is convex.

Abstract: Radio frequency (RF) packages containing substrates having coefficient of thermal expansion (CTE) matched mount pads are disclosed, as are methods for fabricating RF packages and substrates. In embodiments, the RF package contains a high thermal performance substrate including a metallic base structure, which has a frontside facing a first RF power die and a first die attach region on the frontside of the base structure. A first CTE matched mount pad is bonded to the metallic base structure and covers the first die attach region. The first CTE mount pad has a CTE greater than the CTE of RF power die and less than the CTE of the metallic base structure. An electrically-conductive bonding material attaches the RF power die to the first CTE matched mount pad, while RF circuitry integrated into first RF power die is electrically coupled to the metallic base structure through the mount pad.

Abstract: A power semiconductor module, which is a semiconductor device, includes a semiconductor element 155 and a lead frame 318 that is disposed to face the semiconductor element 155 and connected to the semiconductor element 155 by a solder material 162. The lead frame 318 has the top surface 331 including a surface facing the semiconductor element 155, and the side surface 334 connected to the peripheral edge portion 333 of the top surface 331 at a predetermined angle with respect to the top surface 331. The top surface of the lead frame 318 includes the solder surface 332 that is in contact with the solder material 162 and the solder resistance surface on which the solder material 162 is less wettable than on the solder surface 332. The solder resistance surface is formed to surround the periphery of the solder surface 332. In this manner, when the semiconductor element and the lead frame are solder-joined in the semiconductor device, the region where the solder wet-spreads is appropriately controlled.

Abstract: An electronic assembly includes a first printed wiring board (PWB) on a first side of the electronic assembly, and a first stiffener secured to the first PWB. The electronic assembly also includes a second PWB on a second side of the electronic assembly, opposite the first side, a second stiffener secured to the second PWB, and a center stiffener seated in the second stiffener and between the first stiffener and the second stiffener. The center stiffener has a first side facing the first stiffener, a second side that is opposite the first side and facing the second stiffener, a first end, and a second end, opposite the first end. Electronic devices are secured to the center stiffener. The center stiffener dissipates heat from the electronic devices, and the electronic devices include power dies.

Abstract: A semiconductor device includes: a carrier including an electronic circuit; a plurality of semiconductor chip packages mounted on the carrier, each of the chip packages including an encapsulation encapsulating the semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip with the electronic circuit, and at least one cooling structure protruding from the encapsulation; and a cooling element thermally conductively connected to at least one cooling structure of each of at least two of the plurality of semiconductor chip packages.

Abstract: A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a pad at a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to the pad; and a molding compound encapsulating the semiconductor die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.

Abstract: An external terminal electrode is attached to a frame, and the frame contains a first resin, and has a first adhered surface. A heat sink plate supports the frame, has an unmounted region where a power semiconductor element is to be mounted within the frame in plan view, is made of metal, and has a second adhered surface. An adhesive layer contains a second resin different from the first resin, and adheres the first adhered surface of the frame and the second adhered surface of the heat sink plate to each other. One of the first and second adhered surfaces includes a flat portion and a protruding portion. The protruding portion protrudes from the flat portion and opposes the other one of the first adhered surface and the second adhered surface with the adhesive layer therebetween.

Abstract: A method of forming a semiconductor device includes providing a substrate that comprises a metal region, forming an encapsulant body of electrically insulating material on an upper surface of the metal region, forming an opening in the encapsulant body, and inserting a press-fit connector into the opening, wherein after inserting the press-fit connector into the opening, the press-fit connector is securely retained to the substrate and an interfacing end of the press-fit connector is electrically accessible.

Abstract: A power device for surface mounting has a leadframe including a die-attach support and at least one first lead and one second lead. A die, of semiconductor material, is bonded to the die-attach support, and a package, of insulating material and parallelepipedal shape, surrounds the die and at least in part the die-attach support and has a package height. The first and second leads have outer portions extending outside the package, from two opposite lateral surfaces of the package. The outer portions of the leads have lead heights greater than the package height, extend throughout the height of the package, and have respective portions projecting from the first base.

Abstract: Certain aspects of the present disclosure provide a capacitor assembly, a stacked capacitor assembly, an integrated circuit (IC) assembly comprising such a stacked capacitor assembly, and methods for fabricating the same. One exemplary capacitor assembly generally includes a first array of trench capacitors and a second array of trench capacitors. The second array of trench capacitors may be disposed adjacent to and electrically coupled to the first array of trench capacitors. Additionally, the second array of trench capacitors may be inverted with respect to the first array of trench capacitors.