Patents Examined by Alonzo Chambliss
  • Patent number: 11367687
    Abstract: A method for forming a silicon photonics interposer having through-silicon vias (TSVs). The method includes forming vias in a front side of a silicon substrate and defining primary structures for forming optical devices in the front side. Additionally, the method includes bonding a first handle wafer to the front side and thinning down the silicon substrate from the back side and forming bumps at the back side to couple with a conductive material in the vias. Furthermore, the method includes bonding a second handle wafer to the back side and debonding the first handle wafer from the front side to form secondary structures based on the primary structures. Moreover, the method includes forming pads at the front side to couple with the bumps at the back side before completing final structures based on the secondary structures and debonding the second handle wafer from the back side.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: June 21, 2022
    Assignee: MARVELL ASIA PTE LTD.
    Inventors: Liang Ding, Radhakrishnan L. Nagarajan
  • Patent number: 11355452
    Abstract: A semiconductor device has a substrate and a semiconductor die disposed over the substrate. An encapsulant is deposited over the semiconductor die and substrate with a surface of the semiconductor die exposed from the encapsulant. A first shielding layer is formed over the semiconductor die. In some embodiments, the first shielding layer includes a stainless steel layer in contact with the surface of the semiconductor die and a copper layer formed over the stainless steel layer. The first shielding layer may further include a protective layer formed over the copper layer. One embodiment has a heatsink bonded to the semiconductor die through a solder layer. A second shielding layer can be formed over a side surface of the semiconductor die.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: June 7, 2022
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Dong Won Son, Byeonghoon Kim, Sung Ho Choi, Sung Jae Lim, Jong Ho Shin, SungWon Cho, ChangOh Kim, KyoungHee Park
  • Patent number: 11348851
    Abstract: An object is to provide a technology for enabling reduction in the time and cost taken to manufacture a die to be used for molding a case that surrounds semiconductor elements. A semiconductor device includes a base plate, a cooling plate, an insulating substrate, a semiconductor element, a case, a lead frame formed integrally with the case and including a terminal formed on one end portion of the lead frame and protruding outward, and a sealant. The case includes a pair of first case components arranged to face each other, and a pair of second case components arranged to face each other and crossing the pair of first case components. Joining end portions of the first case components to end portions of the pair of second case components forms the case.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: May 31, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yasutaka Shimizu
  • Patent number: 11349053
    Abstract: Embodiments relate to the design of an electronic device capable having flexible interconnects that connect together a first body and a second body of the electronic device. The flexible interconnects allow the electrical device to better withstand thermal-mechanical stress during fabrication of the electronic device and user usage of the electronic device.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: May 31, 2022
    Assignee: Facebook Technologies, LLC
    Inventors: Zheng Sung Chio, Daniel Brodoceanu, Ali Seng├╝l, Oscar Torrents Abad, Jeb Wu, Pooya Saketi, Chao Kai Tung, Tennyson Nguty, Allan Pourchet
  • Patent number: 11348862
    Abstract: Provided is a semiconductor device including: a semiconductor chip having a rectangular region including a first corner portion having a first notch portion, a second corner portion being provided to diagonally face the first corner portion, a third corner portion, and a fourth corner portion being provided to diagonally face the third corner portion on a surface and having a semiconductor element formed in the rectangular region; a first electrode including a fifth corner portion being provided on the first corner portion and having a second notch portion, a sixth corner portion being provided on the second corner portion, a seventh corner portion being provided on the third corner portion, and an eighth corner portion being provided on the fourth corner portion, the first electrode being provided on the semiconductor element, and the first electrode being electrically connected to the semiconductor element; and a first connector including a ninth corner portion being provided on the fifth corner portion and
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: May 31, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Seiichi Kamiyama
  • Patent number: 11342269
    Abstract: A package structure includes an insulating encapsulation, at least one semiconductor die, a redistribution circuit structure, and first reinforcement structures. The at least one semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure is located on the insulating encapsulation and electrically connected to the at least one semiconductor die. The first reinforcement structures are embedded in the redistribution circuit structure. A shape of the package structure includes a polygonal shape on a vertical projection along a stacking direction of the insulating encapsulation and the redistribution circuit structure, and the first reinforcement structures are located on and extended along diagonal lines of the package structure.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu
  • Patent number: 11342278
    Abstract: A semiconductor device has a substrate and a semiconductor die disposed over the substrate. An encapsulant is deposited over the semiconductor die and substrate with a surface of the semiconductor die exposed from the encapsulant. A first shielding layer is formed over the semiconductor die. In some embodiments, the first shielding layer includes a stainless steel layer in contact with the surface of the semiconductor die and a copper layer formed over the stainless steel layer. The first shielding layer may further include a protective layer formed over the copper layer. One embodiment has a heatsink bonded to the semiconductor die through a solder layer. A second shielding layer can be formed over a side surface of the semiconductor die.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: May 24, 2022
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: SungWon Cho, ChangOh Kim, Il Kwon Shim, InSang Yoon, KyoungHee Park
  • Patent number: 11335624
    Abstract: A liquid discharge apparatus includes a print head discharging a liquid and a control circuit controlling an operation of the print head. the print head includes a connector having a first terminal, a second terminal, a third terminal, and a fourth terminal, a first integrated circuit, a circuit substrate on which the connector and the first integrated circuit are provided and which has first wiring, second wiring, third wiring, fourth wiring, fifth wiring, and sixth wiring, and a first wiring substrate, in which the first wiring electrically couples the first terminal and the first integrated circuit to each other, the fifth wiring electrically couples the first terminal and the first integrated circuit to each other, and the sixth wiring electrically couples the first integrated circuit and the first wiring substrate to each other.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: May 17, 2022
    Assignee: Seiko Epson Corporation
    Inventor: Yusuke Matsumoto
  • Patent number: 11322445
    Abstract: Embedded Multi-die Interconnect Bridge (EMIB) technology provides a bridge die, where the EMIB includes multiple signal and power routing layers. The EMIB eliminates the need for TSVs required by the SIP assembly silicon interposers. In an embodiment, the EMIB includes at least one copper pad. The copper pad may be configured to protect the EMIB during wafer thinning. The copper pad may be connected to another copper pad to provide signal routing, thereby increasing the signal contact density. The copper pad may be configured to provide an increased power delivery to one or more connected dies.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: Yidnekachew S. Mekonnen, Dae-Woo Kim, Kemal Aygun, Sujit Sharan
  • Patent number: 11322459
    Abstract: A semiconductor device includes a lead, a first semiconductor element, and a sealing resin that covers at least a portion of each of the lead and the first semiconductor element. The lead has an obverse surface on which the first semiconductor element is mounted, and a reverse surface opposite to the obverse surface. The lead includes a first portion having a first surface. The first surface is located between the obverse surface and the reverse surface in the z direction in which the obverse surface and the reverse surface are separated from each other. The first surface of the lead is covered with the sealing resin, and is configured with a plurality of protruding areas and a plurality of recessed areas arranged alternately as viewed in the z direction.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: May 3, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Ryuichi Furutani
  • Patent number: 11315897
    Abstract: A semiconductor package includes: a semiconductor element; a substrate provided with the semiconductor element on a first surface of the substrate, the substrate including a first wiring partially exposed on a second surface of the substrate opposite to the first surface; a first structure formed of an insulating film, or an insulating film and a metal portion, the first structure surrounding an exposed portion of the first wiring, the first structure having asymmetric height and angle; and a first electrode provided on the exposed portion of the first wiring.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: April 26, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Satoru Takaku
  • Patent number: 11309230
    Abstract: In one or more embodiments of the present disclosure, a power electronic module may be described. The power electronic module may comprise a power semiconductor device, a substrate coupled to the power semiconductor device, and a base plate coupled to the substrate. The substrate may include from 50 weight percent (wt. %) to 99.9 wt. % of a poly(dicyclopentadiene) polymer. In one or more other embodiments of the present disclosure, a method for manufacturing a power electronic module may be described. The method may include disposing a solution on a base plate. The solution may include dicyclopentadiene monomer, a ruthenium-based catalyst, and a trialkyl phosphite initiator. The method may further include initiating a polymerization front within the solution to produce a substrate formed directly on the base plate. Furthermore, the method may include coupling a power semiconductor device on the substrate to produce the power electronic module.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: April 19, 2022
    Assignee: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC.
    Inventor: Shailesh N. Joshi
  • Patent number: 11309529
    Abstract: A method of making an OLED device includes providing a first undercut lift-off structure over the device substrate having a first array of bottom electrodes. Next, one or more first organic EL medium layers including at least a first light-emitting layer are deposited over the first undercut lift-off structure and over the first array of bottom electrodes. The first undercut lift-off structure and overlying first organic EL medium layer(s) are removed by treatment with a first lift-off agent comprising a fluorinated solvent to form a first intermediate structure. The process is repeated using a second undercut lift-off structure to deposit one or more second organic EL medium layers over a second array of bottom electrodes. After removal of the second undercut lift-off structure, a common top electrode is provided in electrical contact with the first and second organic EL medium layers.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: April 19, 2022
    Assignee: Orthogonal, Inc.
    Inventors: John Andrew DeFranco, Terrence Robert O'Toole, Frank Xavier Byrne, Diane Carol Freeman
  • Patent number: 11302655
    Abstract: A semiconductor device includes a semiconductor element having an electrode, material of which is first metal, a lead frame through which a plurality of holes extend with an outer contour of the electrode being avoided in a first portion, and having the first portion, material of which is second metal, a bonding layer interposed between the first portion and the electrode, and solder being inside the plurality of holes and adjoining the bonding layer, the solder being thicker than the bonding layer. The plurality of holes have a plurality of first holes extending through the first portion in a thickness direction of the first portion. The bonding layer has a first bonding layer located on the electrode side and being an alloy of the first metal and tin, and a second bonding layer located on the first portion side and being an alloy of the second metal and tin. The plurality of first holes are located in an annular region inside the outer contour of the electrode.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 12, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Nobuyoshi Kimoto, Mitsunori Aiko, Takaaki Shirasawa
  • Patent number: 11296034
    Abstract: A substrate, a semiconductor package, and a method of manufacturing the same are provided. The substrate includes an interposer element. The interposer element has a first surface and a second surface opposite to the first surface. At least two rows of pads are disposed adjacent to the first surface of the interposer element. The interposer element includes at least one slot disposed between the two rows of pads and extending from the first surface to the second surface, wherein a projection area extending from an edge of the slot to an edge of the first surface of the interpose element is nonoverlapping at least one pad.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: April 5, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Hao Chang, Yi Chen
  • Patent number: 11289397
    Abstract: A semiconductor package according to an embodiment of the present invention includes: a heat sink board including an insulated board and a first metal layer formed on the insulated board; at least one semiconductor chip placed on the first metal layer; a plurality of lead frames connected to the semiconductor chips used to electrically connect the semiconductor chips to the outside; and a package housing partially covering the heat sink board, wherein both end parts of the insulated board are projected further than both end parts of the first metal layer.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: March 29, 2022
    Assignee: JMJ Korea Co., Ltd.
    Inventors: Yun Hwa Choi, Young Hun Kim, Jeonghun Cho, So Young Choi
  • Patent number: 11289396
    Abstract: A semiconductor package includes a semiconductor die including a sensing component, an encapsulant extending along sidewalls of the semiconductor die, a through insulator via (TIV) and a dummy TIV penetrating through the encapsulant and disposed aside the semiconductor die, a patterned dielectric layer disposed on the encapsulant and exposing the sensing component of the semiconductor die, a conductive pattern disposed on the patterned dielectric layer and extending to be in contact with the TIV and the semiconductor die, and a first dummy conductive pattern disposed on the patterned dielectric layer and connected to the dummy TIV through an alignment opening of the first patterned dielectric layer. The semiconductor die is in a hollow region of the encapsulant, and a top width of the hollow region is greater than a width of the semiconductor die.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Chu, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Tian Hu
  • Patent number: 11289520
    Abstract: There are provided a light detection device and a photoelectric conversion system including the light detection device including an avalanche diode including a first semiconductor region of a first conductivity type disposed at a first depth, a second semiconductor region of a second conductivity type disposed at a second depth deeper than the first depth with respect to the first surface, a third semiconductor region that is disposed at a third depth deeper than the second depth with respect to the first surface and is in contact with the second semiconductor region, and first and second separation regions each extending from the first depth to the third depth. The second semiconductor region and the third semiconductor region each extend from the first separation region to the second separation region. The first semiconductor region, the second semiconductor region, and the third semiconductor region have portions overlapping one another in planar view.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: March 29, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Junji Iwata
  • Patent number: 11282778
    Abstract: A semiconductor device package includes a redistribution structure, a conductive substrate stacked on the redistribution structure and an encapsulant encapsulating the redistribution structure and the conductive substrate. The encapsulant encapsulates a side surface of the conductive substrate. A method for manufacturing an electronic device package includes: providing a carrier, forming a redistribution structure on the carrier, mounting a conductive substrate on a first surface of the redistribution structure, forming a first encapsulant to encapsulate the first surface of the redistribution structure and a side surface of the conductive substrate, and removing the carrier.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: March 22, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Hsu-Nan Fang
  • Patent number: 11282775
    Abstract: A chip package assembly having pillars extending between an interconnect layer and solder balls, and methods for manufacturing the same are provide. The pillars decouple stress from the interconnect layer, making crack initiation and propagation to the interconnect layer less likely, resulting in a more robust assembly. In one example, a chip package assembly is provided that includes an integrated circuit (IC) die, an interconnect layer and a plurality of pillars. The IC dies includes a die body containing functional circuitry. The body has a lower surface, an upper surface and sides. The IC die includes contact pads coupled to the functional circuitry and exposed on the lower surface of the die body. The interconnect layer is formed on the lower surface of the body. The plurality of pillars are formed on the interconnect layer and electrically couple to the contact pads through routing formed through the interconnect layer.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: March 22, 2022
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Suresh Ramalingam