Abstract: Bonding and isolation techniques for stacked device structures are disclosed herein. An exemplary method includes forming a first insulation layer on a first device component, forming a second insulation layer on a second device component, and bonding the first insulation layer and the second insulation layer. The bonding provides a stacked structure that includes the first device component over the second device component, and an isolation structure (formed by the first insulation layer bonded to the second insulation layer) therebetween. The isolation structure includes a first portion having a first composition and a second portion having a second composition different than the first composition. The method further includes processing the stacked structure to form a first device disposed over a second device, where the isolation structure separates the first device and the second device. The first insulation layer and the second insulation layer may include the same or different materials.

Abstract: A power semiconductor device includes: a package and a plurality of power semiconductor chips, each power semiconductor chip including a semiconductor body, a first load terminal, a second load terminal and a control terminal. The device also includes a plurality of outside terminals. The outside terminals include: one or more first outside terminals electrically connected with the first load terminals; one or more second outside terminals each of which is electrically connected with each of the second load terminals; and a plurality of third outside terminals. Each control terminal is electrically connected with at least one individual third outside terminal of the plurality of third outside terminals.

Abstract: The present invention relates to the field of screen display technology, and discloses an automotive organic light-emitting diode (OLED) display screen, including a foldable OLED panel. The foldable OLED panel is of a rectangular structure and includes a display panel end and a folding region. The folding region is folded outwards to form a folded panel end. The foldable OLED panel is provided with at least one folded panel end. A back of the display panel end is bonded and fixed to the folded panel end. A circular polarizer is attached to a surface of the display panel end via an optical adhesive. A protective cover plate is attached to a surface of the circular polarizer via an optical adhesive.

Abstract: A semiconductor device is provided that includes a lead frame, a die attached to the lead frame using a first solder, a clip attached to the die using a second solder, and a copper slug attached to the clip. First gull wing leads are attached to the leadframe for a drain connection of the semiconductor device. Second gull wing leads are attached to the clip for a gate connection and for a source connection of the semiconductor device.

Abstract: A semiconductor circuit structure includes a semiconductor substrate with an original semiconductor surface, an active region within the semiconductor substrate, and a transistor formed based on the active region. The transistor includes a gate structure, a first spacer neighboring to a first sidewall of the gate structure, and a second spacer neighboring to a second sidewall of the gate structure. Wherein a thermal conductivity of the first spacer or the second spacer includes is higher than the thermal conductivity of silicon nitride (Si3N4).

Abstract: A laminate including a member that serves as a light-transmissive electrode layer and a zinc oxide layer that serves as an electron transport layer for an organic thin-film solar cell is provided. The zinc oxide layer has a Zn deposition amount of not less than 20.0 mg/m2 and not more than 120.0 mg/m2. An S value represented by Formula (1) is not more than 0.90 when, in the zinc oxide layer, an oxygen 1s spectrum obtained by X-ray photoelectron spectroscopy is separated into three peaks, an area of a peak in which a binding energy of a peak top is in a range of not less than 529.0 eV and less than 530.7 eV is represented by ?, and an area of a peak in which a binding energy of a peak top is in a range of not less than 530.7 eV and less than 532.2 eV is represented as ?: S = ? / ( ? + ? ) .

Abstract: A display device according to the present invention is characterized by comprising: a base part; assembly electrodes extending in one direction and formed on the base part; a dielectric layer formed so as to cover the assembly electrodes; a barrier rib part stacked on the dielectric layer while forming holes so as to overlap the assembly electrodes; semiconductor light-emitting elements disposed inside the holes; and wiring electrodes electrically connected to the semiconductor light-emitting elements, wherein the assembly electrodes are formed so as to include Al, and the holes include AlOx.

Abstract: Provided is a semiconductor device reducing local increase in temperature caused by a void in a bonding material. A semiconductor device includes a conductive member, a semiconductor element, a bonding part, and a lead. The semiconductor element includes a switching element. The semiconductor element is held by the conductive member via a first bonding material. The bonding part is provided on an upper surface of the semiconductor element. The bonding part is electrically connected to an electrode of the switching element other than a gate electrode. The lead is bonded to the bonding part via a second bonding material. The bonding part and the second bonding material are provided in a region including a center part of the upper surface of the semiconductor element.

Abstract: Examples of devices for providing cooling solutions are described. One example device at least one printed circuit board (PCB) and at least one baffle cover positioned along an edge of the at least one PCB. The at least one PCB is immersed in a cooling fluid in a tank. The at least one PCB includes one or more integrated circuit (IC) chips with a thermal interface material (TIM) applied to surfaces of the one or more IC chips that are coupled to a boilerplate. The baffle cover includes one or more openings that are configured to control an agitation of the cooling fluid proximate to the edge of the at least one PCB.

Abstract: A semiconductor device includes a first electrode, a ferroelectric layer disposed on the first electrode and implementing a negative capacitance, a dielectric structure disposed on the ferroelectric layer and including a first dielectric layer and a second dielectric layer that are alternately stacked, and a second electrode disposed on the dielectric structure. The ferroelectric layer and the dielectric structure are configured to be electrically connected in series to each other. The ferroelectric layer and dielectric structure together have a non-ferroelectric property.

Abstract: An example thin-film transistor includes a substrate, a source including a body of source material on the substrate, a drain including a body of drain material on the substrate, a body of channel material between the source and the drain, a body of gate dielectric material on the body of channel material, and a body of gate material on the body of gate dielectric material. The source material includes a metal nitride.

Abstract: A display panel includes a driving circuit layer, light emitting components and encapsulation structures. The light emitting components are disposed on the driving circuit layer, and each includes a first electrode, a light emitting pattern disposed on the first electrode, a second electrode disposed on the light emitting pattern and a pixel definition layer disposed on the driving circuit layer. The pixel definition layer has a pixel opening overlapping with the first electrode. The light emitting pattern and the second electrode cover the pixel definition layer, the first electrode located in the pixel opening and a portion of the driving circuit layer located outside the pixel opening. The encapsulation structures respectively cover the light emitting components, and each encapsulation structure includes a first encapsulation pattern. Edges of the first encapsulation pattern, the light emitting pattern and the second electrode overlapping with each other are aligned with each other.

Abstract: An electronic package and a manufacturing method thereof are provided, in which a full-panel wafer is provided and includes a plurality of electronic bodies arranged in an array at intervals, a plurality of trenches are formed across the electronic bodies along a first direction on the full-panel wafer, so that the trenches on a single electronic body are arranged parallel to each other at interval and along a second direction perpendicular to the first direction. Then, in a singulation process, any trench can be selected for cutting to obtain a plurality of electronic elements of a required size. Finally, each of the electronic elements is disposed on a packaging region of a carrier structure, so that each of the electronic elements is electrically connected to at least a portion of electrical contact pads in the packaging region.

Abstract: A circuit board includes a plurality of first insulating base materials and a plurality of second insulating base materials that are alternately laminated, a first metal layer being formed into a pattern shape on a first surface of the first insulating base material, and a second metal layer being formed into a pattern shape on a second surface of the first insulating base material. The first metal layer is formed into a trapezoidal shape that is large in diameter on a first surface side of the first insulating base material. The second metal layer is formed into a trapezoidal shape that is large in diameter on a second surface side of the first insulating base material. The first metal layers and the second metal layers are laminated in such a manner that the trapezoidal shapes are alternately oriented.

Abstract: A package device is provided. The package device includes a substrate, a plurality of upper lands disposed on one surface of the substrate, a plurality of upper solder balls disposed on the plurality of upper lands, a die connected to the plurality of upper solder balls, a plurality of lower lands disposed on the other surface of the substrate, a plurality of lower solder balls disposed on some of the plurality of lower lands, and a capacitor connected to the lower lands on which the plurality of lower solder balls are not disposed among the plurality of lower lands, provided on an opposite side of the die, and including a height greater than the height of the plurality of lower solder balls.

Abstract: A semiconductor chip includes: a photonic integrated circuit (PIC) comprising an active component electrically connected to a first landing pad at a surface of the PIC, wherein the first landing pad is configured to receive a copper pillar, which, when installed, provides at least a portion of a first electrical interconnect between the active photonic component and a second integrated circuit to be stacked on the surface of the PIC, and wherein, when viewed from above the PIC towards the PIC, a center of the active photonic component on the PIC is offset from a nearest edge of the first landing pad by about a distance less than 10 ?m.

Abstract: A wire protecting part partially encloses a first lead frame and a second lead frame and has an enclosing surface from which the first and second lead frames protrude. The enclosing surface is parallel to semiconductor chips, and includes a water stop part protruding, from the enclosing surface, between the first and second lead frames.

Abstract: Micro-LED structures include an LED epilayer that may be formed before the micro-LED structure is coupled to a backplane substrate. In order to prevent light leakage and maximize light output, the sidewalls and other surfaces of the LED epilayer may be coated with a reflective coating. For example, the reflective coating may include a metal layer that is electrically insulated between dielectric layers from the micro-LED electrodes. The reflective coating may also be formed using multiple layers in a distributed Bragg reflector configuration. This reflective coating may be formed during the LED fabrication process before the micro-LED structure is coupled to the backplane. The pixel isolation structures on the backplane may also include a reflective coating that is applied above the LED epilayers.

Abstract: A display screen includes a backplane, an array of light-emitting diodes electrically integrated with the backplane, the array of light-emitting diodes configured to emit UV light in a first wavelength range, and a plurality of isolation walls formed on the backplane between adjacent light-emitting diodes of the array of light-emitting diodes with the isolation walls spaced apart from the light-emitting diodes and extending above the light-emitting diodes. The plurality of isolation walls include a core of a first material and a coating covering at least a portion of the core extending above the light-emitting diodes. The coating is an opaque second material having transmittance less than 1% of light in the first wavelength range.

Abstract: An integrated circuit (IC) package comprising a die having a front side and a back side. A solder thermal interface material (STIM) comprising a first metal is over the backside. The TIM has a thermal conductivity of not less than 40 W/mK; and a die backside material (DBM) comprising a second metal over the STIM, wherein the DBM has a CTE of not less than 18×10?6 m/mK, wherein an interface between the STIM and the DBM comprises at least one intermetallic compound (IMC) of the first metal and the second metal.