Abstract: A computer for simultaneously executing plural instructions decides the kind of operation and the possibility of simultaneous execution for the plural instructions as the instructions are read out from a main memory to a cache memory. The plural instructions and a corresponding decision result are stored in the cache memory. The decision process is performed for several groups of the plural instructions read out from the main memory to the cache memory in order. Then, the plural instructions are respectively assigned to a corresponding operation unit according to the decision result, and are subsequently executed by the corresponding operation unit. As a result of this arrangement, the repeated decision process for the plural instructions is not necessary when they are later read out from the cache memory to the operation unit.

Abstract: A small electronic apparatus such as an electronic organizer, electronic memo, etc. is disclosed which has a memory for storing data, and a communication unit for transmitting data stored in the memory to another electronic apparatus, and for receiving data from the other electronic apparatus. The apparatus selects, before transmitting at least one portion of said data, either of an add mode (transmitted data is added to data stored in the other electronic apparatus) and a update mode (data stored in the other electronic apparatus is replaced with the transmitted data). The apparatus has a signal unit for, when the add mode is selected, transmitting a first signal indicative that the add mode is selected to the other electronic apparatus, and for, when the update mode is selected, transmitting a second signal indicative that the update mode is selected to the other electronic apparatus. The apparatus displays data which has been transmitted when a data transmission error has occurred.

Abstract: A pulse generator includes an event counter receiving an external clock for counting the external clock, a first compare register coupled to the event counter for generating a first equal signal when a count value of the event counter becomes equal to a value set in the first compare register. The first equal signal is supplied to the event counter so as to clear the event counter. A free-running counter receives an internal clock for counting the internal clock, and a second compare register is coupled to the free-running counter for generating a second equal signal when a count value of the free-running counter becomes equal to a value set in the second compare register.

Abstract: A data-driven type computer system including an input limiting section for monitoring a current number of packets existing in the circular pipeline of the system while being processed. The input limiting section is adapted to control packets from being inputted from the external unit when the current number of packets exceeds a specified threshold value which is greater than a minimum packet number existing in the circular pipeline and which allows the attainment of the highest possible throughput of the system. The input limiting section further includes a predictive control unit to preliminarily analyze a current data flow graph to be processed in the system and also to take order in rank a possible rate of increase in the quantity of packets generated by a copying operation as well as a possible rate of reduction in the prior processing by the system.

Abstract: A bus-to-bus interface preserves data coherence between masters and slaves operating within a multiple processor computer system. Two buses are connected via the interface. The first bus connects a number of self-identifying masters. The second bus connects a number of master devices and a number of slave devices. The second bus has no mechanism with which devices connected to the second bus may identify themselves. The interface contains a pair of registers for each slave device connected through the second bus. One register stores a busy bit if the corresponding slave is engaged on behalf of a master. The second register stores an identifying code for the master delegating a task to the corresponding slave. When a slave has accepted a task on behalf of a master and commanded the master to relinquish the bus, the busy register will be set and the master identification register will store the identifying code for the delegating master.

Abstract: A parallel processor network comprised of a plurality of nodes, each node including a processor containing a number of I/O ports, and a local memory. Each processor in the network is assigned a unique processor ID (202) such that the processor IDs of two processors connected to each other through port number n, vary only in the nth bit. Input message decoding means (200) and compare logic and message routing logic (204) create a message path through the processor in response to the decoding of an address message packet and remove the message path in response to the decoding of an end of transmission (EOT) Packet. Each address message packet includes a Forward bit used to send a message to a remote destination either within the network or to a foreign network. Each address packet includes Node Address bits that contain the processor ID of the destination node, it the destination node is in the local network.

Abstract: An apparatus for and method of aborting the remainder of a microinstruction if a branch by that microinstruction or a subsequent microinstruction renders the results of said microinstruction to be invalid. Within an instruction processor having the capability for pipelined operation, the sensitivity of an operation of a microinstruction to the branch condition may be indicated by one or more abort bits. If an abort bit is set and the corresponding branch condition occurs, the remainder of the microinstruction is aborted. By thus indicating the sensitivity to a branch, the microinstruction can proceed under full pipeline operation until such time as a branch condition actually occurs.

Abstract: A reception unit for providing data supplied from a serial input circuit to an inner bus and a transmission unit for providing the data supplied from the inner bus to a serial output circuit hold at least two sorts of control procedures among HDLC procedure, BI-SYNC procedure and start-stop synchronous procedure as control procedures for data transmission/reception, and the control procedures held by these units can be selected alternatively based on a command of the processor.

Abstract: A hybrid pipelined processor and associated processing methods are described for separately handling substantially concurrently in a time division manner multiple program instruction threads. The hybrid architecture includes an instruction fetch unit, an instruction decode unit and an execution unit. The execution unit includes multiple sets of register files each of which contains the working contents for a corresponding one of a plurality n of instruction threads. Timing and control circuitry is coupled to each of the principal processor components for controlling the timing and sequence of operations on instructions from the plurality n of instruction threads such that multiple instruction threads are separately handled substantially concurrently. Corresponding hybrid processing methods for such a single pipelined processor are also discussed.

Abstract: A computer architecture which significantly reduces latency in fetching instructions from main memory includes a code-pump located proximate to the memory and a filter cache located proximate to the processor. The code pump reduces latency in fetching instructions by predicting possible instruction streams that may be executed by the processor and passing instructions from all possible streams to the filter cache. The code pump fetches instructions from the memory and partially decodes the instructions to determine their types. Instruction types which may change the flow of the program such as subroutine calls and conditional branches, cause the code pump to concurrently supply instructions from all flow paths that can be predicted from these instructions. To keep track of the possible flow paths, the code pump maintains a data structure which is a combination of multiple stack entries (for call instructions) and tree entries (for branch instructions).

Abstract: A monolithic integrated circuit as may be used in combination with a plurality of sensors for generating respective sensor output signals, which monolithic integrated circuit includes means for converting each sensor output signal to bit-serial digital format, together with some initial processing circuitry comprising a bit-serial multiply-add processor. This processor includes a bit-serial digital multiplier for multiplying a first digital processor input signal in bit-serial form by a second digital processor input signal to generate a digital product signal, a digital adder for adding a third digital processor input signal to the digital product signal to generate a digital sum signal, and means for supplying a digital processor output signal with bits correspond-ing to those of said digital sum signal.

Abstract: A parallel processing system performs an application function by a plurality of processing unit contained within a single network. The parallel processing system includes at least one slave unit connected to a common network and capable of processing a specified amount of data at a particular processing speed. At least one master unit, which may include a local slave unit, is connected to the common network and initiates an application function to be processed by the slave units. The slave units are polled to determine the processing power of each slave unit, the resources available to each slave unit and the availability of each slave unit. One or more slave units are engaged in processing the application function. If a plurality of slave units are selected, the application function is divided into a plurality of portions of data and each portion is assigned and communicated to a specific slave unit for processing. Predetermined calculations are performed on each portion of data by each slave unit.

Abstract: A process of programming a programmable logic device (PLD) to carry out a specified logic function. The PLD contains three levels of logic implemented as a plurality of functional blocks, each with AND and OR planes, and a programmable interconnect matrix or logic expander carrying out AND logic. After providing such a PLD with specified size constraints and after specifying a logic function, the function is split or factored into subfunctions or factors. A Boolean factorization procedure chooses factors by replacing pairs of product terms in the first factor with their supercube and minimizing the number input terms and product terms required. Subfunctions or factors which are too large can be simplified by combining pairs of inputs in the interconnect matrix. The product terms of a subfunction or factor can be ordered according to the number of input terms they have and assigned to the functional blocks one at a time.

Abstract: In a dataflow processor, double precision data segments of higher and lower significant bits and like segments of single precision data are read out of a memory and appended with a tag to form packets. The packets are forwarded to a ring bus to which computing modules are connected. Each module includes an interface which forwards the packet onto the bus if another module is the destination. If the packet is destined to the own module, the packet is split into a tag and a data segment. If the tag indicates that the data segment is double precision data, it is assembled with the companion segment of a previous packet into a double precision data word. Otherwise, it is translated to a single precision data word of the same bit width as the double precision data word. A data set is formed by successive double precision data words or by successive single precision data words.

Abstract: The present invention relates to a floating console control system of computer system. This computer system includes a main storage unit storing the operating system, a central processing unit for reading instructions of a program stored in the main storage unit and excuting programmed processing and calculations and a service processor connected to the main storage unit and central processing unit to load the program to the main storage unit. The service processor is connected to a plurality of terminals which are able to perform as both a service processor terminal and a work station terminal. The purality of terminals are assigned numbers and stored, in such a manner that the operating system is loaded to the main storage unit, when the plurality of terminal issues connection request to the service process.

Abstract: A digital signal processing apparatus according to the present invention includes two or more address registers associated with at least one of an instruction memory, a data memory, or a coefficient memory and two or more data registers associated with a computing block, and these two or more registers are duty cycled switched between different jobs being simultaneously processed by the computing block to enable efficient processing on a single chip of jobs that can be processed with different processing speeds, such as jobs suited for high speed processing or low speed processing.

Abstract: The present invention is bus to bus interface for connecting a first bus to a second bus. A control means includes first and second control sequence means, substantially similar, for tracking and controlling the channels of data within a first and a second FIFO device. The first sequence control means includes first circular queue means for providing a predetermined number of slots, with each slot containing information regarding a channel of data already resident in first FIFO device, including the identity of the channel and the status of the channel, and containing information regarding a channel of data pending residence in first FIFO device, including the identity of the pending channel.

Abstract: A disk unit control apparatus (DKC) comprises a cache memory provided between a CPU and an external memory (DKU) storing the information exchanged with the CPU, the cache memory holding temporarily copies of the information stored in the DKU. A request from the CPU for access to the information stored in the DKU is met as far as possible by use of the information held in the cache memory. First transfer routes of information between the CPU and the cache memory is greater in number than second transfer routes of information between the cache memory and the DKU. This makes it possible that even when direct accesses to the DKU in the same number as the second transfer routes occur in each of the first transfer route, accesses to the cache memory which may arise from other CPUs are capable of being effected through the remaining ones of the first transfer routes.

Abstract: The invention relates to an inexpensive telecommunications device utilizing existent components located in the home or office, such as a television receiver and a telephone, for creating an interactive display terminal for accessing information stored in remote computer databases. In one embodiment according to the invention, the terminal is configured with the necessary logic components to communicate with a host computer system via telephone lines. Alternatively, the device may be directly connected to an inhouse data retrieval network. The terminal is software controlled at the host database and can be dedicated to a particular host computer database system, or may be utilized with various host systems. A multiple screen memory, which is programmable at the host database, may be utilized for storing multiple television screens of information. Peripheral components, such as a printer or disk drive, may be attached to the terminal.

Abstract: A processor specially adapted for use as a coprocessor. The processor is implemented as a microprocessor. The adaptations include the following: The microprocessor has a master-slave pin which receives an input which determines whether the microprocessor operates as a bus master or a bus slave. Certain output pins have three-state bus drivers which employ feedback to ensure that a signal on a line being driven by the driver has gone inactive before the driver is turned off. Instructions executed by the microprocessor permit specification of portions of the internal registers as sources and destinations and specification of the size of an ALU operation, permitting easy operation on data ranging from bytes through 24-bit pointers. Instructions are executed in an instruction pipeline and a separate I/O instruction pipeline.