Abstract: The data storage subsystem is implemented using redundancy groups of data storage modules, at least one module of which comprises a plurality of data storage elements. In this manner, the one dimensional data storage module redundancy group is expanded in another dimension by the use of a plurality of storage elements to implement each of the data storage modules. Enhanced performance is obtained by having more actuators concurrently accessing data. The reconstruction of data due to an equipment failure is therefore localized to a data storage element rather than requiring the replacement of an entire data storage module.

Abstract: An accumulating multiplication circuit includes a multiplication part receiving first and second input data, each composed of "n" bits, so as to output a first 2n-bit data of a partial product of the first and second input data, and a shifter for shifting the "2n-bit" data, which is the subject of the arithmetical operation, rightward by "n" bits. An arithmetical operation part receives the first 2n-bit data and the right-shifted 2n-bit data so as to output a third 2n-bit data. Thus, a double-precision multiplication can be efficiently executed.

Abstract: A method and apparatus for processing digital video data with a first processor and a second processor, wherein the two processors run asynchronously. First and second processor offsets are associated with the first and second processors, respectively. Commands for the two processors are stored in a set queue residing in memory shared by the two processors. The first and second processor offsets are compared to determine whether only one processor or both processors may implement commands.

Abstract: A system and method for guaranteeing coherency between a write back cache and main memory in a computer system that does not have the bus level signals for a conventional write back cache memory. Cache coherency can be maintained by writing back all modified data in the cache prior to execution of the command that initiate the DMA or Bus Master transfer to or from main memory. When bus snooping logic detects writes from the CPU, the cache and main memory are synchronized. After synchronization, the bus snooper continues to look for access hits to modified data in the cache. If hits occurs and it is a DMA cycle, the CPU is prevented from further accesses to cache until after the DMA transfer, modified bytes are written back to main memory. If it is a bus master device seeking access to main memory, the CPU is prevented from further accesses to cache until the modified bytes are written back to main memory.

Abstract: The method and apparatus of the present invention permit users to associate conditions of interest, such as keywords or originator identities. In response to the sending of a message, the data processing system determines which user conditions are met by the message input into the system and may associate the identities of such users with the message. In one embodiment, the system returns to the sender of the message the identities of users whose conditions are met by the message. In another embodiment, the system routes the message to users whose conditions are met by the message and, optionally, returns a confirmation of the delivery of the message to the sender. In either embodiment, a user can designate himself as "invisible", so that the system will not report the invisible user's identity to the sender.

Abstract: A connection-oriented communication system capable of realizing the communication path re-establishment automatically, without requiring the programming of the procedures for the re-establishment of the communication path in the mutually communicating programs.

Abstract: A method for organizing and programming distributed computer systems in which processors are connected via interconnection or communication networks, such that even if many cases of hardware and software faults occur within the processors or within the networks, such faults do not lead to the failures in the application's computation. Parallel and asynchronous execution of multiple versions of a program module is performed with processors which are connected by a network without involving any direct interaction between the processors during the execution of the same or different versions of the program module.

Abstract: A system and method for real time internal bus monitoring of a data processing device is disclosed. A plurality of processors having address outputs, data lines, and clocks are connected to a synchronizing circuit to lock the clocks of the processors in phase. A memory is connected to all of the data lines in common and is connected to the address outputs of fewer than all of the processors. Emulation circuitry is connected to the address outputs of a processor instead of said memory. The method discloses synchronizing the processors by locking the clocks in phase. Then accessing the system memory by addressing it with the address output of only one of the processors. And finally, monitoring at least one of the other processors via its address output.

Abstract: A method and system for implementing a common protocol for communication of data between a first application program and a second application program. The method and system uses a high level interface specification that is created in a computer program language-independent fashion using an object oriented paradigm. The high level interface specification is used to define the common protocol, and to generate first and second protocol interfaces. Either of the generated first and second protocol interfaces is capable of performing the services of a client or server, and are inserted into the first and second application programs respectively. The first and second protocol interfaces are executed by the first and second application programs for communication of data between them using the common protocol.

Abstract: A local area network (LAN) topology monitor including segment monitor nodes which report the presence of new end nodes to a network manager node. The segment monitors send a test-node message when requested by the network manager and inform the network manager of any test-node messages originating from other segments. The network manager uses the sequence of received new-node messages and test-node messages to determine the topology of the LAN. If one segment monitor reports a new node, the new node must be connected to the same segment as the reporting monitor. If multiple segment monitors report the presence of a new node, the network manager requests each reporting segment monitor to send a test-node message. Since the segment monitors report test-node messages received from other segment monitors, if only one segment monitor responds as having received a test-node message, then that segment contains the new node. Otherwise, the new node is off-segment.

Abstract: A broadband intelligent network (50) an ATM switch or other fast-packet switch (51) in a fiber optic, fast-packet communication system. The ATM switch (51) is directly coupled (53) through one of its ports to a network service control point (61) for the implementation of requested services without the use of an intermediate common channel signaling system. ATM cells, identified as signaling cells, carry customer service requests and are automatically routed through the ATM switch to the network service control point (61). The service control point (61) determines the requested service and executes a corresponding programmed procedure (210). Connection service requested by a particular signaling cell is implemented by the service control point (61) sending a command cell through a port of the ATM switch (51) to instruct the switch connection management processor (64) to establish a switched virtual circuit for the requested connection.

Abstract: A distributed information processing system which includes a server having a resume-request processor and clients having resume-request units or processor. An user at the client site operates a resume switch to save an operation state of the client in the server's magnetic disc, and resume it from the server's magnetic disc. The operation state includes contents of the main memory, contents of the display memory, values of the I/O registers for peripheral devices, and information about the file of the server being used by the application program run by the user. The user is able to use any client of the system in the same situation including a connection state between the file and the application program as before.

Abstract: DLL devices are built with multiple MAC address instead of a single MAC address, and provide a multiple virtual DLL interfaces to the upper layers (3-7) in a computer. This results in a new class of multi-function computers for attachment to a network system which take advantage of the multiple virtual DLL interfaces, to increase performance of the respective functions executed by the computer. Thus, a new network interface control apparatus and a new class of multi-function computer systems for attachments to networks are provided. The memory in the medium access control device stores a plurality of additional network addresses in addition to the assigned network addresses. The address filtering logic includes circuits responsive to the additional network addresses, such as logic for blocking a particular frame on at least one of the plurality of data channels when the source and destination address of a particular frame are found in the additional addresses stored in the memory.

Abstract: A tiered communications service which utilizes multiple methods of communication and provides the ability for different host computer systems to pass dam, unconcerned with the type of communications medium used by the service. Each method of communication is ranked according to its preference within the service. When the communications service encounters an error while attempting to send data to another host system, it performs an automatic switch to the method with the next lower preference which is available for use. The service sends notification to the other system of the change in communications method used and which method to start using, then continues sending the data. The communications method may be switched to a higher or lower preferred method explicitly by operator command, which also sends notification to the other systems of a change in method.

Abstract: There is provided a common-memory controlling apparatus which controls data transfer between a common-memory and a plurality of central processing units. A separating buffer separates a CPU bus connected to each of the central processing units from a common-memory bus connected to the common-memory. A request signal generating circuit generates a request signal for accessing to the common-memory when each of the central processing units requires accesses to the common-memory. An arbitration circuit arbitrates the request signals supplied by the central processing units so that a request signal corresponding to one of the central processing units is selected. The central processing unit having the highest priority level is served. A control signal generating unit generates control signals used for controlling a bus connection corresponding to the selected central processing unit so that the CPU bus connected to the selected central processing unit is connected to the common-memory.

Abstract: A car built-in type one-chip microcomputer including a ROM, a RAM, and an input/output port, wherein a control program which is executed on the car built-in type one-chip microcomputer is stored in a high level language, so that formation, change and verification of a control program can be easily carried out by an ordinary programmer who has never been trained to treat an assembly language. Even if the kind of the microcomputer is changed, it is not necessary to change the control program. The program can be modified as a result of experiment. A program developed by a program developing apparatus can be used, as it is compatible with the microcomputer.

Abstract: This invention relates to the adaptation of personal computers to communication through external networks, and more particularly to the ready adaptation of such computers to networks of varying characteristics, such as telecommunications networks located in various countries of the world. The adapter has first and second controllable digital/analog convertors for exchanging signals with a digital signal processor of the computer and controllable by a bus interface controller of the computer for converting signals between digital and analog forms. The adapter also has first and second connectors of the type required by the particular external network, coupled to the convertors for exchanging signals with the external network and for exchanging signals with an external device such as a telephone set.

Abstract: A superscalar-type processor includes an instruction memory, a fetch stage fetching simultaneously a plurality of instructions from the instruction memory, functional units respectively executing predetermined functions, and a decode state decoding the fetched instructions to issue parallel-processable instructions to related functional units. The decode stage includes a decoder determining whether a branch instruction is included in the received instructions and whether a branch is generated according to the branch instruction. The decoder links a write delaying flag indicating whether the instruction is after a branch instruction and a validity flag indicating whether the instruction is valid to the instruction on issuing the instruction to a functional unit. The functional unit includes an execution stage executing an instruction and a write back stage changing a machine state according to the result of execution in the execution stage.

Abstract: The present invention is a programmable data processing system and apparatus which operates as an independent microprocessor. The programmable data processing system of the present invention stores both general purpose and special purpose graphic instructions. The programmable data processing apparatus of the present invention has both types of instructions within its instruction set. This provision of a single processing apparatus for preforming both types of instructions enables a highly flexible solution to bit map graphics problems. This is because the program of the data processing apparatus may be altered to provide the most desirable graphics algorithm without loss of the general purpose calculation and program flow capability of a general purpose data processor. The data processor of the present invention may serve as a parallel processor for a host data processing system for primarily control of bit mapped graphics.

Abstract: A subscriber terminal service system, which has a switchboard connected to a plurality of subscriber terminals and a computer connected with the switchboard and executes services to subscribers, has the functions of setting a flag indicative of the possibility/impossibility of the execution of an application on the basis of a message sent from the computer, referring to the flag in response to a service request sent from the subscriber terminal to determine whether or not the execution of the requested application should be permitted, sending a control message to the switchboard when the condition of possibility/impossibility of the execution of an application on the computer, and changing the content of the flag in the switchboard on the basis of the control message. The start or stop of any application executed in the computer is made through a console device connected with the computer or by a scheduler provided in the computer.