Abstract: A method and apparatus for generating a sequence of displacement vectors and associated minimal error values. The vectors and-associated values represent the best match of a current block of elements of a first frame of a signal with one of a plurality of search blocks of elements located within a corresponding search window of a second frame. A first stream of data, representing the elements of the first frame is transmitted to a linear array of processing units; a second stream of data, representing the elements of the second frame is transmitted to the array; a hybrid stream of data from the elements of the second stream is synthesized such that the elements of the hybrid stream are aligned in time with the elements of the first stream so as to enable each processing unit of the array to compute an error between a particular current block and a different search block of the corresponding search window. The error is a measure of the difference between two blocks of elements.

Abstract: There is provided a mechanism for propagating exception conditions in a computer system when instructions are subject to exception conditions. The apparatus includes a set of data registers for storing data manipulated by the instructions of the computer system, and a set of state registers for storing speculative states of data manipulated by the instructions, there being one state register associated with each data register. Furthermore, the apparatus includes a logic circuit, coupled to the set of state registers, for propagating the states from a source one of the state registers to a destination one of the state registers, if data stored in an associated source one of the data registers are used as a source for an associated destination one of data registers, and if data stored in the source data register were manipulated by a particular instruction subject to an exception condition.

Abstract: For obtaining a central processing unit to perform, with the same operation code, an operation in which a carry input is effective and an operation in which the carry input is invalid or an operation in which a borrow input is effective and an operation in which the borrow input is invalid, between an output of a carry and borrow flag and a carry and borrow input of an ALU there is provided a switching circuit to switch the input of the ALU by a control signal different from a control signal of the central processing unit due to an operation code.

Abstract: A data processor includes a first circuit for decoding a sequence of instruction including a conditional branch instruction in such a manner that said conditional branch instruction is decoded and an instruction fetched after said conditional branch instruction is decoded before a branch condition for said conditional branch instruction has not decided. Said first circuit generates an operand address for the decoded instruction and a first signal indicating that said operand address is one generated before a branch condition is decided. A second circuit generates, after decision of said branch condition, a second signal indicating whether or not an instruction decoded after said conditional branch instruction is executed. The bus interface circuit performs replacement of a content of an associative memory. A control circuit receives the first and second signals and operates to hold replacement of a content of the associative memory.

Abstract: Supplied with first and second signals from first and second control units (19, 29), first and second reading units (17, 27).read first and second readout ATM signals from first and second primary memory units (15, 25) which memorize an ATM signal (11). The second control unit produces the second-reading signal when a predetermined interval lapses after supplied with a first reading start signal from the first control unit. A first processing unit (21) processes the first readout ATM signal into a first STM signal and a first processed content signal. A second processing unit (31) processes, in response to the first processed content signal, the second readout ATM signal into a second STM signal. An output reading unit (35) read first and second output STM signals at the same time from first and second secondary memory units (23, 33) which memorize the first and the second readout STM signals.

Abstract: A data processor, comprises: an instruction decoding unit which includes an encoding circuit encoding bit positions of "1" or "0" of a register list field represented by a bit string consisting of "1" and "0", in binary digits representing the register number from which or to which data to be transferred is transferred, and decodes the instruction to output a control code including the decoded result of an operation code field and the register number; an instruction executing unit which accesses a memory and executes the instruction; and instruction execution control unit which controls the instruction executing unit in accordance with the control code outputted from the instruction decoding unit to load data to the register indicated by the register number from a memory area, or to store data into the memory area from the register indicated by the register number, and is capable of executing the instruction for transferring plural data between the memory and register at high efficiency, by encoding the regis

Abstract: A method and apparatus for controlling a conditional branch instruction in a pipeline type data processing apparatus which are adapted to judge whether or not a conditional branch instruction is valid, judge whether or not a condition code necessary for a taken/not-taken judgement made for the conditional branch instruction is valid, and selectively make a taken/not-taken judgement for the conditional branch instruction in accordance with the results of the judgements made to the conditional branch instruction and the condition code.

Abstract: The branch prediction using a branch prediction table formed by an associative memory which is applicable to a super scalar processor without causing confusion in the branch prediction. The branch prediction uses a branch prediction table for registering entries, each entry including a branching address, a branch target address, and an instruction position indicating a position of the predicted branch instruction in group of instructions to be executed concurrently, or an entry address indicating a position of each entry in the associative memory of the table. A correctness of the predicted branch instruction is checked by using actual branch target address and/or actual instruction position of actual branch instruction encountered in the actual execution of presently fetched instructions. When the predicted branch instruction is incorrect, instructions fetched at a next processing timing are invalidated and the entry in the table is rewritten.

Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes.

Abstract: A processor comprises an instruction register which holds a plurality of user instruction codes one by one, a state counter which outputs a number indicating the internal state,of a system which changes along with the execution of instructions, and a decoder which receives as input the contents of the instruction register and the state counter and produces various types of control signals for the system. Additionally, the processor has two further comprises a detection/storage unit which detects the occurrence of predetermined specific processing and when detecting the same stores the specific instruction code preselected from among the above-mentioned user instruction codes in the instruction register.

Abstract: The present invention relates to a macro instruction set computer (MISC) architecture having main memory for storing system softwares of the computer, instructions, and user programs; first memory for storing preparatory data for operations, intermediate results of operations and the final results of completed operations, and operating in stack form; second memory for storing the break point address of subprograms and address for recovery of the break point while returning from a call, and operating in stack form; a CPU having: address management for the main memory; main memory data port for receiving instructions and data from main memory and writing data in the CPU into main memory; control logic combinational decoding for decoding instructions from main memory and generating control signals controlling the operations of the computer; ALU for performing arithmetic and logic operation functions; top of stack, next to the top of stack and the third one to the top of stack register of the first memory; top of

Abstract: Apparatus for recovering resources in a data processing system having at least one CPC including at least one central processor for executing instructions arranged in programs for processing data, a main storage for storing data and said programs, and including a structured external facility, and multiple message paths connected between the CPC and the structured external storage facility for passing data, messages and responses therebetween. The CPC includes multiple indicators, one for each message path, and vectors which indicate the validity of data shared by the main storage with the structured external storage facility. A message path status facility determines if any of the message paths become unavailable. If any of the message paths is determined to be unavailable, its indicator is set, and a recovery of resources is started. The status of each message path is tested.

Abstract: In a multi-system complex having central processing complexes (CPCs) and subsystems, a hardware facility for prompt interdicting I/O and message operations. A CPC or subsystem failure causes as interruption in the availability of the data bases to the attached network of terminals. Often such networks have thousands of terminals. Even a short loss of data is detrimental. Therefore the CPC or subsystem takeover must be accomplished as quickly as possible and the I/O attached to the failing CPC or subsystem must be interdicting to release it for use to the rest of the complex. The disclosed hardware facility provides a mechanism which is program initiated and controlled and which guarantees the prompt completion of the interdiction function.

Abstract: Vector logic is implemented by pipelining logic stages comprised of dynamic mousetrap logic gates. A novel pipeline latch is associated with each logic stage of the pipeline. Each pipeline latch has a latch reset mechanism, an input trigger mechanism, a disabling mechanism, a flip-flop mechanism, an output gating mechanism, and a latch enable pull-up mechanism. Moreover, the logic stages are alternately clocked. While the even numbered stages are receiving a high clock signal for instigating propagation, the odd numbered stages are receiving a low clock signal for instigating precharging, and vice versa. The high and low clock times for each stage is substantially equivalent. Due to inherent manufacturing inequalities, clock asymmetry results. An advantaged and disadvantaged phase arises. Because of the novel latch and associated method, pipeline stages operating in the disadvantaged phase can steal time from those operating in the advantaged phase. Further, no minimum clock frequency is required.

Abstract: A signal processor architecture that comprises a data network having multiple ports, a control bus, and a plurality of signal processing clusters connected to at least two ports and the control bus. Each signal processing cluster comprises a system control processor connected to the control bus, a second control bus, and a global bulk memory having multiple ports. A plurality of functional processing elements are connected to the system control processor by way of the second control bus, and each are connected to a port of the global bulk memory. The global bulk memory comprises a subdata flow network having multiple gateways and full crossbar interconnectivity between each of the multiple gateways.

Abstract: In an arithmetic unit capable of performing arithmetic operations with single byte instructions or a number of bits less than one byte, an instruction which does not specify any register number is executed under the control of a timing control means and a register number stored in a register-specifying memory is selected. When an instruction which does not specify any address is executed under the control of a timing controller, the address information stored in an address-specifying memory is selected, and then the instruction is performed.

Abstract: A database unit monitors the communications occurring within at least one communication system for hardware identification codes of communication or broadcast units. Upon detecting the hardware identification code, the database unit compares the one received with a stored hardware identification code for the unit. When the stored hardware code does not match the one received, the database unit indicates that the unit has undergone an unauthorized modification.

Abstract: A data editing apparatus includes a mass storage device to edit multimedia data such as picture, audio, text and other data. By the visual graphic display of the time positions of the edited information, the user can easily grasp the reproduction time of the picture, text and audio data, thereby simplifying synchronization of plural media data. Graphic editing may be effected to facilitate multimedia data editing.

Abstract: A digital signal processing apparatus which employs a ROM-stored library of predetermined instructions which are user-accessible via a sequencer for execution as a program of instructions. The apparatus preferably may also include an instruction RAM which is user-programmable to supplement the prestored instructions in the on-board instruction ROM.

Abstract: The invention relates to an inexpensive telecommunications device utilizing existent components located in the home or office, such as a television receiver and a telephone, for creating an interactive display terminal for accessing information stored in remote computer databases. In one embodiment according to the invention, the terminal is configured with the necessary logic components to communicate with a host computer system via telephone lines. Alternatively, the device may be directly connected to an inhouse data retrieval network. The terminal is software controlled at the host database and can be dedicated to a particular host computer database system, or may be utilized with various host systems. A multiple screen memory, which is programmable at the host database, may be utilized for storing multiple television screens of information. Peripheral components, such as a printer or disk drive, may be attached to the terminal.