Abstract: A computer system comprising a plurality of caching agents with a cache hierarchy, the caching agents sharing memory across a system bus and issuing memory access requests in accordance with a protocol wherein a line of a cache has a present state comprising one of a plurality of line states. The plurality of line states includes a modified (M) state, wherein a line of a first caching agent in M state has data which is more recent than any other copy in the system; an exclusive (E) state, wherein a line in E state in a first caching agent is the only one of the agents in the system which has a copy of the data in a line of the cache, the first caching agent modifying the data in the cache line independent of other said agents coupled to the system bus; a shared (S) state, wherein a line in S state indicates that more than one of the agents has a copy of the data in the line; and an invalid (I) state indicating that the line does not exist in the cache.

Abstract: A computer system is described. The computer system includes a bus, a CPU coupled to the bus, and a memory coupled to the bus. A peripheral device is coupled to the bus for performing a predefined peripheral operation. A logic is coupled to the bus and the peripheral device for causing the CPU to be interrupted to control the peripheral device for the peripheral operation when the logic receives a request for the peripheral operation. The logic does not control the peripheral device to perform the peripheral operation. The peripheral operation of the peripheral device is only controlled by the CPU. The request may be generated by a software program running on the CPU. The request may also be generated by the peripheral device. Although the CPU is controlling the peripheral operation, the existing peripheral controller-based application software can still be used. A method for controlling the peripheral device for the peripheral operation is also described.

Abstract: A network analysis method is applied to traffic data collected in respect of a network of the type comprising a plurality of logical segments each with a plurality of nodes. The method involves processing the traffic data by preferentially removing traffic associated with nodes identified as acting as global servers, and using the remaining traffic to identify nodes acting as local servers. Upon the local servers being identified, the network analysis method carries out further processing to make suggestions as to whether any of these local servers should be moved to another logical segment and as to whether it would be worthwhile splitting a segment between two associated local servers.

Abstract: In a milli-mode processor, bits (0-6) of an access list entry token (ALET) in the program access register must be zeros in order for access register translation to be successful. When the ALET is being copied from a program access register to a millicode access register, bits 0-3 of ALET, written into the millicode access register, are set to the access register number of the program access register from which the data is being read. This establishes the affinity between the program access register number and any logical fetches which might be attempted by millicode.

Abstract: A sorting apparatus is composed of sort processors connected in a pipeline fashion. Each sort processor 106 merge sorts data from the preceding sort processor and then outputs the merge sort result to the succeeding sort processor. The sort processor includes sort core portions and a front end internal storage and a back end internal storage for the respective sort core portions. Outside the sort processors, there are added external memories for the respective sort core portions. The front and back end internal storages and the external memories constitute a local memory. The sort core portions use, when a faulty area is found in the local memory, part of the front end and back end internal storages as an alternative memory.

Abstract: A system resource enable apparatus for enabling operations on a system resource including a register representing current and future operations on the resource, a pattern generator that applies a pattern corresponding to a requested resource operation to each of a plurality of requests for resource operations in a queue, compare logic that determines for each of the plurality of requests if the request will conflict with other resource operations by comparing the pattern applied to the request with the register, priority grant logic that grants priority to a request in the queue if no conflict is determined and to update the register according to the pattern applied to the request, and resource enable logic that enables operations on the resource according to the register.

Abstract: A system resource enable apparatus for enabling operations on a system resource including a register representing current and future operations on the resource, a pattern generator that applies a pattern corresponding to a requested resource operation to each of a plurality of requests for resource operations in a queue, compare logic that determines for each of the plurality of requests if the request will conflict with other resource operations by comparing the pattern applied to the request with the register, priority grant logic that grants priority to a request in the queue if no conflict is determined and to update the register according to the pattern applied to the request, and resource enable logic that enables operations on the resource according to the register.

Abstract: A network architecture and methodology provides two stages or levels of network redirection to allow effective importation of storage into either or both of a client/requester and a server. Each level of redirection is achieved through the establishment of a bi-directional communication link, preferably by the creation of an access list or export file at each host containing a portion of a distributed resource. By using two levels of network redirection, a terminal communicates only with a single, predetermined server, thus permitting the use of user-friendly Lan server systems. The predetermined server communicates with the remainder of the network as a client through the network communication protocols, thus removing constraints on operating systems which may be running at hosts. Full access to the distributed resource is thereby made transparent to the user and operational limitations engendered by limitations of hard disk capacity at terminals and servers are overcome.

Abstract: To connect the various stations of a data processing system, a bus system is used, to which all users have access. In accordance with the invention, a method for automatic assignment of bus addresses is provided, whereby each user generates a random address that is enquired by a control unit. After clashes recognized by the control unit, this method is repeated until each user has been assigned a clear address.

Abstract: A dual bus architecture for a computer system including a number of computer system devices and a number of computer system resources. Each of the computer system devices and computer system resources are coupled by first and second communication busses. First and second bus arbitrators provide bus arbitration functions allowing first and second computer system devices to access first and second computer system resources simultaneously. A method of accessing a number of computer system resources by a number of computer system devices coupled by a dual bus architecture is also provided.

Abstract: Distributed processing systems having a host processor and at least one object oriented processor are disclosed. An object oriented processor according to the invention has a communications interface, an intelligent message handler, and a task-specific functionality. The communications interface is coupled to a host processor via a message based communications link. A high level command language is provided which is easily implemented in a host processor program. The command language includes subsets of commands which are understood by different object oriented processors having different functionality. According to one embodiment, the object oriented processor includes support for a broad array of input and output devices. The command language includes high level commands for initializing, reading from and/or writing to the peripherals supported by the object oriented processor.

Abstract: A coprocessor has a systolic array of processors each associated with a memory; an array data bus conveying input data to and output data from connections to the array; data buffers for the input and output data; an input and output data bus communicating with the data buffers and with a host processor; a control bus conveying successive operation codes to the array processors an instruction control store containing instructions providing operation codes for successive operations of the array processors, and a sequencer to select instructions from the control store. An intermediate data bus with a microprocessor and further random access memory communicating with that bus, carries input and output data for the array, input and output data for the microprocessor, and addresses for the memories associated with the processors of the array and for the sequencer.

Abstract: A new system and method allows a Manager in a Simple Network Management Protocol (SNMP) environment to gather updates from its Agents. The system and method comprise the unique provision of an index which is used in each of the Agent's tables for indicating the various revisions thereof. The index lexicographically increases with each revision to the table. The Manager maintains a record of the index of the data which it has received from its Agents, requesting only that data having a lexicographically larger indexing. Further, the index is used in related tables so that the tables will be kept in "sync" in that the Manager will know whether it has the latest updates so that an accurate picture may be portrayed.

Abstract: In an Open System Interconnection (OSI) environment, an agent Common Management Information Protocol (CMIP) platform maintains an up to date tree of all of the Managed Object Instances (MOIs), in order to perform scoping functions. The agent platform receives a message from an OSI manager which includes a base MOI and levels below the base MOI to receive the message. The agent platform recurses through the tree below the base MOI to determine which MOIs should receive the message. If the message is delete, the children of MOIs to be deleted are also deleted. The children of undeletable MOIs are not deleted. A current, accurate tree is maintained by the agent platform, which can register a new MOI in the tree when a valid request is received from the MOI or the manager. The agent platform can also deregister an MOI upon valid request from the agent associated with the platform.

Abstract: A trigger is armed to a predetermined detection point (DP) of a basic call state model controlled for each call by a switching system so that a service control point (SCP) can be unconditionally activated. The SCP stores service control information for each time band in such a manner as to correspond to each user. When a first control signal is received from the switching system, the DP which is determined by the service control information is notified to the switching system and the switching system arms the trigger to this DP. When the state of the call shifts to a specific DP to which the trigger is armed because a called party is busy or does not answer, for example, the switching system sends a second control signal to the SCP, and the SCP notifies a terminating terminal equipment determined by the service control information in response to the second control signal.

Abstract: An adder which reduces signal propagation delay experienced by conventional adders by calculating bitwise carries and utilizing these bitwise carries as non-selecting inputs. In a preferred embodiment, the adder includes three primary circuits. The first circuit for generating propagate and generate signals based on its two inputs. The second circuit uses the propagate and generate signals in combination with a global carry-in signal to produce bitwise carries based on the Kogge-Stone Parallel Algorithm. These bitwise carries in combination with bit sums of the first and second digital inputs are used to calculate a plurality of real bit sums corresponding to the sum of these digital inputs.

Abstract: A modular array processor architecture (10) comprising a plurality of interconnected parallel processing node (11)s that each comprise a control processor (12), an arithmetic processor (13) having an input port (22) for receiving data from an external source that is to be processed, a node memory (14) that also comprises a portion of a distributed global memory, and a network interface (15) coupled between the control processor (12), the arithmetic processor (13), and the node memory (14). Data and control buses (17, 18) are coupled between the arithmetic processors (13) and network interfaces (14) of each of the processing nodes (11). Respective network interfaces (15) link each of the arithmetic processors (13), node memories (14) and control processors (12) together to provide for communication throughout the architecture (10) and permit each node to communicate with the node memories (14) of all other processing nodes (11).

Abstract: A simple, but effective method and apparatus for employing the same is utilized to ensure the atomicity of atomic instructions. Two bits which are visible in a register are used. The control bit is read and write accessible. The status bit is read only accessible. The control bit and status bit are coupled such that the state of the status bit is updated with the state of the control bit after a predetermined delay. Therefore, code can be written to utilize the feature to execute an atomic instruction. Execution of the atomic instruction is initiated, the control bit is set and an instruction, such as branch if clear, is executed which causes the processor to wait until the status bit is set before executing subsequent instructions. Therefore, the atomic instruction has sufficient time to complete execution before the status bit is set and subsequent instruction are executed.

Abstract: An address encoding method and an address decoding circuit therefor is disclosed. In the address encoding method, a part of the outputs of address latches are made to designate circuits to be controlled, and the rest of the outputs are made to designate the relevant addresses of the circuits to be controlled. Based on this method, the constitution of the decoding circuit becomes simple.

Abstract: A microcomputer including an EEPROM in which data may be stored and from which stored data may be read either under control of a central processing unit of the microcomputer or under direct external control. The microcomputer includes separate inputs for data input and data output signals when storing and reading is under the control of the central processing unit and when storing and reading of data is under direct external control. The central processing unit may inhibit direct external control of storing data in and reading data from the EEPROM.