Abstract: A method and system are disclosed for reducing run-time delay during conditional branch instruction execution in a pipelined processor system. A series of queued sequential instructions and conditional branch instructions are processed wherein each conditional branch instruction specifies an associated conditional branch to be taken in response to a selected outcome of processing one or more sequential instructions. Upon detection of a conditional branch instruction within the queue, a group of target instructions are fetched based upon a prediction that an associated conditional branch will be taken. Sequential instructions within the queue following the conditional branch instruction are then purged and the target instructions loaded into the queue only in response to a successful a retrieval of the target instructions, such that the sequential instructions may be processed without delay if the prediction that the conditional branch is taken proves invalid prior to retrieval of the target instructions.

Abstract: A massively parallel processor apparatus having an instruction set architecture for each of the N.sup.2 the PEs of the structure. The apparatus which we prefer will have a PE structure consisting of PEs that contain instruction and data storage units, receive instructions and data, and execute instructions. The N.sup.2 structure should contain "N" communicating ALU trees, "N" programmable root tree processor units, and an arrangement for communicating both instructions, data, and the root tree processor outputs back to the input processing elements by means of the communicating ALU trees. The apparatus can be structured as a bit-serial or word parallel system. The preferred structure contains N.sup.2 PEs, identified as PE.sub.column,row, in a N root tree processor system, placed in the form of a N by N processor array that has been folded along the diagonal and made up of diagonal cells and general cells. The Diagonal-Cells are comprised of a single processing element identified as PE.sub.

Abstract: A system and method are described which take an arbitrarily assembled collection of nodes on a bus or network and imposes an optimized hierarchical tree structure where there is only one root node. Nodes having both parent and child nodes are considered branch nodes while nodes having only parent nodes are leaf nodes. Loops or cycles in the physical topology are resolved into a logical topology that is acyclic and directed. A signaling scheme is developed in which nodes, via on board communications hardware, signal all connected nodes and respond accordingly until hierarchical relationships are established. Cycles are resolved by intelligently breaking links to yield an acyclic graph. Direction is established by each node recognizing its parent/child status with respect to connected nodes until a single node is established as a root node.

Abstract: A protection system for a computer is provided. This system is essentially based on the provision of an EEPROM (20) of unstandard access and containing configuration data of the computer as well as a password. At power-on, the contents of the EEPROM except eventually the password, are copied into a CMOS memory (16) which must conventionally be present in the computer. The invention eventually provides additional circuitry for irreversibly cutting the access to the EEPROM and specified peripheric devices.

Abstract: A process for terminating a client server network connection that includes a first automatic termination of all programs executing on the client from code accessed from the server. The disconnection processing interrogates the client computer system to determine any open program files or libraries. Network program files or libraries result in a user prompting to determine whether they should be automatically terminated. In an alternate embodiment, a profile may indicate whether automatic termination will take place without user notification. Once all network loaded programs have been terminated, the disconnection process proceeds normally to sever the network connection.

Abstract: In a computer network system having client and server computers (26,27), an access right check requesting section (28) of the client computer supplies a user certification datum to a access right checking section (32) of the server computer. The access right checking section (32) checks a name of a user and a password of the user certification datum with predetermined held names of users and predetermined held passwords to produce and supply a certification result datum to a client certification result holding section (29) of the client computer when the name of the user coincides with the one of predetermined held names of the users and when the password coincides with the one of predetermined held passwords. A process requesting section (30) compares the certification result datum of the client certification result holding section (29) with the user certification datum which is supplied with a process requesting command having the user certification datum.

Abstract: A receive buffer management system associates a virtual buffer pool with each node communicating with a receiver and creates an actual buffer pool for use by all nodes, with a "low-water-mark" indicating buffers are running out and a "high-water-mark" indicating enough buffers are available. Each time a buffer is taken a count is added to the virtual pool for that sending node and each time a buffer is returned to the actual pool, the counter for the sending node's virtual pool is decremented. Each virtual pool has a quota. Buffers are allocated until the number of buffers in the actual buffer pool drops below the low-water-mark. Then packets from a node above its quota will be discarded and those buffers will be immediately returned to the actual pool. Packets will be discarded for all over-quota nodes until those nodes drop below their quota or the actual pool reaches the high-water-mark. Alternatively, a sliding window acknowledgement replaces the virtual pool and counter.

Abstract: A parallel processor system controls access to a distributed shared memory and to plural cache memories to prevent frequently-used local data from being flushed out of a cache memory. The parallel processor system includes a plurality of nodes each including a processor and a shared memory in a distributed shared memory arrangement, and a local-remote divided cache memory system, wherein local data and remote data are controlled separately. Each local-remote divided cache memory system includes a local data area, a remote data area, and a cache memory controller by which either the local data area or the remote data area is accessed according to the contents of an access request.

Abstract: A generic network device includes a serial line switching apparatus for performing either parallel or serial communications amongst multiple nodes over switching networks. An aspect includes is the adaptation of standard and proprietary serial interfaces using either optical or electrical transmission media to interface to the parallel switch. The converted serial data is routed to the selected destination through the parallel switch network, where it is received and converted back into a serial optical or electrical interface/protocol. Thus, the combination of the switching adapter and an ALLNODE parallel switching network make it feasible for serial message data to be switched and routed to various destinations.

Abstract: A communication data processor. Data received from a communication channel is stored in a data area. A list area corresponding to the data area in which the communication data has been stored is deleted from a vacant list management area and then added to a logical check list management area. A list area corresponding to a data area logically checked by a lower layer logical check section is deleted from the logical check list management area and then added to a higher layer protocol classification list management area. A list area corresponding to a data area classified by a higher layer protocol classification section is deleted from the higher layer protocol classification list management area and then added to the vacant list management area. When data relating to a protocol having an OSI model is to be processed, it is not required to perform the transfer of real data in a data storage.

Abstract: An interconnect mechanism for allowing use of an IDE compatible add-in card in a PCI compliant expansion slot. Unused PCI pins are exploited to provide for proper routing of necessary interrupt signals from an IDE add-in card. The presence of the IDE card in the PCI slot enables signaling circuitry for routing IDE interrupts to the computer system's interrupt controller and reroutes existing hard disk interrupt signals to the interrupt controller as a secondary hard disk interrupt. Another otherwise unused pin is exploited to provide a signal for lighting the computer system's hard disk active indicating LED. The gating circuitry is provided such that non-IDE, PCI-compliant add-in cards are provided with unaffected operation in the PCI slot.

Abstract: A communications device is attachable to a host computer. The device transmits, receives, and stores entire files of data with their attributes needed for recognition, reading, and writing by a proper application program. Logical devices such as processors, filters, locks, and telecommunications devices in the communications device include electronic circuits for assembling message files and for transmitting selected datafiles to and from an attached host computer. The communications device also transmits, stores and receives with respect to a second remote device or a computer with a modem. The device permits file communication without permitting access to its own host computer or workstation. The device may transmit while the computer is off, and without logging into the second computer provided with the same type of device.

Abstract: In arrays of processors, especially linear arrays, it is important to be able to communicate to adjacent neighbors (en masse). That is, each element of the array can communicate with its neighbor on the left simultaneously. In addition, the array processor is provided with the ability for selected elements of the array, picket processing elements, to simultaneously communicate with other elements that are further away in one dimension than the nearest neighbor in one transfer cycle. This is accomplished by causing intermediate elements to become transparent in the communication paths, thus allowing data to "slide" through intermediate nodes to the destination node. This system can be used in the implementation of fault tolerance in the array of elements.

Abstract: A naming service maintains lists of names for receiving messages, with the names having a defined format portion for routing messages in the network. At least some names have additional routing information that is passed to another server or service for routing the messages externally, such as with remote e-mail or facsimile transmission.

Abstract: The present invention discloses a distributed data transfer system for transferring data among several processing units and an integrated data storage means, e.g., a memory sub-system. The distributed data transfer system includes a plurality of distributed data transfer means for connecting to the processing units. The distributed data transfer system further includes a distribution control means connected to the distributed data transfer means and the integrated data storage means. The distributed data transfer means, under the control of the distribution control means, is capable of transferring the data in divisible portions over a plurality of scheduled time periods. In a preferred embodiment, the distributed data transfer means further includes a plurality of data bus branches and a bus trunk connecting to the data bus branches. The distribution control means further includes a programmable control means for down-loading of control programs for controlling the distributed data transfers.

Abstract: The present invention provides a program control system including plural programs, plural execution means each of which executes the corresponding program of the plural programs, a memory for storing the plural programs, plural program counters each of which generates an address for reading the corresponding one of the programs from the memory, and a selector for selecting an output of one of the program counters and providing the output to the memory. Each of the programs stored in the memory and executed by the corresponding one of the execution means is indicated by the address generated by the corresponding one of the program counters selected by the selector, and the memory sequentially stores instructions in each of the programs.

Abstract: A mechanism and method providing an early read operation of data associated with an instruction dispatched for execution to provide data dependency information in time to be used for scheduling subsequent instructions which may execute back-to-back in a pipeline microprocessor. The present invention provides the above functionality for instructions following single cycle instructions. The present invention provides immediate scheduling of instructions that are dependent on single cycle instructions. A reservation station holds the information pertaining to instructions that are to be scheduled for execution. The early read logic is implemented so that an address of a destination register associated with a dispatched single cycle instruction can be read from the associated entry of the reservation station early enough so as to be used and compared against the addresses of source registers of other instructions waiting to be scheduled (a CAM match).

Abstract: A computer model for facilitating computer assisted design includes data structures which are flexibly organized by storing of information in accordance with entities or simulations thereof (including symbolic layer entities, area entities, area spec entities and area spec usage pattern entities), which are hierarchically associated both by relationships between them at a given level of abstraction of the physical entity they represent and by various attributes that correspond to different levels of abstraction in graphs. The graphs are freely mappable onto any desired fixed data structure such as a hierarchical area tree. Each hierarchical level and particularly the symbolic layer entity within the computer model provides data hiding at each lower level thereof and thus provides data hiding in the fixed data structure by virtue of the mapping function in order to reduce data processing overhead for manipulation of the fixed data structure.

Abstract: An arithmetic and logic operation system capable of performing an arithmetic and logic operation for data longer than one word, includes an arithmetic and logic unit for performing an arithmetic and logic operation for a less significant one-word length portion of the data, and an incrementer/decrementer for incrementing or decrementing of a more significant data portion exceeding the one-word length of the data. A carry signal or a borrow signal generated in the arithmetic and logic unit is supplied to the incrementer/decrementer so that the incrementer/decrementer is controlled so as to selectively increment, or decrement the received data or alternately to output the received data without modification.

Abstract: A power conservation system for use in a computer system. The power conservation system has an activity monitor and a plurality of modes of operation. The power conservation system has a power switching unit which couples the power supply to a selected group of the computer system circuits depending upon the power mode of operation. By controlling the power mode in response to the activity of the computer system, the power consumption of the computer system can be controlled.