Abstract: Systems and/or methods that facilitate accessing data in a memory are presented. The memory can be flash memory that includes a plurality of sectors in an array that can be associated with a decoder component that includes a regulator component, which facilitates performing read operations within a desired period of time. Each sector can be associated with a decoder subcomponent and associated regulator subcomponent. Parasitic resistance and capacitance elements can increase the further in distance a sector and associated decoder component are from a booster component, which is utilized to increase the voltage at a boost-strap node within each decoder subcomponent to facilitate performing read operations. To counter the parasitic elements, each regulator subcomponent can include one or more capacitors, where the number of capacitors and total capacitance value can be determined based on the distance the associated decoder subcomponent is from the booster component.

Abstract: A system and method for reducing soft-writing in a multilevel flash memory during read or verify includes a memory cell. A first and second reference cells are coupled to the memory cell and are configured to receive a first and a second voltage. A current comparison circuit is coupled to the first and second reference cells and to the memory cell and is configured to compare current flow through the memory cell with current flow through the first and second reference cells, and to determine whether the memory cell holds a first range of values while the first reference cell receives the first voltage, and if the memory cell does not hold the first range of values, to determine whether the memory cell holds a second range of values while the second reference cell receives the second voltage, thereby reducing soft-writing during the read operation.

Abstract: A semiconductor memory device includes a memory cell array with memory cells arranged therein, each memory cell being settable to have one of plural physical quantity levels, simultaneously selected two memory cells constituting a pair cell serving as a data storage unit, wherein each memory cell is set to have one in N (where N is an integer equal to three or more) physical quantity levels, and each pair cell is set to have different physical quantity levels in two memory cells therein, thereby storing M-value data defined by M=2n (where M>N and “n” is an integer equal to two or more), the M-value data being defined by such M combination states that differences of the physical quantity levels in the two memory cells are different from each other.

Abstract: Shifts in the apparent charge stored on a floating gate (or other charge storage element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other charge storing elements). To account for this coupling, the read process for a targeted memory cell will provide compensation to an adjacent memory cell (or other memory cell) in order to reduce the coupling effect that the adjacent memory cell has on the targeted memory cell. The compensation applied is based on a condition of the adjacent memory cell. To apply the correct compensation, the read process will at least partially intermix read operations for the adjacent memory cell with read operations for the targeted memory cell.

Abstract: In sensing a group of cells in a multi-state nonvolatile memory, multiple sensing cycles relative to different demarcation threshold levels are needed to resolve all possible multiple memory states. Each sensing cycle has a sensing pass. It may also include a pre-sensing pass or sub-cycle to identify the cells whose threshold voltages are below the demarcation threshold level currently being sensed relative to. These are higher current cells which can be turned off to achieve power-saving and reduced source bias errors. The cells are turned off by having their associated bit lines locked out to ground. A repeat sensing pass will then produced more accurate results. Circuitry and methods are provided to selectively enable or disable bit-line lockouts and pre-sensing in order to improving performance while ensuring the sensing operation does not consume more than a maximum current level.

Abstract: A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a negative substrate bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. The negative substrate bias voltage also reduces the occurrence of program disturbs in cells adjacent to target cells by extending the depletion region deeper below the bit line that corresponds to the drain of the target device. The negative substrate bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce error in the verification operations.

Abstract: In sensing a group of cells in a multi-state nonvolatile memory, multiple sensing cycles relative to different demarcation threshold levels are needed to resolve all possible multiple memory states. Each sensing cycle has a sensing pass. It may also include a pre-sensing pass or sub-cycle to identify the cells whose threshold voltages are below the demarcation threshold level currently being sensed relative to. These are higher current cells which can be turned off to achieve power-saving and reduced source bias errors. The cells are turned off by having their associated bit lines locked out to ground. A repeat sensing pass will then produced more accurate results. Circuitry and methods are provided to selectively enable or disable bit-line lockouts and pre-sensing in order to improving performance while ensuring the sensing operation does not consume more than a maximum current level.

Abstract: A NAND flash memory having a cell string structure includes a wordline configured to transfer a wordline voltage to a memory cell. A selection line is configured to transfer a selection voltage to a selection transistor connected to the memory cell and at least one shielding line is interposed between the wordline and the selection line and is operable to reduce capacitance-coupling between the wordline and the selection line during a programming operation.

Abstract: Methods and circuitry are present for executing current memory operation while other multiple pending memory operations are queued. Furthermore, when certain conditions are satisfied, some of these memory operations are combinable or mergeable for improved efficiency and other benefits. The management of the multiple memory operations is accomplished by the provision of a memory operation queue controlled by a memory operation queue manager. The memory operation queue manager is preferably implemented as a module in the state machine that controls the execution of a memory operation in the memory array.

Abstract: A nonvolatile semiconductor memory includes: a first semiconductor chip on which a first memory in mounted; a second semiconductor chip on which a second memory is mounted; wherein in the second memory which is a destination for copying, a read enable operation is performed after booting up a command which makes the read enable operation recognize as a write enable operation, and a data of the first memory, which is a source of the copy, is copied to the second memory.

Abstract: Various embodiments include a circuit to receive data information, a memory array including memory cells coupled to a bit line, and control circuitry to charge the bit line while the data information is received at the circuit. The control circuitry may program the data information into a selected memory cell of the memory cells after the data information is received at the circuit. Other embodiments including additional methods, apparatus, and systems are disclosed.

Abstract: A row active control circuit of a PSRAM controls a refresh timing when a refresh operation is performed before activation of a row path for embodiment of a page mode, thereby preventing mis-operations. The row active signal generating unit generates a row active signal when an active condition is set by the internal active signal. The internal active signal generating unit generates the internal active signal in response to a refresh start signal. The row active control unit generates a row active standby signal with the row active signal in response to the internal active signal. The external active signal generating unit for generating an external active control signal in response to the row active standby signal.

Abstract: A bit line is connected to a charge storing circuit through a charge transferring circuit. A control circuit controls charge transferability of the charge transferring circuit according to a change in the voltage of the bit line resulting from a charge read out from a memory cell. A leakage controlling circuit lowers the charge transferability of the charge transferring circuit in a read operation temporarily before the charge is read out to the bit line. The leakage controlling circuit makes it possible to avoid charge transfer between the charge storing circuit and the bit line before data is read from the memory cell. The charge storing circuit can thus generate a read voltage sufficient for a read circuit to operate with, in accordance with the logical value of the data stored in the memory cell.

Abstract: Methods and apparatuses for automatically measuring memory cell threshold voltages are disclosed. Measurement circuitry includes an internal reference current generator, a plurality of memory cells, a pre-charge bit line reference circuit, and comparator and latch circuitry. If the reference current is greater than the memory cell current, the bit line voltage will increase. Conversely, if the reference current is less than the memory cell current, the bit line voltage will decrease. The reference current is generated in large steps until a comparator, that compares the bit line voltage and a pre-charged bit line reference voltage, is switched. The reference current then generates a current in small steps until the comparator is again switched. The reference current converges on the memory cell current within an accuracy of 10 nA. The memory cell threshold voltage is then determined from the memory cell current. Systems including memory according to an embodiment of the invention are also disclosed.

Abstract: In a method of inputting/outputting data in a semiconductor memory device, first data and second data are buffered and outputted to a first output node and a second output node, respectively, in a normal mode. In a test mode, the first data is buffered through a first transmission line and a second transmission line and outputted to the first output node and the second output node in response to at least one control signal. Also, in the test mode, the second data is buffered through the first transmission line and the second transmission line and outputted to the first output node and the second output node in response to the at least one control signal. Accordingly, test time may be reduced, and variations of operation characteristics caused by merging the data pins may also be reduced.

Abstract: A semiconductor memory device includes a memory cell array including memory cells, word lines which select the memory cells, bit lines which transfer data of the memory cells, a sense amplifier circuit which amplifies data transferred to the bit lines, a first dummy cell group including first dummy cells, a dummy word line which selects the first dummy cell group, a dummy bit line to which data of the first dummy cell group is transferred, a generation circuit which generates an activation signal to activate the sense amplifier circuit based on a variation in a potential level of the dummy bit line, and a potential generating circuit which generates a first source potential applied to the first dummy cell group. The first source potential is different from a power supply potential.

Abstract: A phase-change random access memory device is provided. The phase-change random access memory device includes a plurality of memory blocks, a main word line, a plurality of local word lines and a plurality of section word line drivers connected between the main word line and each of the plurality of local word lines and adapted to adjusting voltage levels of the plurality of local word lines in response of voltages applied to the main word line and block information. The plurality of section word line drivers include at least one first section word line driver and at least one second section word line driver. The first section word line drivers include pull-down devices while not including pull-up devices.

Abstract: The direction of magnetization of a reading ferromagnetic material 5R forming a spin filter when reading is the same as that of a pinned layer 1. In this case, a torque that works on the spin of a free layer 3 due to a spin polarized current becomes “zero.” When the element size is made small so as to improve the integration degree of the magnetic memory, according to the scaling law, the writing current can be made small. In the present invention, the resistance to the spin injection magnetization reversal due to a reading current is high, so that the magnitude of the writing current can be lowered.

Abstract: Source contacts of driver transistors are short-circuited through the use of an internal metal line within a memory cell. This metal line is isolated from memory cells in an adjacent column and extends in a zigzag form in a direction of the columns of memory cells. Individual lines for transmitting the source voltage of driver transistors can be provided for each column, and the source voltage of driver transistors can be adjusted also in units of memory cell columns in the structure of single port memory cell.

Abstract: An array structure of single-level poly NMOS EEPROM memory cells and method of operating the array is discussed implemented in a higher density embedded EEPROM layout that eliminates the use of high voltage transistors from the array core region. If they are utilized, the high voltage transistors are moved to row and column drivers in the periphery region to increase array density with little or no added process complexity to allow economic implementation of larger embedded SLP EEPROM arrays. During program or erase operations of the array, the method provides a programming voltage for the selected memory cells of the array, and a half-write (e.g., mid-level) voltage to the remaining unselected memory cells to avoid disturbing the unselected memory cells of the array.