Abstract: Embodiments of the present invention help to increase yaw stiffness while achieving higher peel stiffness and lower roll stiffness and pitch stiffness in a suspension supporting a head slider. A gimbal according to an aspect of the present invention has a securing point where the gimbal is secured to a load beam in the front and securing points where the gimbal is secured to the load beam in the rear. The gimbal tongue pivots on a dimple contact point. A front ring is secured at the securing point to support the gimbal tongue. The rear ring is secured at the securing points to support the gimbal tongue. The rear ring provides the gimbal tongue with higher yaw stiffness than the front ring. The front ring provides the gimbal tongue with higher peel stiffness than the rear ring.

Abstract: A nonvolatile memory device includes a plurality of memory banks, each including a plurality of nonvolatile resistive memory cells (e.g. PRAM cells). The device also includes a write global bitline shared by the memory banks and a read global bitline shared by the memory banks. The device further includes a control circuit configured to write data to a selected nonvolatile memory cell in a first memory bank using the write global bitline while reading data from a selected nonvolatile memory cell in a second memory bank using the read global bitline such that a discharge time period of the write global bitline is longer than a quenching time period of a write current which flows through the nonvolatile memory cell of the first memory bank.

Abstract: In a non-volatile semiconductor memory device, variations in voltage applied to a bit line when an erase voltage applying step is repeatedly executed are suppressed, thereby reducing variations in Vt after erasure. A memory array includes memory cells arranged in an array, a plurality of word lines, and a plurality of bit lines and main bit lines. The memory array also includes a usable region which can store data and an isolation region which cannot store data. Each bit line provided in the usable region is connected via a select transistor to the corresponding main bit line. At least one main bit line is connected not only to a bit line of the usable region, but also to a bit line of the isolation region via a select transistor.

Abstract: An inadvertent write can be prevented when a read is performed. The duration of the write current pulse for writing information in the magnetic memory layer is longer than the duration of the read current pulse for reading the information from the magnetic memory layer.

Abstract: A semiconductor integrated circuit includes a sense amplifier for sensing input data and a sense amplifier controller for blocking a signal path between the sense amplifier and a memory cell when a test mode signal is activated.

Abstract: A test circuit and method for use in a semiconductor memory device is provided. The test method for use in a semiconductor memory device including a plurality of memory blocks may include sequentially enabling a plurality of word lines by applying a stress to the wordlines and performing a test operation, in response to sequentially applied test addresses, each of the word lines being sequentially selected from the plurality of memory blocks and enabled.

Abstract: An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell is programmable to store one of a plurality of data states, and (ii) a bit line, having a plurality of memory cells coupled thereto. Memory cell control circuitry applies one or more read control signals to perform a read operation wherein, in response to the read control signals, a selected memory cell conducts a current which is representative of the data state stored therein. Sense amplifier circuitry senses the data state stored in the selected memory cell using a signal which is responsive to the current conducted by the selected memory cell. Current regulation circuitry is responsively and electrically coupled to the bit line during a portion of the read operation to sink or source at least a portion of the current provided on the bit line.

Abstract: An integrated circuit including an array of memory cells, a circuit, volatile storage, and non-volatile storage. The circuit is configured to detect defective memory cells in the array of memory cells and provide addresses of the defective memory cells. The volatile storage is configured to store the addresses, where each entry in the volatile storage includes one of the addresses and a volatile storage master bit. The non-volatile storage is configured to store the addresses, where each entry in the non-volatile storage includes one of the addresses and a non-volatile storage master bit.

Abstract: A word line voltage is applied to a plurality of word lines. A read/write voltage is applied to a plurality of bit lines. The read/write voltage is applied to a plurality of source lines. A word line selector selects the word line and applies the word line voltage. A driver applies a predetermined voltage to the bit line and the source line, thereby supplying a current to the memory cell. A read circuit reads a first current having flowed through the memory cell, and determines data stored in the memory cell. When performing the read, the driver supplies a second current to second bit lines among other bit lines, which are adjacent to the first bit line through which the first current has flowed. The second current generates a magnetic field in a direction to suppress a write error in the memory cell from which data is to be read.

Abstract: An apparatus for adjustment of a digital delay function of a data memory unit comprising said data memory unit (102), an elastic store register, ESR, (104) and read clock and write clock adapted to control read and write operations, a write counter associated with the write clock and a read counter associated with the read clock. Said memory (102) works in series with said ESR (104). The memory (102) delivers two data elements from two logically neighbouring cells. Said ESR (104) writes the two data elements from the memory (102) at every cycle of the write clock, wherein if the write counter is increased by one at a cycle of the write clock the output position in the memory (102) is not changed, and if the write counter is increased by two at one cycle of the write clock the output position in the memory (102) is moved backward by one data element and if the write counter is not changed at one cycle of the write clock the output position in the memory (102) is moved forward by one data element.

Abstract: A non-volatile semiconductor memory device includes: a memory cell array having electrically rewritable and non-volatile memory cells arranged; a data register circuit configured to hold write data to be written into the memory cell array; and an address decode circuit configured to decode a write address signal and control the write data-loading in the data register circuit, the address decode circuit being settable in such a multiple selection mode that the same write data is loaded in multiple registers in the data register circuit in correspondence to multiple addresses.

Abstract: The present invention provides a technique capable of simplifying a layout structure of a semiconductor device having a semiconductor memory section in which an input port and an output port are separated from each other, and which includes a bypass function. In a semiconductor memory device to be used as a semiconductor memory section of the semiconductor device, in a bypass mode, an output buffer outputs input data transmitted through a bypass line, extending from an input buffer circuit to the output buffer circuit, to an output port. In the layout structure of the semiconductor memory device, in plan view, a memory cell array is arranged between the input buffer circuit and the output buffer circuit, and a bypass line is arranged through between the memory cell arrays.

Abstract: A flash memory storage apparatus including a multi level cell (MLC) NAND flash memory, a flash memory controller, and a host transmission bus is provided. The MLC NAND flash memory includes a plurality of blocks for storing data, wherein each of the blocks has an upper page and a lower page, and the writing speed of the lower page is faster than that of the upper page. The flash memory controller is electrically connected to the MLC NAND flash memory and is used for executing storage mode switching steps. The host transmission bus is electrically connected to the flash memory controller and is used for communicating with a host. The flash memory storage apparatus provided by the present invention can provide multiple storage modes in order to store different data.

Abstract: A phase change memory device is presented that includes a phase change resistance cell array and a cache register. The phase change resistance cell array includes a phase change resistor configured to sense crystallization changed depending on currents so as to store data corresponding to resistance change. The cache register is configured to store a plurality of data applied externally depending on a register write command and to simultaneously output the plurality of data to the phase change resistance cell array depending on a cell write command.

Abstract: Semiconductor-on-diamond (SOD) substrates and methods for making such substrates are provided. In one aspect, a method of making an SOD device is provided that includes etching depressions into an etch surface of a semiconductor substrate to a uniform depth, depositing a diamond layer onto the etch surface to form diamond-filled depressions, and thinning the semiconductor substrate at a thinning surface opposite the etch surface until the diamond filled depressions are exposed, thus forming a semiconductor device having a thickness substantially equal to the uniform depth.

Abstract: An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.

Abstract: By performing a planarization process, for instance based on a planarization layer, prior to forming a resist mask for selectively removing a portion of a stressed contact etch stop layer, the strain-inducing mechanism of a subsequently deposited further contact etch stop layer may be significantly improved.

Abstract: A semiconductor memory device includes a plurality of banks, each configured to receive a bank operation control signal and perform predetermined operations in response to the received bank operation control signal, a plurality of bank control blocks, each configured to receive a bank sequential signal and generate the plurality of bank operation control signals in response to enable periods of the received bank sequential signal, and a bank sequential signal generating block configured to generate the plurality of bank sequential signals each having a multiplicity of enable periods that are sequential in response to a command signal.

Abstract: A MRAM includes a first magnetoresistive effect (MR) element that takes a low and high resistance states. A second MR element is fixed to a low or high resistance state. First and second MOSFETs are connected to the first and second MR elements, respectively. A sense amplifier amplifies a difference between values of current flowing through the first and second MOSFETs. A current circuit outputs reference current whose value lies between current flowing through the first MR element of the low and high resistance states. A third MOSFET has one end that receives the reference current and is connected to its own gate terminal. The gate terminal of the second MOSFET receives the same potential as the gate terminal of the third MOSFET. A first resistance element is connected to the others end of the third MOSFET and has the same resistance as the second magnetoresistive effect element.

Abstract: A detect circuit may be used to detect one or more characteristics corresponding to the fuse being programmed. When the one or more characteristics of the fuse being programmed reach the desired states or values, the programming of the fuse is discontinued. Thus, the programming duration for each fuse is customized for each fuse. As a result, for some embodiments, there may be fewer fuses that have been over-programmed. In addition, for some embodiments, the range of impedances of the programmed fuses have a narrower distribution of impedances due to the use of the detect circuit.