Abstract: The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit lines and a block copy is performed, data is first outputted to the even-bit lines, and after the potential of the even-bit line is determined, the bit line potential holding circuit operates. Then, biasing of the potential of the even-bit lines is carried out by the bit line potential holding circuit, the potentials of the bit lines are maintained and held. At the same time, data is outputted to the odd-bit lines and the potentials of the odd-bit lines are determined. Then, a program voltage is supplied to a selected word line, and data is simultaneously written (programmed) in the memory cells connected to the even-bit lines, and the memory cells connected to the odd-bit lines.

Abstract: Bit lines (BL0, BL0R, BL1, BL1R, . . . ) of a ROM memory array with differential detection reading are arranged within two overlaid metallization levels so as to increase the read reliability of binary values stored in the array. The ROM array is divided into matrix segments (100, 101, . . . ) aligned parallel to the bit lines. The bit lines are shifted horizontally and/or vertically within transition regions (T) located between the segments of matrix, by effecting circular permutations between the positions of the bit lines that are divided up into groups of four.

Abstract: The invention relates to a ROM memory cell of a ROM memory, which provides a first predetermined potential or a second predetermined potential in the driven state at a memory cell output in a manner dependent on the programming state of the ROM memory cell.

Abstract: A memory layout where the pre-charger circuits are connected between different pairs of bit lines than are the sense amplifiers: The two bits lines in each bit line pair are connected to different pre-charge circuits and thus they can be charged to different pre-charge voltages. That is, the bit line and bit line bar sense lines in each bit line pair are connected to different pre-charge circuits. With this configuration it is possible to perform a sense stress test by activating all of the address lines at the same time and to charge to bit line and the bit bar line in each pair of sense lines to different voltages. With this configuration it is possible to reduce the number of test pads required.

Abstract: A method is described for erasing a selected data region in an NROM cell that is a member of a virtual ground NROM EEPROM array. The method provides that erasing the selected data region does not disturb the program state of unselected data regions.

Abstract: An integrated circuit (IC) includes a redundancy feature. The redundancy feature is provided by a redundancy circuitry within the IC. The redundancy circuitry is configured to provide the redundancy by using a decoder circuitry. The decoder circuitry receives and decodes coded defect information from a set of circuit elements adapted to provide the coded defect information.

Abstract: A semiconductor memory device having a stacked-bank architecture capable of activating the word lines coupled to memory cells selectively with respect to the memory banks is disclosed. The semiconductor memory device includes memory bank groups and a decoder unit. Each of the memory bank groups includes a plurality of memory banks arranged in a stacked-bank architecture. The decoder unit generates a decoded row address signal to individually select one of the memory banks in response to an external address signal under the control of an output enable signal. Accordingly, the semiconductor memory device having a stacked-bank architecture capable of activating the word lines coupled to memory cells selectively with respect to the memory banks has lower power consumption and operates stably against noise.

Abstract: A memory array includes a buried diffusion region, a first source line that supplies electrical power to the buried diffusion region, a second source line that supplies electrical power to the buried diffusion region, a first bitline transistor having a first channel width and a second bitline transistor having a second channel width. The first bitline transistor is proximate to the first source line and is electrically coupled to a first memory cell. The first bitline transistor is disposed between the first and second source lines. The second bitline transistor is proximate to the first bitline transistor and is electrically coupled to a second memory cell. The second bitline transistor is disposed between the first and second source lines and is farther from the first source line than the first bitline transistor. The second channel width is greater than the first channel width.

Abstract: The programming speed of a nonvolatile semiconductor memory device used as a flash memory is increased as follows. First, second, and third assist gates, a control gate, as well as first and second storage nodes are created over a p-type well. In the course of a programming operation, first of all, the p-type well is set at 0V. Then, a first inversion layer created by setting the first assist gate at a voltage A is set at a voltage B and the second assist gate is set at a voltage C. Subsequently, a second inversion layer created by setting the third assist gate at a voltage D is set at a voltage E and the control gate is set at a voltage F to inject hot electrons generated on the surface of the p-type well in close proximity to the second assist gate into the second storage node.

Abstract: A step voltage generator includes multiple trainable voltage references. Each of the trimmable voltage references uses a flash cell with a variable threshold voltage and a feedback loop to trim a reference voltage. The threshold voltage of the flash cell can be programmed to affect the reference voltage.

Abstract: Non-volatile memory devices have a page buffer that can verify pre-erase. A non-volatile memory device may include a cell array having a plurality of strings consisting of memory cells disposed at the intersection regions of bit lines and word lines, and a plurality of page buffers connected to the bit lines through a sensing line.

Abstract: A nitride read-only memory (NROM) device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according to comparison of the bias voltage and the reference voltage. The memory cell is connected to the bias unit via a first switch. The cycling cell is connected to the bias unit via a second switch. The compensation cell is connected to the bias unit via a third switch. The control unit is for controlling the cycling cell and the compensation cell according to the bit value.

Abstract: Errors can occur when reading the threshold voltage of a programmed non-volatile storage element due to at least two mechanisms: (1) capacitive coupling between neighboring floating gates and (2) changing conductivity of the channel area after programming (referred to as back pattern effect). To account for coupling between neighboring floating gates, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell. To account for the back pattern effect, a first voltage is used during a verify operation for unselected word lines that have been subjected to a programming operation and a second voltage is used for unselected word lines that have not been subjected to a programming operation. The combination of these two techniques provides for more accurate storage and retrieval of data.

Abstract: A method for reading data from a dynamic memory circuit is provided, wherein at least one memory cell can be addressed via a word line and a bit line, wherein the memory cell is connected to a first reading amplifier via the bit line, and wherein a switching element, which in the off state isolates the first reading amplifier from the bit line, is provided. The method comprises: a) turning on the switching element to connect the first reading amplifier to the bit line, b) activating the word line to activate the memory cell for reading, c) activating the first reading amplifier to initiate assessment of the information on the bit line, d) turning off the switching element to isolate the first reading amplifier from the bit line, and e) transferring the information which has been read to a data bus.

Abstract: A dynamic programming method for a non-volatile storage device is described. Memory cells are provided arrayed in R rows. Sub bit lines are provided coupled to voltage supply lines through select circuits. During program operation, the select circuits are switched such that one or more of the source side sub bit line or the drain side sub bit line is floating when all other program voltages are applied to a selected cell.

Abstract: Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.

Abstract: There provided a semiconductor memory device which ensures writing to all memory cells regardless of fluctuations in properties of the memory cells caused by manufacturing error or the like and can reduce write operation time and power consumption. Write operations for a memory cell 1 and a dummy memory cell 1a are controlled based on a write amplifier control signal WAE. Write operation end timing is determined based on a write completion signal WRST which indicates a storage state of the dummy memory cell 1a. The dummy memory cell 1a and peripheral circuitry are designed so that write time required for the dummy memory cell 1a is more than or equal to a maximum of write time required for the memory cells 1.

Abstract: Provided is directed to an apparatus and method of supplying power in a semiconductor memory device which supplies an external voltage of high level at the beginning operation which current consumption is rapidly increased and then supplies an internal voltage of a target level, but the external voltage is supplied for a longer time in case that the current consumption is increased more when plural pairs of bitlines are selected than when a pair of bitlines is selected, and thus the apparatus comprises the relatively small number of internal voltage generators and also it is capable of improving reliability of a circuit operation.

Abstract: Disclosed is an input data distribution device for a memory device, the input data distribution device comprising: a decoding section for receiving a starting column address applied when a write command is activated; and N number of switching sections each of which receives N bits of data applied sequentially through one data pin after the write command is activated, wherein each of the switching sections exclusively outputs one bit from among the N bits of data by using an output signal of the decoding section and a signal for determining a burst type.

Abstract: A non-volatile memory device performs a multi-page copyback operation where after a plurality of copyback data read out from one or more mats are sequentially stored in a plurality of buffers, the stored data are simultaneously programmed to different mats. The copyback data may be read out without limitation to the location of mats and the number of copyback data to be read out from the respective mats. The read-out copyback data are simultaneously programmed to a plurality of mats.