Abstract: A media streamer (10) includes at least one storage node (16, 17) for storing a digital representation of a video presentation. The Video presentation requires a time T to present in its entirety, and is stored as a plurality of N data blocks, each data block storing data corresponding approximately to a T/N period of the video presentation.

Abstract: Disclosed are apparatus and methods for synchronized interleaving of multimedia data arriving from distinct sources. The invention independently buffers the incoming data streams and determines the amount of presentation time associated with each data element or byte of each data stream. The invention then draws data from the buffers at varying rates that reflect these differences, continuously presenting the withdrawn data to an interleaving module at data-streaming rates that reflect equivalent presentation-time rates. The invention also includes means for disabling synchronization when one type of data is streamed at a particularly high or low rate, resulting in buffer overload (with either the high-rate data or all data other than that transferred at the low rate).

Abstract: An interface arrangement is connected between a scanning head for electro-optically reading bar code symbols and a host device having a host processor operative for processing signals with a predetermined data exchange format. The interface arrangement includes a housing; a first connector on the housing for direct connection to the host device; a second connector on the housing for direct connection to a head cable connected to the scanning head; and a conversion circuit within the housing for converting decoded signals generated in the head into data signals having a format compatible with the predetermined data exchange format of the host processor.

Abstract: A computer system for controlling the mode of operation of a data cache. When a DMA state machine detects a DMA cycle to a memory block, the machine interrupts the processor so the processor sets a new value of the DMA state to control the mode of cache operation associated with the block.

Abstract: An information signal transmission device in which information signals are transmitted to requesting parties responsive to requests made by plural requesting parties. The signals of the leading end of the information signals are pre-stored in a versing-up memory and, when a request is made by a requesting party, an output signal of a buffer memory unit for time axis expansion is transmitted to such requesting party after an output signal of the versing-up memory unit is transmitted to such requesting party.

Abstract: A hard disk controller integrated circuit of a SCSI target device comprises a sequencer which causes a SCSI bus to transition from a command bus phase to a data transfer bus phase during execution of an autoread or an autowrite SCSI command without waiting for a communication from a microprocessor of the SCSI target device. In some embodiments, the command is determined to be either an autotransfer command or a non-autotransfer command. If the command is a non-autotransfer command, then the sequencer does not proceed directly to the data transfer phase but rather requires microprocessor intervention before proceeding to the data transfer phase. In some embodiments, an autotransfer command (such as an autoread or an autowrite command) is carried out by the disk drive controller integrated circuit with only two interrupts being generated to the microprocessor: one after receiving the autotransfer command from the initiator; and one after data transfer of the autotransfer command is complete.

Abstract: A hard disk controller integrated circuit of a SCSI target device comprises a sequencer which causes a SCSI bus to transition from a command bus phase to a data transfer bus phase during execution of an autoread or an autowrite SCSI command without waiting for a communication from a microprocessor of the SCSI target device. In some embodiments, the command is determined to be either an autotransfer command or a non-autotransfer command. If the command is a non-autotransfer command, then the sequencer does not proceed directly to the data transfer phase but rather requires microprocessor intervention before proceeding to the data transfer phase. In some embodiments, an autotransfer command (such as an autoread or an autowrite command) is carried out by the disk drive controller integrated circuit with only two interrupts being generated to the microprocessor: one after receiving the autotransfer command from the initiator; and one after data transfer of the autotransfer command is complete.

Abstract: A computer system as provided with an internal flash ROM which includes the BIOS. In the event the flash ROM becomes corrupt, a special purpose interface allows for mode switching of a standard parallel port from a standard peripheral interface, such as a printer interface to a special purpose interface to enable the BIOS to be executed from an external ROM or another computer connected to the parallel port.

Abstract: A high performance serial bus operating at multiple transmission rates is disclosed. The serial bus is able to automatically generate data response packets for return to a requesting node. The automatic packet generation uses the source and destination information to generate a return destination packet for directing the requested data to the request source destination. Since the bus network is capable of operating at several different transmission rates, the speed at which the data request packet was transmitted is used for retransmitting the data requested back to the source node requesting the data.

Abstract: A micro processor including a bus fraction register with an encoding which when decoded indicates either a bus fraction encoding or a stop clock function, data processing logic that includes a number of units including a bus unit, arranged as an instruction pipeline. The units are clocked by an internal clock running at a first frequency and operating with an I/O bus clocked by an I/O clock running at a second frequency which is a fraction of the first frequency. A stop clock signal is generated upon the condition that the bus fraction register contains the stop clock encoding. A bus unit busy (BBSY) signal line is polled to ensure that all pending bus cycles in the pipeline are completed, the polling being initiated in response to the stop clock signal. A special cycle encoded to indicate the stop clock function is run to inform the units of the microprocessor that the internal and I/O clocks are going to stop toggling.

Abstract: Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical serial bus assembly for the bus controller to dynamically detect and manage the interconnection topology of the serial bus elements. The serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic support an hierarchical view of the serial bus elements, logically dividing the hierarchy into multiple tiers. This logical view of the serial bus elements is used by the bus controller to detect the presence of interconnected serial bus elements and the functions of the bus agents, i.e.

Abstract: The present invention constructs SCSI device support code so that it can be ported to multiple operating system environments. The present invention also allows support for a device to be coded only once, and yet be supported on multiple operating system environments. Accordingly, a method and system for supporting a plurality of devices utilized with a data processing system is disclosed. This method and system allows for a plurality of devices to be utilized on a plurality of operating system platforms. The method and system comprises receiving a request from a user for a particular device, formatting the request into at least one common packet and then providing the at least one common packet to each of the plurality of operating system platforms. In so doing, any of the plurality of operating system platforms can utilize the at least one common packet to provide a device driver for the particular device.

Abstract: A procedure for the optimal processing of variable-cost actions such as encountered in the storage reclamation procedures for a multivolume data library. The procedure introduces a temporary processing queue to minimize idle processing capacity during the scanning and sorting of a large plurality of variable-cost actions such as the recycling of a plurality of data storage volumes each having a variable recycle processing cost related to the action of valid data remaining on the volume. Volumes (actions) are selected for the immediate queue according to a dynamically-adjusted threshold test for the processing cost. This processing cost threshold is dynamically adjusted to optimize the immediate queue in relation to the available processing capacity. After scanning and sorting all volumes according to recycle processing cost, the temporary (immediate) queue is updated to a final recycle processing queue by appending a sorted deferred queue to the remainder of the immediate queue.

Abstract: An expandable local area hub network is provided by the present invention. The network comprises a plurality of hubs coupled along a memory bus. The network further includes a segment switch coupling the plurality of hubs to a first segment arbiter and a second segment arbiter to associate the plurality of hubs with the first segment arbiter and the second segment arbiter to form separate and distinct system units. In use, the first segment arbiter grants a hub controlling access to a first segment memory bus for transmission of a packet on the first segment memory bus based upon an internal protocol and the second segment arbiter grants a hub controlling access to a second segment memory bus for transmission of a packet on the second segment memory bus based upon an internal protocol.

Abstract: The present invention discloses a method and apparatus for retrieval of information from a remote computer by a PC equipped with a facsimile modem where the PC initiates the communication. The method and apparatus in a preferred embodiment take advantage of the standard fields associated with facsimile transmission for exchange of information. The invention also provides a simple arrangement for changing the transmit mode of a facsimile modem to a receive mode.

Abstract: A system providing a multiple number of virtual channels in a computer system having a smaller number of physical channels. Multiple queues are provided that are mapped to channels. The mapping of the queues to the channels changes depending on the message traffic and priority of the queues. Queues of lower priority are preempted if a higher priority queue needs a channel.

Abstract: A data distribution system has a number of data processing devices interconnected by data transmission media. At least one of the data processing devices transmit data to other data processing devices in the system. The transmitting data processing system includes memory for storing the data to be transmitted, programmable data processing circuitry, and data transmission apparatus for transmitting an encoded representation of the stored message as a sequence of data packets. Priority data, stored in the memory, represents a plurality of assigned priority levels for specified portions of the stored message such that portions of the stored message have respective assigned priority levels. A data encoding program generates an encoded representation of the stored message that includes, for each portion of the stored message, a level of redundant data corresponding to the priority level assigned to that portion of the stored message.

Abstract: An apparatus for interfacing a plurality of nodes to a network includes a plurality of working ports coupled to the nodes, an attachment port coupled to the network, an address table for storing addresses associated with the working ports, an incoming packet controller, and an outgoing packet controller. The incoming packet controller receives an incoming information packet from the network via the attachment port, and determines whether a destination address contained in the incoming packet matches one of the addresses stored in the address table. If a destination address match is found, then it is concluded that the incoming packet is intended for one of the working ports. Consequently, the incoming packet is sent to the working ports. If no destination address match is found, the incoming packet controller prevents the packet from being sent to the working ports, thereby eliminating unnecessary signal traffic to the ports.

Abstract: In a video conferencing system including stations at a plurality of different sites, and in which system first and second video channels are simultaneously displayed at each site station on a picture-in-picture video monitor, a site controller causes a video decoder at the site to decode either a video signal generated at the site or a video signal received from another site via the first video channel. The site controller also responds to a channel assignment signal generated by a system controller by assigning the first video channel to either a first predetermined broadcast frequency or to a second predetermined broadcast frequency and by assigning a second video channel carrying a video signal received from another site to the other of the first and second predetermined broadcast frequencies.

Abstract: An imaging system having an image sensor which is read out as a plurality of parallel image signals. A plurality of parallel image signal processing channels are provided to process said plurality of image signals. Each channel includes a programmable I/O station for receiving, storing, and transmitting data used in controlling the channel. A closed loop serial I/O transmission link serially connects the programmable I/O stations. A controller is connected to the link to control the transmission of data to one or more of said plurality of programmable I/O stations.