Abstract: A data reproduction apparatus comprising: a storage unit for storing element data, and the management data including index data dividing the element data into first and second data groups and channel data indicating a first-data-group reproduction order; a management data readout and save unit for reading out and saving the management data; a first-data-group-readout first direction unit for outputting a first readout direction for the first-data-group element data as per the channel data; an input manipulation unit for accepting instruction input to select a reproduction channel of the first-data-group element data; a first-data-group-readout second direction unit for outputting a second readout direction for the first-data-group element data as per the channel data; a first-data-group readout unit for reading out the element data as per either the first or second readout direction; a first-data-group reproduction unit for converting the readout element data into reproduction data; a first-data-group output

Abstract: An automatic addressing technique for flexibly specifying the individual physical addresses of a plurality of devices coupled to an information bus. An anchor pattern is applied to an address bus of a plurality of address taps sufficient to uniquely specify the numbered J of devices to be attached thereto. Each device is connected to a tap on the address bus, each tap having the same number of bits. A plurality of address transform elements are serially connected to the bus, each transform element being located between adjacent tap positions. Each transform element converts the address pattern coupled to its input to another pattern capable of uniquely specifying the next address in the desired sequence. A wide variety of address sequences are available for selection, with each particular address sequence automatically determined by the related specific anchor pattern.

Abstract: A mainframe computer programmed to convert input data sets and build HSG or ISO-9660 Compact Disc (CD) images communicates with a channel attached controller that is in turn attached to one or more writers of respective Writable Compact Discs (CD-Ws). The images generated through batch processing in the mainframe computer are cached on the writers both so as to increase the speed of CD-W generation. Both subsequent labeling, and distribution of the CD-Ws to remotely-situated end users who view the CD-W images on PCs, are automated under positive closed loop feedback, control.

Abstract: A hard disk controller integrated circuit of a SCSI target device comprises a sequencer which causes a SCSI bus to transition from a command bus phase to a data transfer bus phase during execution of an autoread or an autowrite SCSI command without waiting for a communication from a microprocessor of the SCSI target device. In some embodiments, the command is determined to be either an autotransfer command or a non-autotransfer command. If the command is a non-autotransfer command, then the sequencer does not proceed directly to the data transfer phase but rather requires microprocessor intervention before proceeding to the data transfer phase. In some embodiments, an autotransfer command (such as an autoread or an autowrite command) is carried out by the disk drive controller integrated circuit with only two interrupts being generated to the microprocessor: one after receiving the autotransfer command from the initiator; and one after data transfer of the autotransfer command is complete.

Abstract: Apparatus and accompanying methods for use preferably in a multi-system shared data (sysplex) environment (100), wherein each system (110) provides one or more servers (115), for dynamically and adaptively assigning and balancing new work and for new session requests, among the servers in the sysplex, in view of attendant user-defined business importance of these requests and available sysplex resource capacity so as to meet overall business goals. Specifically, systems and servers are categorized into two classes: eligible, i.e., goal-oriented servers running under a policy and for which capacity information is currently available, and candidate, i.e., servers which lack capacity information.

Abstract: An interconnection network comprises a pair of backplanes for receiving X pluggable node cards. The pair of backplanes include X backplane connector groups, each backplane connector group adapted to receive mating connectors from a pluggable node card. Each backplane connector group includes X/2 connectors. A first backplane includes first permanent wiring which interconnects a first subset of pairs of connectors between backplane connector groups. A second backplane includes second permanent wiring which interconnects a second subset of pairs of connectors between backplane connector groups. The first permanent wiring and second permanent wiring connect complementary subsets' of pairs of the connectors. A plurality of node cards, each including a card connector group, pluggably mate with the backplane connector groups. Each node card further includes a frontal connector that is adapted to receive a cable interconnection.

Abstract: A scalable software architecture, for optimal performance on a RAID level 1, 3, 4 and 5 disk array or tape array. The software architecture consists of a software device driver and one or more driver daemon processes to control I/O requests to the arrays. Implemented in a UNIX or NetWare operating environment, this architecture provides a transparent interface to the kernels I/O subsystem, physical device drivers and system applications. The array driver and I/O daemon can be run on a uni-processor or multi-processor system platform to optimize job control, error recovery, data recreation, parity generation and asynchronous writes.

Abstract: A plurality of higher-level units are connected to a library unit, for example, as a lower-level unit through an SCSI. Furthermore, the plurality of higher-level units are connected by means of a communication path to mutually exchange information regarding the status of use of SCSI for the access to the lower-level library unit. A monitoring control section is provided in each of the plurality of higher-level units to instruct necessary processing in response to the status of use of SCSI. Particularly, when an abnormal occupation of SCSI caused by hang-up of any other higher-level unit is detected by the monitoring control section of a higher-level unit, the higher-level unit instructs its own SCSI controller to reset the bus to achieve bus reset of the other SCSI controller, thus releasing the occupation.

Abstract: A direct memory access controller is provided that performs DMA transfers by executing both a memory access cycle and an I/O access cycle. During the memory access cycle, the address location of system memory to be accessed is driven on the addressing lines of a local bus. During the I/O access cycle, an address value within a DMA configuration address range is driven on the address lines of the local bus. The DMA configuration address range is the range of address values to which the configuration registers of the DMA controller are mapped for receiving initialization data. Accordingly, other peripheral devices that may be connected to the local bus will not respond to the I/O access cycle. An address disable signal is further not required to disable the address decoders of other I/O peripheral devices not involved in the DMA transfer.

Abstract: The present invention provides a computer network having a plurality of nodes which can communicate with each other over the network. Of the total number of nodes, a set of them are programmed to communicate via a first or a second protocol, whilst at least one node is programmed such that it can only communicate via the first protocol and not the second protocol. Each node in the set comprises a receiving means, responsive to input from the plurality of nodes in the network, for registering the `states` of the software levels on those nodes; these states are stored in a storage device within the node. Further each node in the set has an indication means for producing an output signal indicating its own state, this output signal being transparent to the at least one node that can only communicate via the first protocol.