Abstract: An electronic device is provided, which includes a window including a transparent area and an opaque area; a panel disposed below the transparent area and including multiple pixels; a substrate disposed below the panel; an optical adhesive member disposed between the window and the panel; and a filler member disposed in at least a portion of a space formed between the opaque area and the substrate. The filler member transmits a light of a designated band, which is for curing the optical adhesive member, to a portion of the optical adhesive member disposed below the opaque area through a separation space between the filler member and the portion of the optical adhesive member.

Abstract: Group III nitride based light emitting diode (LED) structures include multiple quantum wells with barrier-well units that include Ill nitride interface layers. Each interface layer may have a thickness of no greater than about 30% of an adjacent well layer, and a comparatively low concentration of indium or aluminum. One or more interface layers may be present in a barrier-well unit. Multiple barrier-well units having different properties may be provided in a single active region.

Abstract: The invention discloses a transistor, a three dimensional memory device including such transistors and a method of fabricating such memory device. The transistor according to the invention includes a pillar of a semiconductor material, extending in a normal direction of a semiconductor substrate, a gate dielectric layer and a gate conductor. The pillar of the semiconductor material has a base side face parallel to the normal direction, a tapered side face opposite to the base side face, a top face perpendicular to the normal direction, a bottom face opposite to the top face, a front side face adjacent to the base side face and the tapered side face, and a rear side face opposite to the front side face. A first elongated portion, sandwiched among the base side face, the front side face, the bottom face and the top face, forms a source region. A second elongated portion, sandwiched among the base side face, the rear side face, the bottom face and the top face, forms a drain region.

Abstract: An electronic device includes a package structure with opposite first and second sides spaced apart along a first direction, opposite third and fourth sides spaced apart along a second direction, opposite fifth and sixth sides spaced apart along a third direction, the first, second, and third directions being orthogonal to one another. A set of first leads extend outward from the first side along the first direction, a set of second leads extend outward from the second side along the first direction, and a thermal pad includes a first portion that extends along a portion of the fifth side, and a second portion that extends along a portion of the third side to facilitate cooling and visual solder inspection when soldered to a host printed circuit board.

Abstract: An object of the present invention is to improve manufacturing efficiency of a semiconductor device. The method of manufacturing a semiconductor device includes a sealing step of sealing a semiconductor chip mounted on the wiring substrate. The sealing step includes a step of arranging the wiring substrate between an upper mold and a lower mold, suctioning a lower surface of the wiring substrate with the plurality of suction holes, thereby holding the wiring substrate the upper mold, and a step of sealing the semiconductor chip, an upper surface of the wiring substrate, and the plurality of side surfaces of the wiring substrate such that each of the semiconductor chip, the upper surface of the wiring substrate, and the plurality of side surfaces of the wiring substrate is covered with the resin in the lower mold.

Abstract: A gate structure is formed over a substrate. The gate structure includes a gate electrode and a hard mask located over the gate electrode. The hard mask comprises a first dielectric material. A first interlayer dielectric (ILD) is formed over the gate structure. The first ILD comprises a second dielectric material different from the first dielectric material. A first via is formed in the first ILD. Sidewalls of the first via are surrounded by spacers that comprise the first dielectric material. A second ILD is formed over the first ILD. A via hole is formed in the second ILD. The via hole exposes the first via. A protective layer is formed in the via hole. A bottom segment of the protective layer is removed. Thereafter, an etching process is performed. A remaining segment of the protective layer prevents an etching of the spacers during the etching process.

Abstract: This work develops a novel microfluidic method to fabricate conductive graphene-based 3D micro-electronic circuits on any solid substrate including, Teflon, Delrin, silicon wafer, glass, metal or biodegradable/non-biodegradable polymer-based, 3D microstructured, flexible films. It was demonstrated that this novel method can be universally applied to many different natural or synthetic polymer-based films or any other solid substrates with proper pattern to create graphene-based conductive electronic circuits. This approach also enables fabrication of 3D circuits of flexible electronic films or solid substrates. It is a green process preventing the need for expensive and harsh postprocessing requirements for other fabrication methods such as ink-jet printing or photolithography. We reported that it is possible to fill the pattern channels with different dimensions as low as 10×10 ?m. The graphene nanoplatelet solution with a concentration of 60 mg/mL in 70% ethanol, pre-annealed at 75° C. for 3 h, provided ˜0.

Abstract: A method includes patterning an interconnect trench in a dielectric layer. The interconnect trench has sidewalk and a bottom surface. A liner layer is deposited on the sidewalls and the bottom surface of the interconnect trench. The interconnect trench is filled with a first conductive metal material. The conducting metal material is recessed to below a top surface of the dielectric layer. A cap layer is deposited on a top surface of the first conductive metal material. The cap layer and the liner layer are of the same material. The method further includes forming a via on a portion of the interconnect trench.

Abstract: A semiconductor device including a source/drain region having a V-shaped bottom surface and extending below gate spacers adjacent a gate stack and a method of forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a fin; forming a gate spacer on a sidewall of the gate stack; etching the fin with a first anisotropic etch process to form a first recess adjacent the gate spacer; etching the fin with a second etch process using etchants different from the first etch process to remove an etching residue from the first recess; etching surfaces of the first recess with a third anisotropic etch process using etchants different from the first etch process to form a second recess extending below the gate spacer and having a V-shaped bottom surface; and epitaxially forming a source/drain region in the second recess.

Abstract: A semiconductor device according to an exemplary embodiment of the present disclosure includes: an n? type layer disposed in a first surface of a substrate; an n type layer disposed on the n? type layer; a first electrode disposed on the n type layer, and a second electrode disposed in a second surface of the substrate, wherein an energy band gap of the n? type layer is larger than an energy band gap of the n type layer.

Abstract: Provided herein are methods of filling gaps using high density plasma chemical vapor deposition (HDP CVD). According to various implementations, carbon-containing films such as amorphous carbon and amorphous carbide films are deposited by HDP CVD into gaps on substrates to fill the gaps. The methods may involve using high hydrogen-content process gasses during HDP CVD deposition to provide bottom-up fill. Also provided are related apparatus.

Abstract: Example embodiments of systems and methods for creating a chip fraud prevention system with a fraud prevention fluid are provided. A chip fraud prevention system includes a device including a chip. The chip may be at least partially encompassed in a chip pocket which contains a fraud prevention fluid. The fraud prevention fluid may be contained in a capsule or implemented as an adhesive. One or more connections may be communicatively coupled to at least one surface of the chip. The one or more connections may be placed in close proximity and/or in contact to the fraud prevention fluid.

Abstract: A semiconductor memory device comprising a strained semiconductor layer and a contact etch stop layer, CESL, wherein the strained semiconductor layer and the CESL are both arranged to reduce the probability of an electron tunnelling out of a charge trapping layer of the semiconductor memory device.

Abstract: A light emitting device is provided. The light emitting device includes a light emitting element, which emits blue light, and a light transmissive member having a first principal face bonded to the light emitting element and a second principal face opposite the first principal face. The light transmissive member has a light transmissive base material and wavelength conversion substances, which are contained in the base material and which absorb the light from the light emitting element and emit light. The wavelength conversion substances are localized in the base material towards the first principal face, and include a first phosphor which emits green to yellow light and a second phosphor which emits red light. The first phosphor is more localized towards the first principal face than the second phosphor. The second phosphor is a manganese-activated fluoride phosphor.

Abstract: A MOSFET includes a substrate, a trench, a bottom oxide, a shield poly, two gate polys and an inter-poly oxide. The trench is formed on the substrate. The bottom oxide is formed on the trench. The shield poly is formed on the trench, and a part of the bottom oxide is separated by the shield poly. The two gate polys are formed on the bottom oxide. The inter-poly oxide is formed between the two gate polys. The shield poly is staggered from at least one of the two gate polys in a horizontal direction and a vertical direction. Therefore, the capacitance between a source electrode and a gate electrode is effectively reduced, and the delay time during switching is shorten and the energy loss is reduced at the same time.

Abstract: Discussed is an electroluminescent display device, wherein a first electrode of a first sub pixel includes a first lower electrode and a first upper electrode, a first electrode of a second sub pixel includes a second lower electrode and a second upper electrode, a first electrode of a third sub pixel includes a third lower electrode and a third upper electrode, a distance between the first lower electrode and the first upper electrode, a distance between the second lower electrode and the second upper electrode, and a distance between the third lower electrode and the third upper electrode are different from one another, the third upper electrode includes a third lower layer and a third upper layer, and the third lower layer is formed in the same pattern as that of the third lower electrode in an upper surface of the third lower electrode.

Abstract: Embodiments are directed to a method and resulting structures for a semiconductor device having reduced parasitic capacitance. A semiconductor fin is formed on a substrate. A first bottom spacer is formed on a surface of the substrate and a sidewall of the semiconductor fin. A sacrificial spacer is formed over a channel region of the semiconductor fin and a portion of the first bottom spacer. A second bottom spacer is formed on a surface of the first bottom spacer and adjacent to the sacrificial spacer. The sacrificial spacer is removed and a conductive gate is formed over the channel region of the semiconductor fin.

Abstract: A semiconductor device includes a semiconductor substrate with a collector region formed within the semiconductor substrate. A base region, including a first base region and a second base region, is formed over the collector region. An extrinsic base region is formed laterally adjacent to and coupled to the second base region. A base link region is disposed proximate to the second base region, wherein the base link region couples the extrinsic base sidewall to the second base region. A method for forming a semiconductor device includes forming the collector region within the semiconductor substrate, forming a plurality of dielectric layers over the collector region, forming an extrinsic base layer over the collector region, etching an emitter window, forming the first base region over the collector region, forming the second base region over the first base region, wherein forming the second base region includes forming the base link region.

Abstract: The present disclosure provides a semiconductor structure and a method for preparing the semiconductor structure. The semiconductor structure includes a substrate; a drain disposed in the substrate; a drain contact disposed in the drain; a source disposed in the substrate; a source contact disposed in the source; a gate structure with a bottom disposed in the substrate between the drain and the source; a channel disposed at the bottom of the gate structure connecting the drain and the source; a drain stressor disposed in the drain between the gate structure and the drain contact; a drain strained silicon layer disposed in the substrate surrounding the drain stressor connected to the channel; a source stressor disposed in the source between the source contact and the gate structure; and a source strained silicon layer disposed in the substrate surrounding the source stressor connected to the channel.

Abstract: Example sensor apparatus for microfluidic devices and related methods are disclosed. In examples disclosed herein, a method of fabricating a sensor apparatus for a microfluidic device includes etching a portion of an intermediate layer to form a sensor chamber in a substrate assembly, where the substrate assembly has a base layer and the intermediate layer, and where the base layer comprises a first material and the intermediate layer comprises a second material different than the first material. The method includes forming a first electrode and a second electrode in the sensor chamber. The method also includes forming a fluidic transport channel in fluid communication with the sensor chamber, where the fluidic transport channel comprises a third material different than the first material and the second material.