Abstract: Disclosed is a method for forming a dual damascene pattern. The method includes the steps of forming a lower conductive structure on a lower insulating layer, forming a first protective film, a first insulating film, a second insulating film, a third insulating film, and a second protective film, sequentially, on the lower insulating layer and the lower conductive structure, forming a via hole up to a predetermined depth of the second insulating film through the second protective film and the third insulating film, forming a trench up to the predetermined depth of the second insulating film through the second protective film and the third insulating film, and simultaneously, extending the via hole up to a point at which the first protective film is exposed, and selectively etching the first protective film exposed through the via hole to expose the lower conductive pattern and form the dual damascene pattern.

Abstract: A leadframe for multi-chip package (MCP) including a die pad and a plurality of leads. A dielectric layer is formed on the lower surface of the die pad, so that the die pad is etched to form an interconnecting conductor with a bonding region. An insulation layer is formed on the interconnecting conductor and exposes the bonding region, so that a chip or a passive component can be electrically connected to the leads via the interconnecting conductor.

Abstract: A method is described for characterizing defects on a test surface of a semiconductor wafer using a confocal-microscope-based automatic defect characterization (ADC) system. The surface to be tested and a reference surface are scanned using a confocal microscope to obtain three-dimensional images of the test and reference surfaces. The test and reference images are converted into sets of geometric constructs, or “primitives,” that are used to approximate features of the images. Next, the sets of test and reference primitives are compared to determine whether the set of test primitives is different from the set of reference primitives. If such a difference exists, then the difference data is used to generate defect parameters, which are then compared to a knowledge base of defect reference data. Based on this comparison, the ADC system characterizes the defect and estimates a degree of confidence in the characterization.

Abstract: There is here disclosed a semiconductor device manufacturing method, comprising arranging at least one subject piece in a processing chamber, and starting a predetermined processing, applying a light having a predetermined wavelength to a monitoring section which is formed to enable transmission and reflection of the light and which is provided at a tip of a monitoring device to indirectly monitor a thickness of a film on the subject piece, and measuring a reflection light which is the application light is reflected near the monitoring section, while the light and the reflection light are isolated from an atmosphere and a substance in the chamber, measuring an amount of a substance on the monitoring section based on the reflection light, determining a thickness of a film on the subject piece based on the substance, and conducting the processing while controlling the processing based on the thickness of the film.

Abstract: Disclosed is a method of in-wafer testing of integrated optical components and in-wafer chips with photonic integrated circuits (PICs).

Abstract: Techniques for identifying, locating, detecting, and reviewing voltage contrast defects are described. A system for implementing the present invention includes a charged particle beam defect review system with one or more installed electron flood guns. In order to review a semiconductor specimen, an entire semiconductor wafer or a sub-region of a wafer is flooded with electrons from the flood gun(s) so that the wafer surface is charged to a certain voltage level. Flooding the specimen greatly enhances the effect of voltage contrast review techniques and therefore manifests voltage contrast defects that would not appear otherwise. The inventive techniques can also be applied so that a review system can be used to inspect at least a portion of a semiconductor wafer. Techniques for controlling the amount of negative charge applied to the specimen are also described.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes embedding and forming a coupling terminal as an external electrode of an electronic circuit on an active surface side of a substrate having an active surface formed with a plurality of electronic circuits, exposing a part of the coupling terminal by polishing a back surface side of the substrate, mounting a semiconductor chip on the back surface side of the substrate via the coupling terminal, sealing the semiconductor chip mounted on the substrate by a sealing material, and cutting the substrate for every forming area of each electronic circuit and dividing it into a plurality of semiconductor devices.

Abstract: A solid state electronically steerable antenna can be generated from a sheet of semiconductor material by forming a pattern of localised plasma regions in the sheet, either by injecting carriers into, or by generating carriers in, those localised regions. A suitable solid state plasma antenna can be made from a silicon wafer (10) by first thermally oxidising the surfaces and subjecting the wafer (10) to a high temperature stabilisation process to improve the stoichiometry at the silicon/silica interface, and optionally also performing a low-temperature bake in a gas mixture including hydrogen. This produces a wafer (10) with a long minority carrier lifetime. Regions of the wafer (10) in which plasma may be generated are then defined by reticulation to form isolated regions with high minority carrier lifetime. The resulting discrete regions may be of a size less than 1 mm, for example 0.3 mm.

Abstract: The present invention relates to a method for flip chip bonding by utilizing an interposer with embedded bumps. The method comprises (a) providing a first element having a first surface; (b) forming an interposer onto the first surface; (c) forming a plurality of openings on the interposer; (d) forming a plurality of bumps in the openings, wherein the height of the bumps is smaller than the depth of the openings; (e) providing a second element having a plurality of pre-solders; and (f) bonding the first surface onto the second element, so that the pre-solders are disposed in the openings and in contact with the bumps. As a result, the self-alignment between the pre-solders and the bumps can avoid the shift between the first element and the second element.

Abstract: In one embodiment of the present invention, a method includes acquiring parameters for a desired feature of a semiconductor device; determining a data array using the parameters; and forming the desired feature using the data array. The desired feature in one embodiment may be a backside trench.

Abstract: A packaging method for integrated circuits comprising processes such as wafer grinding, wafer mount, wafer saw, die attach, etc., multiple singulated chips are each attached and assembled to leadframe unit, the leadframe unit is used as electrical out-connecting component for each chip, and the wire-bonding part of the chip is dispensed continuously with encapsulant material to seal, curing method is further applied to solidify the encapsulant, then saw or punching method is used to dice apart each chip accompanied with leadframe unit (singulation process), a ready-to-use integrated circuit is thus obtained, such manufacturing processes let the goals of easy-to-manufacture, fast production and lowered-production cost be easily achieved for the packaging and singulating processes.

Abstract: A method to deposit nucleation problem free ruthenium by ALD. The nucleation problem free, relatively smooth ruthenium ALD film is deposited by the use of plasma-enhanced ALD of ruthenium underlay for consequent thermal ruthenium ALD layer. In addition, oxygen or nitrogen plasma treatments of SiO2 or other dielectrics leads to uniform ALD ruthenium deposition. The method has application as a direct plating layer for a copper interconnect or metal gate structure for advanced CMOS devices.

Abstract: A method for manufacturing an electronic device for signal transmission includes winding a wire of at least one electronic element onto a winding portion of an inner terminal of a lead of a packaging casing, displacing the at least one electronic element away from the inner terminal to a side of the packaging casing that is distal to the inner terminal, immersing the winding portion of the inner terminal and the wire in a bath of molten solder, and removing the inner terminal and the wire from the bath of the molten solder so that the winding portion of the inner terminal forms a welded portion for reliably and electrically connecting the inner terminal to the wire. Preferably, electrical connection between the inner terminal and the wire is tested after the step of removing the inner terminal and the wire from the bath of the molten solder.

Abstract: A method of determining a work function of a metal to be used as a metal gate material provides a metal-on-silicon (MS) Schottky diode on a silicon substrate. The MS Schottky diode is formed by deposition of the metal in a single step deposition through a shadow mask that is secured on the silicon substrate.

Abstract: A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress of the region is changed by ion implanting. Therefore, compressive stress and tensile stress occur on the high stress layer. According the disclosed method, the high stress layer may simultaneously improve the characteristics of the transistors formed on the same wafer. Further, the mobility of the carriers of the device is enhanced.

Abstract: A combination composed from a form standard and a CSP is attached to flex circuitry. Solder paste is applied to first selected locations on the flex circuitry and adhesive is applied to second selected locations on the flex circuitry. The flex circuitry and the combination of the form standard and CSP are brought into proximity with each other. During solder reflow operation, a force is applied that tends to bring the combination and flex circuitry closer together. As the heat of solder reflow melts the contacts of the CSP, the combination collapses toward the flex circuitry displacing the adhesive as the solder paste and contacts merge into solder joints. In a preferred embodiment, the form standard will be devised of heat transference material, a metal, for example, such as copper would be preferred, to improve thermal performance. In other embodiments, the methods of the invention may be used to attach a CSP without a form standard to flex circuitry.

Abstract: A liquid crystal display device and a method of fabricating the same are disclosed in the present invention. More specifically, the method includes the steps forming a gate line on the first substrate sequentially forming a first insulating layer, an amorphous silicon layer, and a metal layer on the first substrate, patterning the metal layer to form a data line, forming a second insulating layer on the data line, patterning the second insulating layer and the amorphous silicon layer to form a passivation layer and an active layer, respectively, forming a pixel electrode at a pixel region defined by the gate and data lines, assembling the first substrate and the second substrate having a black matrix thereon, wherein the black matrix vertically overlaps at least one boundary line defined by different exposures during step-and-repeat exposure processes; and forming a liquid crystal layer between the first and second substrates.

Abstract: A method for forming dual gate electrodes using a damascene gate process is disclosed.

Abstract: A method of forming a shallow trench isolation device in order to prevent kick effects comprising a semiconductor structure having a patterned masking layer formed thereon. A shallow trench is formed in the semiconductor structure by using the patterned masking layer as a mask. A liner oxide layer and a doped dielectric layer are formed in sequence on the semiconductor structure to cover the surface of the shallow trench. A layer of oxide is formed on the semiconductor structure to fill the shallow trench. The dopants in the doped dielectric layer diffuse into the semiconductor structure surrounding the shallow trench to form an ion doped area, thereby increasing the threshold voltage caused by the recess on the corner structure in order to prevent the kick effect.

Abstract: A structure and method for measuring leakage current. The structure includes: a body formed in a semiconductor substrate; a dielectric layer on a top surface of the silicon body; and a conductive layer on a top surface of the dielectric layer, a first region of the dielectric layer having a first thickness and a second region of the dielectric layer between the conductive layer and the top surface of the body having a second thickness, the second thickness different from the first thickness. The method includes, providing two of the above structures having different areas of first and the same area of second or having different areas of second and the same area of first dielectric regions, measuring a current between the conductive layer and the body for each structure and calculating a gate tunneling leakage current based on the current measurements and dielectric layer areas of the two devices.