Abstract: A method includes performing an atomic layer deposition (ALD) process to form a dielectric layer on a wafer. The ALD process comprises an ALD cycle includes pulsing calypso ((SiCl3)2CH2), purging the calypso, pulsing ammonia, and purging the ammonia. The method further includes performing a wet anneal process on the dielectric layer, and performing a dry anneal process on the dielectric layer.

Abstract: In some embodiments a method comprises depositing a first silicon nitride layer on a top surface of a semiconductor wafer and forming one or more first gaps in the first silicon nitride layer. The one or more first gaps can relieve stress formed in the first silicon nitride layer. A first fill material is deposited on the first silicon nitride layer and the first silicon nitride layer is planarized. A second silicon nitride layer is deposited across the first silicon nitride layer and one or more second gaps are formed in the second silicon nitride layer. The one or more second gaps can relieve stress formed in the second silicon nitride layer. A second fill material is deposited across the second silicon nitride layer and the second silicon nitride layer is planarized.

Abstract: A long-lifetime light-emitting device is provided. The light-emitting apparatus includes a first light-emitting device and a first color conversion layer. The first color conversion layer contains a first substance. An EL layer of the first light-emitting device includes a first layer, a second layer, a third layer, a light-emitting layer, and a fourth layer in this order from the anode side. The first layer contains a first organic compound and a second organic compound. The second layer contains a third organic compound. The third layer contains a fourth organic compound. The light-emitting layer contains a fifth organic compound and a sixth organic compound. The fourth layer contains a seventh organic compound. The first organic compound is an organic compound having an electron accepting property to the second organic compound. The fifth organic compound is an emission center substance. The HOMO level of the second organic compound is higher than or equal to ?5.7 eV and lower than or equal to ?5.4 eV.

Abstract: A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, and a first conductive layer. The first insulating layer is provided over the semiconductor layer. The first conductive layer is provided over the first insulating layer. The semiconductor layer includes a first region that overlaps with the first conductive layer and the first insulating layer, a second region that does not overlap with the first conductive layer and overlaps with the first insulating layer, and a third region that overlaps with neither the first conductive layer nor the first insulating layer. The semiconductor layer contains a metal oxide. The second region and the third region contain a first element. The first element is one or more elements selected from boron, phosphorus, aluminum, and magnesium.

Abstract: A method includes forming an active region on a substrate, forming a sacrificial gate stack engaging the active region, measuring a gate length of the sacrificial gate stack at a height lower than a top surface of the active region, selecting an etching recipe based on the measured gate length of the sacrificial gate stack, etching the sacrificial gate stack with the etching recipe to form a gate trench, and forming a metal gate stack in the gate trench.

Abstract: A method includes forming a mask layer above a substrate. The substrate is patterned by using the mask layer as a mask to form a trench in the substrate. An isolation structure is formed in the trench, including feeding first precursors to the substrate. A bias is applied to the substrate after feeding the first precursors. With the bias turned on, second precursors are fed to the substrate. Feeding the first precursors, applying the bias, and feeding the second precursors are repeated.

Abstract: A semiconductor device includes a first active pattern extending lengthwise along a first direction and a second active pattern extending lengthwise along the first direction and spaced apart from the first active pattern in the first direction. The device also includes a field insulating film between the first active pattern and the second active pattern. An upper surface of the field insulating film is lower than or coplanar with upper surfaces of the first and second active patterns. The device further includes an element isolation structure in an isolation trench in the first active pattern and the field insulating film. An upper surface of the element isolation structure is higher than the upper surfaces of the first and second active patterns.

Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer, a gate structure, and a field plate. The second nitride semiconductor layer is formed on a first surface of the first nitride semiconductor layer. The gate structure is disposed on the second nitride semiconductor layer. The field plate includes a first portion and a second portion connected to the first portion. The first portion has a first surface substantially in parallel to the first surface of the first nitride semiconductor layer, and a second surface adjacent to the first surface of the first portion. The first surface of the first portion of the field plate and the second surface of the first portion of the field plate define a first angle of about 90°.

Abstract: A composition, comprising: a carbon backbone polymer; a first crosslinker; and a second crosslinker. The first crosslinker partially crosslinks the carbon backbone polymer at a temperature ranging from 100° C. to 170° C., and the second crosslinker crosslinks the carbon backbone polymer at a temperature ranging from 180° C. to 300° C. The first crosslinker is one or more selected from the group consisting of A-(OR)x, A-(NR)x, where A is a monomer, oligomer, or a second polymer having a molecular weight ranging from 100 to 20,000, R is an alkyl group, cycloalkyl group, cycloalkylepoxy group, or C3-C15 heterocyclic group, OR is an alkyloxy group, cycloalkyloxy group, carbonate group, alkylcarbonate group, alkyl carboxylate group, tosylate group, or mesylate group, NR is an alkylamide group or an alkylamino group, and x ranges from 2 to 1000. The second crosslinker is different from the first crosslinker.

Abstract: Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include depositing a silicon-containing material on the substrate. The silicon-containing material may extend within the one or more recessed features along the substrate and a seam or void may be defined by the silicon-containing material within at least one of the one or more recessed features along the substrate. The methods may also include treating the silicon-containing material with a hydrogen-containing gas, such as plasma effluents of the hydrogen-containing gas, which may cause a size of the seam or void to be reduced.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for controlling a photoresist (PR) trimming rate in the formation of the 3D memory devices are disclosed. In an example, a method includes forming a dielectric stack over a substrate, measuring a first distance between the first trimming mark and the PR layer along a first direction, and trimming the PR layer along the first direction. The method also includes etching the dielectric stack using the trimmed PR layer as an etch mask to form a staircase, forming a second trimming mark using the first trimming mark as an etch mask, measuring a second distance between the second trimming mark and the trimmed PR layer, comparing the first distance with the second distance to determine a difference between an actual PR trimming rate and an estimated PR trimming rate, and adjusting PR trimming parameters based on the difference.

Abstract: A method for manufacturing a semiconductor structure includes: forming a first diffusion film layer on a dielectric layer, a thickness of the first diffusion film layer being not less than a thickness of a doped layer; forming a hard mask on the first diffusion film layer; etching each film layer corresponding to a first region and a second region toward a substrate, until the first diffusion film layer corresponding to the first region is exposed; and next, removing a first metal oxide layer remaining on the dielectric layer corresponding to the second region. As a result of the presence of the doped layer, the hard mask corresponding to the second region has a relatively small thickness.

Abstract: A method includes etching a silicon layer in a wafer to form a first trench in a first device region and a second trench in a second device region, performing a pre-clean process on the silicon layer, performing a baking process on the wafer, and performing an epitaxy process to form a first silicon germanium region and a second silicon germanium region in the first trench and the second trench, respectively. The first silicon germanium region and the second silicon germanium region have a loading in a range between about 5 nm and about 30 nm.

Abstract: Semiconductor processing methods are described that include providing a substrate to a reaction chamber, where the substrate includes substrate trenches that have a top surface and a bottom surface. A deposition gas that includes a carbon-containing gas and a nitrogen-containing gas flows into a plasma excitation region of the reaction chamber. A deposition plasma having an electron temperature less than or about 4 eV is generated from the deposition gas. The methods further include depositing a carbon-containing layer on the top surface and the bottom surface of the substrate trenches, where the as-deposited carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1. Also described are semiconductor structures that include an as-deposited carbon-containing layer on the top and bottom surface of at least a first and second trench, where the carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1.

Abstract: A method includes removing a dummy gate stack to form a first trench between gate spacers, forming a replacement gate stack in the first trench, recessing the replacement gate stack to form a second trench between the gate spacers, selectively depositing a conductive capping layer in the second trench, forming a dielectric hard mask in the second trench and over the conductive capping layer, and etching the dielectric hard mask using an etching gas to form an opening in the dielectric hard mask. The replacement gate stack is revealed to the opening. The conductive capping layer is more resistant to the etching gas than the replacement gate stack. The method further comprises forming a gate contact plug over and contacting the conductive capping layer.

Abstract: A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.

Abstract: A manufacturing method of a device chip includes removing a film in regions corresponding to streets, forming a modified layer inside a wafer by irradiating a laser beam from the back surface side of the wafer along regions corresponding to the regions from which the film has been removed, and giving an external force to the wafer to divide the wafer into individual device chips. In film removal, the distance from an end part of the street in the width direction to the region from which the film is to be removed is set equal to or shorter than a predetermined upper limit value to cause formation of a step between a region in which a substrate is exposed and a region coated with the film at an outer edge part of the device chip when the wafer is divided into the individual device chips in the dividing step.

Abstract: A sacrificial sealing layer is formed on a high-? metal gate (HKMG) stack to suppress oxidants, e.g., oxygen and water, from impacting the metal gate stack, thus preserving the device EOT. The method integrated processes that include forming an interfacial layer on the substrate; forming a high-? metal oxide layer on the interfacial layer, the high-? metal oxide layer comprising a dipole region adjacent to the interfacial layer, the dipole region; depositing a capping layer on the high-? metal oxide layer; and forming a sacrificial sealing layer on the capping layer. The dipole region is formed by driving a dopant species, e.g., zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium (Ti), tantalum (Ta), zirconium (Zr), aluminum (Al), niobium (Nb), or mixtures thereof, of a dipole film into the high-? metal oxide layer to form a dipole region.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

Abstract: Group III nitride based light emitting diode (LED) structures include multiple quantum wells with barrier-well units that include III nitride interface layers. Each interface layer may have a thickness of no greater than about 30% of an adjacent well layer, and a comparatively low concentration of indium or aluminum. One or more interface layers may be present in a barrier-well unit. Multiple barrier-well units having different properties may be provided in a single active region.