Abstract: Example embodiments of systems and methods for creating a chip fraud prevention system with a fraud prevention fluid are provided. A chip fraud prevention system includes a device including a chip. The chip may be at least partially encompassed in a chip pocket which contains a fraud prevention fluid. The fraud prevention fluid may be contained in a capsule or implemented as an adhesive. One or more connections may be communicatively coupled to at least one surface of the chip. The one or more connections may be placed in close proximity and/or in contact to the fraud prevention fluid.

Abstract: Techniques are disclosed for providing an integrated circuit structure having NMOS transistors including an arsenic-doped interface layer between epitaxially grown source/drain regions and a channel region. The arsenic-doped interface layer may include, for example, arsenic-doped silicon (Si:As) having arsenic concentrations in a range of about 1E20 atoms per cm3 to about 5E21 atoms per cm3. The interface layer may have a relatively uniform thickness in a range of about 0.5 nm to full fill where the entire source/drain region is composed of the Si:As. In cases where the arsenic-doped interface layer only partially fills the source/drain regions, another n-type doped semiconductor material can fill remainder (e.g., phosphorus-doped III-V compound or silicon).

Abstract: Plasma atomic layer deposition (ALD) is optimized through modulation of the gas residence time during an excited species phase, wherein activated reactant is supplied such as from a plasma. Reduced residence time increases the quality of the deposited layer, such as reducing wet etch rates, increasing index of refraction and/or reducing impurities in the layer. For example, dielectric layers, particularly silicon nitride films, formed from such optimized plasma ALD processes have low levels of impurities remaining from the silicon precursor.

Abstract: A pixel arrangement structure and a display panel. The pixel arrangement structure includes a plurality of pixel units. Each of the pixel units includes at least one pixel group. Each pixel group comprises one first sub-pixel, one second sub-pixel, and two third sub-pixels. The first sub-pixel, the second sub-pixel, and the two third sub-pixels in the pixel group form a virtual quadrilateral. A longest edge of first sub-pixel is arranged to at least partially overlap a first side of the virtual quadrilateral. A longest edge of the second sub-pixel is arranged to at least partially overlap a second side of the virtual quadrilateral. The first edge and the second edge intersect with each other. The pixel arrangement structure increases a pixel density, namely, increases a number of pixels per inch in the display panel, thus a display resolution of the display panel is improved.

Abstract: A method of forming a semiconductor device includes the following operations. A substrate is provided with a device and an insulating layer disposed over the device. A silicon-containing heterocyclic compound precursor and a first oxygen-containing compound precursor are introduced to the substrate, so as to form a zeroth dielectric layer on the insulating layer. A zeroth metal layer is formed in the zeroth dielectric layer. A silicon-containing linear compound precursor and a second oxygen-containing compound precursor are introduced to the substrate to form a first dielectric layer on the zeroth dielectric layer. A first metal layer is formed in the first dielectric layer.

Abstract: Techniques are disclosed for integrating semiconductor oxide materials as alternate channel materials for n-channel devices in integrated circuits. The semiconductor oxide material may have a wider band gap than the band gap of silicon. Additionally or alternatively, the high mobility, wide band gap semiconductor oxide material may have a higher electron mobility than silicon. The use of such semiconductor oxide materials can provide improved NMOS channel performance in the form of less off-state leakage and, in some instances, improved electron mobility as compared to silicon NMOS channels.

Abstract: Methods for depositing an amorphous carbon layer on a substrate and for filling a substrate feature with an amorphous carbon gap fill are described. The method comprises performing a deposition cycle comprising: introducing a hydrocarbon source into a processing chamber; introducing a plasma initiating gas into the processing chamber; generating a plasma in the processing chamber at a temperature of greater than 600° C.; forming an amorphous carbon layer on a substrate with a deposition rate of greater than 200 nm/hr; and purging the processing chamber.

Abstract: A gate structure is formed over a substrate. The gate structure includes a gate electrode and a hard mask located over the gate electrode. The hard mask comprises a first dielectric material. A first interlayer dielectric (ILD) is formed over the gate structure. The first ILD comprises a second dielectric material different from the first dielectric material. A first via is formed in the first ILD. Sidewalls of the first via are surrounded by spacers that comprise the first dielectric material. A second ILD is formed over the first ILD. A via hole is formed in the second ILD. The via hole exposes the first via. A protective layer is formed in the via hole. A bottom segment of the protective layer is removed. Thereafter, an etching process is performed. A remaining segment of the protective layer prevents an etching of the spacers during the etching process.

Abstract: A method includes forming a dummy gate stack on a semiconductor fin, forming gate spacers on sidewalls of the dummy gate stack, forming a first inter-layer dielectric, with the gate spacers and the dummy gate stack being in the first inter-layer dielectric, removing the dummy gate stack to form a trench between the gate spacers, forming a replacement gate stack in the trench, and depositing a dielectric capping layer. A bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first inter-layer dielectric. A second inter-layer dielectric is deposited over the dielectric capping layer. A source/drain contact plug is formed and extends into the second inter-layer dielectric, the dielectric capping layer, and the first inter-layer dielectric.

Abstract: Methods for depositing a silicon-germanium film on a substrate are described. The method comprises exposing a substrate to a silicon precursor and a germanium precursor to form a conformal silicon-germanium film. The substrate comprises at least one film stack and at least one feature, the film stack comprising alternating layers of silicon and silicon-germanium. The silicon-germanium film has a conformality greater than 50%.

Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a dummy gate structure over a substrate, forming a first spacer on a sidewall of the dummy gate structure and a second spacer on the first spacer, forming a source/drain structure on the substrate, removing the second spacer, forming a dielectric structure over the source/drain structure, replacing the dummy gate structure with a metal gate structure and a capping structure on the metal gate structure, and forming an opening in the dielectric structure. The opening exposes the source/drain structure. The method further includes forming a dummy spacer on a sidewall of the opening, forming a contact structure in the opening, and removing the dummy spacer to form an air gap between the contact structure and the metal gate structure. The contact structure is in contact with the source/drain structure in the opening.

Abstract: A method includes forming an adhesive layer over a carrier, forming a sacrificial layer over the adhesive layer, forming through-vias over the sacrificial layer, and placing a device die over the sacrificial layer. The Method further includes molding and planarizing the device die and the through-vias, de-bonding the carrier by removing the adhesive layer, and removing the sacrificial layer.

Abstract: A device includes a conductive feature, a first dielectric layer, a via, an etch stop layer, a second dielectric layer, and a conductive line. The first dielectric layer is above the conductive feature. The via is in the first dielectric layer and above the conductive feature. The etch stop layer is above the first dielectric layer. A side surface of the etch stop layer is coterminous with a sidewall of the via. The second dielectric layer is above the etch stop layer. The conductive line is in the second dielectric layer and over the via. The conductive line is in contact with the side surface of the etch stop layer and a top surface of the etch stop layer.

Abstract: A method of forming a semiconductor device includes forming a material layer over a substrate and forming a first trench in the material layer, forming a conformal capping layer along sidewalls of the first trench, forming a second trench in the material layer while the capping layer is disposed along sidewalls of the first trench and forming a conductive feature within the first trench and the second trench.

Abstract: Embodiments of the present disclosure generally relate to fabricating electronic devices, such as memory devices. In one or more embodiments, a method for forming a device includes forming a film stack on a substrate, where the film stack contains a plurality of alternating layers of oxide layers and nitride layers and has a stack thickness, and etching the film stack to a first depth to form a plurality of openings between a plurality of structures. The method includes depositing an etch protection liner containing amorphous-silicon on the sidewalls and the bottoms of the structures, removing the etch protection liner from at least the bottoms of the openings, forming a plurality of holes by etching the film stack in the openings to further extend each bottom of the openings to a second depth of the hole, and removing the etch protection liner from the sidewalls.

Abstract: A thin film forming method includes: a first operation of supplying a source gas at a first flow rate into a reactor; a second operation of purging the source gas in the reactor to an exhaust unit; a third operation of supplying a reactive gas at a second flow rate into the reactor; a fourth operation of supplying plasma into the reactor; and a fifth operation of purging the reactive gas in the reactor to the exhaust unit, wherein, during the second to fifth operations, the source gas is bypassed to the exhaust unit, and a flow rate of the source gas bypassed to the exhaust unit is less than the first flow rate. According to the thin film forming method, the consumption of the source gas and the reactive gas may be reduced, and the generation of reaction by-products in the exhaust unit may be minimized.

Abstract: In a method of manufacturing a semiconductor device, a sacrificial gate structure including sacrificial gate electrode is formed over a substrate. A first dielectric layer is formed over the sacrificial gate structure. A second dielectric layer is formed over the first dielectric layer. The second and first dielectric layers are planarized and recessed, and an upper portion of the sacrificial gate structure is exposed. A third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A fourth dielectric layer is formed over the third dielectric layer. The fourth and third dielectric layers are planarized, and the sacrificial gate electrode is exposed and part of the third dielectric layer remains on the recessed first dielectric layer. The recessing the first dielectric layer comprises a first etching operation and a second etching operation using a different etching as from the first etching operation.

Abstract: A method for forming a semiconductor device is provided. The method for forming a semiconductor device is provided. The method includes coating a photoresist film over a target layer; performing a lithography process to pattern the photoresist film into a photoresist layer; performing a directional ion bombardment process to the photoresist layer, such that a carbon atomic concentration in the photoresist layer is increased; and etching the target layer using the photoresist layer as an etch mask.

Abstract: A substrate structure of the memory, and a method for preparing the substrate structure of the memory are provided. The method includes: providing a substrate; forming a first mask layer on the substrate, the first mask layer including a plurality of strip patterns extending in a direction and spaced apart from each other; forming a first dielectric layer covering the first mask layer; forming a plurality of sacrificial portions spaced apart from each other in the first dielectric layer and covering a portion of the plurality of strip patterns; filling gaps between the sacrificial portions with a second dielectric material; forming a second mask layer by removing the sacrificial portions while retaining the second dielectric material in the gaps; and performing layer-by-layer etching into the substrate to form a plurality of active areas arranged in an array.

Abstract: A warpage-reducing semiconductor structure includes a wafer. The wafer includes a front side and a back side. Numerous semiconductor elements are disposed at the front side. A silicon oxide layer is disposed at the back side. A UV-transparent silicon nitride layer covers and contacts the silicon oxide layer. The refractive index of the UV-transparent silicon nitride layer is between 1.55 and 2.10.