Patents Examined by Andre? C. Stevenson
  • Patent number: 10672947
    Abstract: A metal layer is formed by vapor deposition or sputtering on an AlN substrate. Since there are irregularities on the surface of the substrate, irregularities are also formed on the surface of the metal layer. Subsequently, irregularities on the surface of the metal layer are removed and flattened in a mirror state by grinding the surface of the metal layer. Then, a dielectric layer is formed on the metal layer by alternately forming a SiO2 film and a TiO2 film through CVD. Next, an electrode layer is formed in a predetermined pattern by vapor deposition and lift-off on the dielectric layer. Since the surface of the metal layer is flattened in a mirror state, reflectance is high on that surface. As a result, the emission efficiency of the light-emitting device can be improved.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: June 2, 2020
    Assignee: TOYODA GOSEI CO., LTD
    Inventor: Shingo Totani
  • Patent number: 10658218
    Abstract: In a cutting method of a workpiece, a half-cut groove having a groove bottom that reflects light of an epi-illumination part is formed in a range of a peripheral surplus region of a planned dividing line that has not been cut, and the half-cut groove is detected with discrimination from a laser-processed groove that diffusely reflects the light and is darkly displayed.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: May 19, 2020
    Assignee: DISCO CORPORATION
    Inventors: Makoto Tanaka, Masanari An
  • Patent number: 10651218
    Abstract: An optical sensor structure is provided. The optical sensor structure includes a sensor pixel array in a substrate, a light collimating layer on the substrate, and at least one through-substrate via. The sensor pixel array has a plurality of sensor pixels. The at least one through-substrate via extends from a first surface to an opposite second surface of the substrate. The at least one through-substrate via is in the sensor pixel array and vertically misaligned with the plurality of sensor pixels.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: May 12, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Hsin-Hui Lee, Han-Liang Tseng, Hsueh-Jung Lin
  • Patent number: 10651047
    Abstract: In some embodiments, the disclosure relates to an integrated circuit structure. The integrated circuit structure has a substrate and a first hard mask layer over the substrate. An island of a second hard mask layer is arranged on the first hard mask layer and is set back from sidewalls of the first hard mask layer. A sacrificial mask is disposed over the island of the second hard mask layer. The sacrificial mask has sidewalls that define an opening exposing upper surfaces of the first hard mask layer and the island of the second hard mask layer. The island of the second hard mask layer extends from below the sacrificial mask to laterally past the sidewalls of the sacrificial mask.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Patent number: 10644167
    Abstract: A thin film transistor including a flexible substrate, a semiconductor layer, a first gate, and a first gate dielectric layer is provided. The semiconductor layer is located on the flexible substrate. The first gate is located on the flexible substrate and corresponds to a portion of the semiconductor layer. The first gate dielectric layer is located between the first gate and the semiconductor layer. The first gate dielectric layer is in contact with the semiconductor layer, and the hydrogen atom concentration of the first gate dielectric layer is less than 6.5×1020 atoms/cm3. A method of manufacturing the thin film transistor is also provided.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: May 5, 2020
    Assignees: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Tai-Jui Wang, Yung-Hui Yeh, Jui-Wen Yang, Hsiao-Chiang Yao, Chun-Hung Chu
  • Patent number: 10636658
    Abstract: Some embodiments include a method of forming a pattern. A first layer is formed to extend over a photoresist feature and along sidewalls of the photoresist feature. The first layer is etched to form first features. The photoresist feature is removed. A second layer is formed to extend over the first features and along sidewalls of the first features. The second layer is etched to form second features. A third layer is formed to extend over the first and second features and along sidewalls of the second features. A fourth layer is spin-coated over the third layer. A portion of the fourth layer is removed from over the first and second features. Segments of the third layer remain along the sidewalls of the second features. Regions of the fourth layer remain as blocks adjacent the segments. The first features and the segments are removed to leave the pattern.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: April 28, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Akira Muto
  • Patent number: 10636853
    Abstract: A method of manufacturing an OLED device includes: preparing a substrate on which a first conductive layer and a pixel defining film defining a plurality of pixels and exposing the first conductive layer for each of the plurality of pixels; disposing a photoresist pattern on the pixel defining film, the photoresist pattern comprising an opening exposing a first pixel of the plurality of pixels; disposing a first material layer onto an entire surface of the substrate to simultaneously dispose an organic light-emitting layer and a first deposition layer; disposing a second material layer onto the entire surface of the substrate to simultaneously dispose a second conductive layer and a second deposition layer; disposing a third material layer onto the entire surface of the substrate to simultaneously dispose a protection layer and a third deposition layer; and removing the photoresist pattern and the first, second, and third deposition layers.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: April 28, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Tae Wook Kang
  • Patent number: 10636762
    Abstract: A method of manufacturing a semiconductor device includes a step of preparing a semiconductor element including a functional surface on which a bump is formed and an adhesive layer of a film shape including a flux component, a step of positioning the semiconductor element above a board including an electrode, a step of activating a flux component by applying ultrasonic vibration to the semiconductor element, a step of bringing the bump into contact with the electrode by pressing the semiconductor element to the board, and a step of bonding the bump to the electrode by continuing the application of the ultrasonic vibration and the pressing of the semiconductor element.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: April 28, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takatoshi Ishikawa, Teppei Kojio
  • Patent number: 10629760
    Abstract: Methods of fabricating emitter regions of solar cells are described. Methods of forming layers on substrates of solar cells, and the resulting solar cells, are also described.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: April 21, 2020
    Assignee: SunPower Corporation
    Inventors: David D. Smith, Helen Liu, Tim Dennis, Jane Manning, Hsin-Chiao Luan, Ann Waldhauer, Genevieve A. Solomon, Brenda Pagulayan Malgapu, Joseph Ramirez
  • Patent number: 10629717
    Abstract: A high power device including with a first nitride semiconductor layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer, and a third nitride semiconductor layer containing an Al element formed on the second nitride semiconductor layer. The second nitride semiconductor layer is a multiple quantum well layer in which a nitride semiconductor layer containing an In element and a nitride semiconductor layer not containing an In element are alternately stacked.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 21, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Infrastructure Systems & Solutions Corporation
    Inventor: Kenichi Sugita
  • Patent number: 10619943
    Abstract: A composite sheet, including: a buffer sheet; and a heat dissipation sheet on one surface of the buffer sheet. One surface of the heat dissipation sheet facing the one surface of the buffer sheet may have a smaller area than the one surface of the buffer sheet. A display device includes a display panel and a composite sheet on one surface of the display panel.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: April 14, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Won Il Lee, Min Seop Kim
  • Patent number: 10622545
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic layer having a variable magnetization direction, a first non-magnetic layer provided on the first magnetic layer, and a second magnetic layer provided on the first magnetic layer and having a fixed magnetization direction and provided on the first magnetic layer. The second magnetic layer includes a non-magnetic metal including at least one of Mo (molybdenum), Ta (tantalum), W (tungsten), Hf (hafnium), Nb (niobium) and Ti (titanium).
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: April 14, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masaru Toko, Keiji Hosotani, Hisanori Aikawa, Tatsuya Kishi
  • Patent number: 10605769
    Abstract: A sensing device including a transistor, at least one response electrode, and a receptor is provided. The transistor includes a gate end, a source end, a drain end, and a semiconductor layer. The source end and the drain end are located on the semiconductor layer, and the gate end is located between the source end and the drain end. The at least one response electrode is disposed opposite to the gate end of the transistor and spaced apart from the transistor. The receptor is bonded onto the at least one response electrode. When a voltage is applied to the at least one response electrode, an electric field between the at least one response electrode and the gate end of the transistor is F, and F?1 mV/cm.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: March 31, 2020
    Assignee: National Tsing Hua University
    Inventors: Yu-Lin Wang, Yen-Wen Chen
  • Patent number: 10607843
    Abstract: According to one embodiment, there is provided a method of manufacturing a semiconductor device which includes forming an alignment mark in a planned cutting line region of a first surface of a semiconductor substrate, forming a stacked structure above the first surface of the semiconductor substrate, removing the portion of the stacked structure present above the alignment mark, aligning the substrate in the lithography process, by causing infrared light to pass through the semiconductor substrate from a second surface thereof which is on a side opposite to the first surface thereof and performing positional alignment for exposure of a resist pattern based on the location of the alignment mark using infrared light reflected from the alignment mark, and exposing the resist, opening a pattern in the exposed resist, and further processing the semiconductor substrate using the resist pattern.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: March 31, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya Watanabe, Keisuke Taira
  • Patent number: 10600860
    Abstract: A resistive material is formed straddling over each semiconductor fin that extends upward from a surface of a substrate. The resistive material is then disconnected by removing the resistive material from atop each semiconductor fin. Remaining resistive material in the form of a U-shaped resistive material liner is present between each semiconductor fin. Contact structures are formed perpendicular to each semiconductor fin and contacting a portion of a first set of the semiconductor fins and a first set of the U-shaped resistive material liners.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Shanti Pancharatnam, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10586738
    Abstract: A method for providing a semiconductor device and the device so formed are described. A doped semiconductor layer is deposited on a semiconductor underlayer. At least a portion of the semiconductor underlayer is exposed. A dopant for the doped semiconductor layer is selected from a p-type dopant and an n-type dopant. An ultraviolet-assisted low temperature (UVLT) anneal of the doped semiconductor layer is performed in an ambient. The ambient is selected from an oxidizing ambient and a nitriding ambient. The oxidizing ambient is used for the n-type dopant. The nitriding ambient is used for the p-type dopant. A sacrificial layer is formed by the doped semiconductor layer during the UVLT anneal. The dopant is driven into the portion of the semiconductor underlayer from the doped semiconductor layer by the UVLT anneal, thereby forming a doped semiconductor underlayer. The sacrificial layer is then removed.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: March 10, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wei-E Wang, Mark S. Rodder, Borna J. Obradovic, Joon Goo Hong
  • Patent number: 10586724
    Abstract: A method includes forming an adhesive layer over a carrier, forming a sacrificial layer over the adhesive layer, forming through-vias over the sacrificial layer, and placing a device die over the sacrificial layer. The Method further includes molding and planarizing the device die and the through-vias, de-bonding the carrier by removing the adhesive layer, and removing the sacrificial layer.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: March 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsiang Hu, Chung-Shi Liu, Hung-Jui Kou, Ming-Da Cheng
  • Patent number: 10586767
    Abstract: A method for fabricating semiconductor wafers comprises creating a semiconductor wafer having a plurality of wide copper wires and a plurality of narrow copper wires embedded in a dielectric insulator. The width of each wide copper wire is greater than a cutoff value and each narrow copper is less than the cutoff value. An optical pass through layer is deposited over a top surface of the wafer and a photo-resist layer is deposited over the optical pass through layer. The wafer is exposed to a light source to selectively remove photo-resist, forming a self-aligned pattern where photo-resist only remains in areas above wide copper wires. The self-aligned pattern is transferred to the optical pass through layer and the remaining photo-resist is removed. The wafer is chemically etched to remove the narrow copper wires, defining narrow gaps in the dielectric insulator. The wafer is metallized with non-copper metal, forming narrow non-copper metal wires.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Cornelius Brown Peethala, Michael Rizzolo, Koichi Motoyama, Gen Tsutsui, Ruqiang Bao, Gangadhara Raja Muthinti, Lawrence A. Clevenger
  • Patent number: 10586886
    Abstract: A micro-LED (3r) transfer method and a manufacturing method are disclosed. The micro-LED (3r) transfer method comprises: forming a sacrificial post (4) on a micro-LED (3r) to be picked-up on a carrier substrate (1); bonding the micro-LED (3r) to be picked-up with a pickup substrate (5) via the sacrificial post (4); lifting-off the micro-LED (3r) to be picked-up from the carrier substrate (1); bonding the micro-LED (3r) on the pickup substrate (5) with a receiving substrate (12); and lifting-off the micro-LED (3r) from the pickup substrate (5). A complicated pickup head is not necessary, and the technical solution is relatively simple.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: March 10, 2020
    Assignee: GOERTEK, INC.
    Inventor: Quanbo Zou
  • Patent number: 10580828
    Abstract: A method of manufacturing an integrated circuit system, includes, in part, providing a planar surface on an insulator, forming first and second bottom electrodes over the insulator substrate, forming a first electrolyte over the first and second bottom electrodes, forming a first top electrode over the first electrolyte, forming and depositing a second bottom electrode over the insulator substrate, patterning and removing the first top electrode and the first electrolyte from regions above the second bottom electrode, forming a second electrolyte above the second bottom electrode and the first tope electrode, forming a second top electrode above the second electrolyte, and patterning and removing the second top electrode and the second electrolyte from regions above the first bottom electrode.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: March 3, 2020
    Assignee: SYNOPSYS, INC.
    Inventor: Chung-Heng Yang