Abstract: Exemplary methods of forming a silicon-and-carbon-containing material may include flowing a silicon-oxygen-and-carbon-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber. The methods may include forming a plasma within the processing region of the silicon-and-carbon-containing precursor. The plasma may be formed at a frequency less than 15 MHz (e.g., 13.56 MHz). The methods may include depositing a silicon-and-carbon-containing material on the substrate. The silicon-and-carbon-containing material as-deposited may be characterized by a dielectric constant below or about 3.5 and a hardness greater than about 3 Gpa.

Abstract: Exemplary methods of forming a semiconductor structure may include forming a first silicon oxide layer overlying a semiconductor substrate. The methods may include forming a first silicon layer overlying the first silicon oxide layer. The methods may include forming a silicon nitride layer overlying the first silicon layer. The methods may include forming a second silicon layer overlying the silicon nitride layer. The methods may include forming a second silicon oxide layer overlying the second silicon layer. The methods may include removing the silicon nitride layer. The methods may include removing the first silicon layer and the second silicon layer. The methods may include forming a metal layer between and contacting each of the first silicon oxide layer and the second silicon oxide layer.

Abstract: A method includes depositing a dielectric cap over a gate structure. A source/drain contact is formed over a source/drain region adjacent to the gate structure. A top of the dielectric cap is oxidized. After oxidizing the top of the dielectric cap, an etch stop layer is deposited over the dielectric cap and an interlayer dielectric (ILD) layer over the etch stop layer. The ILD layer and the etch stop layer are etched to form a via opening extending though the ILD layer and the etch stop layer. A source/drain via is filled in the via opening.

Abstract: Provided are a method of depositing a thin film and a method of manufacturing a semiconductor device using the same, and the method of depositing a thin film uses a substrate processing apparatus including a chamber, a substrate support on which a substrate is mounted, a gas supply unit, and a power supply unit that supplies high-frequency and low-frequency power to the chamber, and includes: a step of mounting, on the substrate support, the substrate including a lower thin film deposited under the condition of a process temperature in a low temperature range; a step of depositing an upper thin film on the lower thin film under the condition of the process temperature in the low temperature range; and a step of treating a surface of the upper thin film under the condition of the process temperature in the low temperature range.

Abstract: A method for making a high-voltage thick gate oxide, which includes depositing a pad silicon oxide on a silicon substrate and depositing a pad silicon nitride on the pad silicon oxide; performing shallow trench isolation photolithography, etching, silicon oxide filling and chemical mechanical polishing; sequentially depositing a mask silicon nitride and a mask silicon oxide on a silicon wafer; removing the mask silicon oxide and the mask silicon nitride in a high-voltage thick gate oxide region, and remaining the pad silicon nitride between two shallow trench isolations in the high-voltage thick gate oxide region; performing first thermal oxidation growth; removing the pad silicon nitride between the two shallow trench isolations in the high-voltage thick gate oxide region; performing second thermal oxidation growth to produce a high-voltage thick gate oxide.

Abstract: A method for fabricating a layer structure having a target topology profile in a step which has a side face and a lateral face, includes processes of: (a) depositing a dielectric layer on a preselected area of the substrate under first deposition conditions, wherein the dielectric layer has a portion whose resistance to fluorine and/or chlorine radicals under first dry-etching conditions is tuned; and (b) exposing the dielectric layer obtained in process (a) to the fluorine and/or chlorine radicals under the first dry-etching conditions, thereby removing at least a part of the portion of the dielectric layer, thereby forming a layer structure having the target topology profile on the substrate.

Abstract: A method of fabricating a semiconductor device is disclosed. The method may include forming a parent pattern, forming an upper thin film on the parent pattern, forming a child pattern on the upper thin film, measuring a diffraction light from the parent and child patterns to obtain an intensity difference curve of the diffraction light versus its wavelength, and performing an overlay measurement process on the parent and child patterns using the diffraction light, which has the same wavelength as a peak of the intensity difference curve located near a peak of reflectance of the parent and child patterns, to obtain an overlay measurement value.

Abstract: An economical, efficient, and effective formation of a high resolution pattern of conductive material on a variety of films by polymer casting. This allows, for example, quite small-scale patterns with sufficient resolution for such things as effective microelectronics without complex systems or steps and with substantial control over the characteristics of the film. A final end product that includes that high resolution functional pattern on any of a variety of substrates, including flexible, stretchable, porous, biodegradable, and/or biocompatible. This allows, for example, highly beneficial options in design of high resolution conductive patterns for a wide variety of applications.

Abstract: A method of manufacturing a semiconductor structure includes: providing a base and a dielectric layer on the base, the base in an array region being provided with discrete capacitive contact plugs and a first conductive layer being formed on a top surface of the capacitive contact plugs; sequentially forming a conversion layer and a target layer on the first conductive layer and the dielectric layer, the target layer in the array region and the first circuit region being provided with first openings through the target layer; patterning the target layer in the array region as well as in the first circuit region and the second circuit region to form a second opening and a third opening; etching the conversion layer to form a first trench; forming a filling layer filling the first trench and removing the conversion layer to form a second trench filled by a second conductive layer.

Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.

Abstract: This work develops a novel microfluidic method to fabricate conductive graphene-based 3D micro-electronic circuits on any solid substrate including, Teflon, Delrin, silicon wafer, glass, metal or biodegradable/non-biodegradable polymer-based, 3D microstructured, flexible films. It was demonstrated that this novel method can be universally applied to many different natural or synthetic polymer-based films or any other solid substrates with proper pattern to create graphene-based conductive electronic circuits. This approach also enables fabrication of 3D circuits of flexible electronic films or solid substrates. It is a green process preventing the need for expensive and harsh postprocessing requirements for other fabrication methods such as ink-jet printing or photolithography. We reported that it is possible to fill the pattern channels with different dimensions as low as 10×10 ?m. The graphene nanoplatelet solution with a concentration of 60 mg/mL in 70% ethanol, pre-annealed at 75° C. for 3 h, provided ˜0.

Abstract: The present disclosure, in some embodiments, relates to an integrated circuit structure. The integrated circuit structure includes a substrate and a hard mask over the substrate. The hard mask has sidewalls that form a first opening and a second opening exposing an upper surface of the substrate. A block mask is arranged on the hard mask and is set back from the sidewalls of the hard mask. Spacers are disposed over the block mask and have sidewalls that define a spacer opening exposing an upper surface of the block mask. The block mask extends from directly below the spacers to laterally past the sidewalls of the spacers.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.

Abstract: A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

Abstract: A method comprises forming first and second fins each comprising alternately stacking first and second semiconductor layers; forming dummy gate structures over the first and second fins, and gate spacers on either side of the dummy gate structures; removing the dummy gate structures to form first and second gate trenches; removing the first semiconductor layers such that the second semiconductor layers are suspended in the first and second gate trenches; depositing a first dielectric layer around the second semiconductor layers and a second dielectric layer around the first dielectric layer; performing an ALD process to form a hard mask layer around the second dielectric layer, the ALD process comprising pulsing a first precursor for a first pulse time longer than about one second; patterning the hard mask layer; and etching a portion of the second gate dielectric layer in the second gate trench.

Abstract: A photodetector, includes a photosensitive layer, a thin film transistor, and a sensing electrode, the sensing electrode connected to one of source/drain electrodes of the thin film transistor to transmit a signal generated by the photosensitive layer to the thin film transistor; wherein the photodetector further is a hydrogen barrier layer which is disposed between the photosensitive layer and the thin film transistor and is configured to inhibit hydrogen of the photosensitive layer from entering the thin film transistor. A method of manufacturing a photodetector is further provided.

Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.

Abstract: A display panel is provided and includes a substrate and a plurality of pixel units. Each of the pixel units includes a color resist block, a light transmission area, and a non-light transmission area. An opening is defined at an edge of the color resist block in the non-light transmission area, and a through-hole area is defined in the opening. The opening includes a first sidewall near the light transmission area, a compensation member is disposed at an end of the first sidewall near a gap area, and a block angle structure is formed between the compensation member and the first sidewall.

Abstract: Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.

Abstract: Methods of forming carbon polymer films are disclosed. Some methods are advantageously performed at lower temperatures. The substrate is exposed to a first carbon precursor to form a substrate surface with terminations based on the reactive functional groups of the first carbon precursor and exposed to a second carbon precursor to react with the surface terminations and form a carbon polymer film. Processing tools and non-transitory memories to perform the process are also disclosed.