Patents Examined by Andre? C. Stevenson
  • Patent number: 11127857
    Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are provided. In embodiments a treatment process is utilized in order to introduce silicon into a p-metal work function layer. By introducing silicon into the p-metal work function layer, subsequently deposited layers which may comprise diffusable materials such as aluminum can be prevented from diffusing through the p-metal work function layer and affect the operation of the device.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Yi Lee, Da-Yuan Lee, Ching-Hwanq Su
  • Patent number: 11121142
    Abstract: A method of manufacturing a memory structure including the following steps is provided. A spacer layer is formed on sidewalls of gate stack structures. A protective material layer covering the spacer layer and the gate stack structures is formed. A mask material layer is formed on the protective material layer. There is a void located in the mask material layer between two adjacent gate stack structures. A first distance is between a top of the protective material layer and a top of the mask material layer. A second distance is between a top of the void and a top of the mask material layer above the void. A third distance is between a bottom of the void and a bottom of the mask material layer below the void. The first distance is greater than a sum of the second and third distances.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: September 14, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Che-Jui Hsu, Chun-Sheng Lu, Ying-Fu Tung, Chen-Wei Liao
  • Patent number: 11121304
    Abstract: A method of making a Josephson junction for a superconducting qubit includes providing a substructure having a surface with first and second trenches perpendicular to each other defined therein. The method further includes evaporating a first superconducting material to deposit the first superconducting material and evaporating a second superconducting material to deposit the second superconducting material in the first trench to provide a first lead, and forming an oxidized layer on the first and second superconducting materials. The method includes evaporating a third superconducting material at an angle substantially perpendicular to the surface of the substructure to deposit the third superconducting material in the second trench without rotating the substructure to form a second lead. A vertical Josephson junction is formed at the intersection of the first and second trenches electrically connected through the first lead and through the second lead.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Vivekananda P. Adiga, Benjamin B. Wymore, Keith Fogel, Martin O. Sandberg
  • Patent number: 11114394
    Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes an article having a substrate, a semiconductor die thereon, a routing carrier attached to the substrate, and a transmission pathway electrically connected to the semiconductor die and the substrate, wherein the transmission pathway runs through the routing carrier. In selected examples, the article is made by manufacturing a substrate, attaching a semiconductor die to the substrate, fabricating a routing carrier comprising a transmission pathway, and integrating the routing carrier into the substrate.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: September 7, 2021
    Assignee: Intel Corporation
    Inventors: Lijiang Wang, Jianyong Xie, Sujit Sharan, Robert L. Sankman
  • Patent number: 11107834
    Abstract: Embodiments of staircase and contact structures of a three-dimensional (3D) memory device and fabrication method thereof are disclosed. The 3D memory device includes a semiconductor substrate and a plurality of through-substrate-trenches penetrating the semiconductor substrate. The 3D memory device also includes a film stack disposed on a first surface of the semiconductor substrate extending through the through-substrate-trenches to a second surface of the semiconductor substrate, wherein the film stack includes alternating conductive and dielectric layers. The 3D memory device also includes a staircase structure formed at an edge of the film stack.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: August 31, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Li Hong Xiao
  • Patent number: 11101365
    Abstract: Example methods for fabricating a semiconductor device and example semiconductor devices are disclosed. An example method may include forming a sacrificial gate structure on a substrate, and the sacrificial gate structure may include a first portion and a second portion. The method may further include, removing the first portion of the sacrificial gate structure and forming an oxide film by oxidizing an upper surface of the second portion of the sacrificial gate structure after removing the first portion of the sacrificial gate structure. The method may additionally include, forming a trench on the substrate by removing the oxide film and the second portion of the sacrificial gate structure; and forming a gate electrode that fills the trench.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: August 24, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Cheon Jeong, YongKuk Jeong, Jin Hyuk Jeong, Tae Gyun Kim
  • Patent number: 11101409
    Abstract: The invention provides a lighting device configured to provide white lighting device light, the lighting device comprising (i) a light source, configured to provide blue light source light, and (ii) a luminescent material element, configured to absorb at least part of the blue light source light and to convert into luminescent material light, wherein the luminescent material element comprises a luminescent material which consists for at least 80 wt. % of a M2-2xEu2xSi5-yAlyOyN8-y phosphor, wherein M comprises one or more of Mg, Ca, Sr, Ba, with a molar ratio of (Mg+Ca+Sr)/(Ba)?0.1, wherein x is in the range of 0.001-0.02, wherein y is in the range of ?0.2, and wherein the white lighting device light comprises said blue light source light and said luminescent material light.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: August 24, 2021
    Inventors: Peter Josef Schmidt, Walter Mayr, Volker Weiler, Hans-Helmut Bechtel
  • Patent number: 11101269
    Abstract: A semiconductor device includes a first active pattern extending lengthwise along a first direction and a second active pattern extending lengthwise along the first direction and spaced apart from the first active pattern in the first direction. The device also includes a field insulating film between the first active pattern and the second active pattern. An upper surface of the field insulating film is lower than or coplanar with upper surfaces of the first and second active patterns. The device further includes an element isolation structure in an isolation trench in the first active pattern and the field insulating film. An upper surface of the element isolation structure is higher than the upper surfaces of the first and second active patterns.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: August 24, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang Min Yoo, Ju Youn Kim, Hyung Joo Na, Bong Seok Suh, Joo Ho Jung, Eui Chui Hwang, Sung Moon Lee
  • Patent number: 11088344
    Abstract: An electronic device is provided, which includes a window including a transparent area and an opaque area; a panel disposed below the transparent area and including multiple pixels; a substrate disposed below the panel; an optical adhesive member disposed between the window and the panel; and a filler member disposed in at least a portion of a space formed between the opaque area and the substrate. The filler member transmits a light of a designated band, which is for curing the optical adhesive member, to a portion of the optical adhesive member disposed below the opaque area through a separation space between the filler member and the portion of the optical adhesive member.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: August 10, 2021
    Inventors: Kiju Kwak, Sunggwan Woo, Hunjo Jung
  • Patent number: 11088295
    Abstract: Group III nitride based light emitting diode (LED) structures include multiple quantum wells with barrier-well units that include Ill nitride interface layers. Each interface layer may have a thickness of no greater than about 30% of an adjacent well layer, and a comparatively low concentration of indium or aluminum. One or more interface layers may be present in a barrier-well unit. Multiple barrier-well units having different properties may be provided in a single active region.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: August 10, 2021
    Assignee: CreeLED, Inc.
    Inventors: Thomas A. Kuhr, Robert David Schmidt, Daniel Carleton Driscoll, Brian T. Collins
  • Patent number: 11088167
    Abstract: The invention discloses a transistor, a three dimensional memory device including such transistors and a method of fabricating such memory device. The transistor according to the invention includes a pillar of a semiconductor material, extending in a normal direction of a semiconductor substrate, a gate dielectric layer and a gate conductor. The pillar of the semiconductor material has a base side face parallel to the normal direction, a tapered side face opposite to the base side face, a top face perpendicular to the normal direction, a bottom face opposite to the top face, a front side face adjacent to the base side face and the tapered side face, and a rear side face opposite to the front side face. A first elongated portion, sandwiched among the base side face, the front side face, the bottom face and the top face, forms a source region. A second elongated portion, sandwiched among the base side face, the rear side face, the bottom face and the top face, forms a drain region.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: August 10, 2021
    Inventor: Chen-Chih Wang
  • Patent number: 11081428
    Abstract: An electronic device includes a package structure with opposite first and second sides spaced apart along a first direction, opposite third and fourth sides spaced apart along a second direction, opposite fifth and sixth sides spaced apart along a third direction, the first, second, and third directions being orthogonal to one another. A set of first leads extend outward from the first side along the first direction, a set of second leads extend outward from the second side along the first direction, and a thermal pad includes a first portion that extends along a portion of the fifth side, and a second portion that extends along a portion of the third side to facilitate cooling and visual solder inspection when soldered to a host printed circuit board.
    Type: Grant
    Filed: August 10, 2019
    Date of Patent: August 3, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Stanley Chou, Yuh-Harng Chien, Steven Alfred Kummerl, Bo-Hsun Pan, Pi-Chiang Huang, Frank Yu, Chih-Chien Ho
  • Patent number: 11081397
    Abstract: A gate structure is formed over a substrate. The gate structure includes a gate electrode and a hard mask located over the gate electrode. The hard mask comprises a first dielectric material. A first interlayer dielectric (ILD) is formed over the gate structure. The first ILD comprises a second dielectric material different from the first dielectric material. A first via is formed in the first ILD. Sidewalls of the first via are surrounded by spacers that comprise the first dielectric material. A second ILD is formed over the first ILD. A via hole is formed in the second ILD. The via hole exposes the first via. A protective layer is formed in the via hole. A bottom segment of the protective layer is removed. Thereafter, an etching process is performed. A remaining segment of the protective layer prevents an etching of the spacers during the etching process.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Leo Hsu, Louis Lin
  • Patent number: 11081438
    Abstract: An object of the present invention is to improve manufacturing efficiency of a semiconductor device. The method of manufacturing a semiconductor device includes a sealing step of sealing a semiconductor chip mounted on the wiring substrate. The sealing step includes a step of arranging the wiring substrate between an upper mold and a lower mold, suctioning a lower surface of the wiring substrate with the plurality of suction holes, thereby holding the wiring substrate the upper mold, and a step of sealing the semiconductor chip, an upper surface of the wiring substrate, and the plurality of side surfaces of the wiring substrate such that each of the semiconductor chip, the upper surface of the wiring substrate, and the plurality of side surfaces of the wiring substrate is covered with the resin in the lower mold.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: August 3, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshiaki Sato, Yoshinori Miyaki, Junichi Arita
  • Patent number: 11066296
    Abstract: This work develops a novel microfluidic method to fabricate conductive graphene-based 3D micro-electronic circuits on any solid substrate including, Teflon, Delrin, silicon wafer, glass, metal or biodegradable/non-biodegradable polymer-based, 3D microstructured, flexible films. It was demonstrated that this novel method can be universally applied to many different natural or synthetic polymer-based films or any other solid substrates with proper pattern to create graphene-based conductive electronic circuits. This approach also enables fabrication of 3D circuits of flexible electronic films or solid substrates. It is a green process preventing the need for expensive and harsh postprocessing requirements for other fabrication methods such as ink-jet printing or photolithography. We reported that it is possible to fill the pattern channels with different dimensions as low as 10×10 ?m. The graphene nanoplatelet solution with a concentration of 60 mg/mL in 70% ethanol, pre-annealed at 75° C. for 3 h, provided ˜0.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: July 20, 2021
    Assignee: Iowa State University Research Foundation, Inc.
    Inventors: Metin Uz, Surya Mallapragada
  • Patent number: 11063152
    Abstract: A semiconductor device including a source/drain region having a V-shaped bottom surface and extending below gate spacers adjacent a gate stack and a method of forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a fin; forming a gate spacer on a sidewall of the gate stack; etching the fin with a first anisotropic etch process to form a first recess adjacent the gate spacer; etching the fin with a second etch process using etchants different from the first etch process to remove an etching residue from the first recess; etching surfaces of the first recess with a third anisotropic etch process using etchants different from the first etch process to form a second recess extending below the gate spacer and having a V-shaped bottom surface; and epitaxially forming a source/drain region in the second recess.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Wei Lee, Hsueh-Chang Sung, Yen-Ru Lee, Jyun-Chih Lin, Tzu-Hsiang Hsu, Feng-Cheng Yang
  • Patent number: 11062943
    Abstract: A method includes patterning an interconnect trench in a dielectric layer. The interconnect trench has sidewalk and a bottom surface. A liner layer is deposited on the sidewalls and the bottom surface of the interconnect trench. The interconnect trench is filled with a first conductive metal material. The conducting metal material is recessed to below a top surface of the dielectric layer. A cap layer is deposited on a top surface of the first conductive metal material. The cap layer and the liner layer are of the same material. The method further includes forming a via on a portion of the interconnect trench.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Koichi Motoyama, Nicholas Anthony Lanzillo, Christopher J. Penny, Somnath Ghosh, Robert Robison, Lawrence A. Clevenger
  • Patent number: 11056596
    Abstract: A semiconductor device according to an exemplary embodiment of the present disclosure includes: an n? type layer disposed in a first surface of a substrate; an n type layer disposed on the n? type layer; a first electrode disposed on the n type layer, and a second electrode disposed in a second surface of the substrate, wherein an energy band gap of the n? type layer is larger than an energy band gap of the n type layer.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: July 6, 2021
    Assignees: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION
    Inventor: NackYong Joo
  • Patent number: 11049968
    Abstract: A semiconductor memory device comprising a strained semiconductor layer and a contact etch stop layer, CESL, wherein the strained semiconductor layer and the CESL are both arranged to reduce the probability of an electron tunnelling out of a charge trapping layer of the semiconductor memory device.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: June 29, 2021
    Assignee: X-FAB SEMICONDUCTOR FOUNDRIES GMBH
    Inventors: Eng Gek Hee, Ek Chien Yeo, Steffen Thiem, Choon Swee Tan
  • Patent number: 11049716
    Abstract: Provided herein are methods of filling gaps using high density plasma chemical vapor deposition (HDP CVD). According to various implementations, carbon-containing films such as amorphous carbon and amorphous carbide films are deposited by HDP CVD into gaps on substrates to fill the gaps. The methods may involve using high hydrogen-content process gasses during HDP CVD deposition to provide bottom-up fill. Also provided are related apparatus.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: June 29, 2021
    Assignee: Lam Research Corporation
    Inventors: Wei Tang, Jason Daejin Park, Bart J. van Schravendijk, Shu Tsai Wang, Kaihan Abidi Ashtiani