Abstract: A semiconductor device according to an exemplary embodiment of the present disclosure includes: an n? type layer disposed in a first surface of a substrate; an n type layer disposed on the n? type layer; a first electrode disposed on the n type layer, and a second electrode disposed in a second surface of the substrate, wherein an energy band gap of the n? type layer is larger than an energy band gap of the n type layer.

Abstract: Provided herein are methods of filling gaps using high density plasma chemical vapor deposition (HDP CVD). According to various implementations, carbon-containing films such as amorphous carbon and amorphous carbide films are deposited by HDP CVD into gaps on substrates to fill the gaps. The methods may involve using high hydrogen-content process gasses during HDP CVD deposition to provide bottom-up fill. Also provided are related apparatus.

Abstract: Example embodiments of systems and methods for creating a chip fraud prevention system with a fraud prevention fluid are provided. A chip fraud prevention system includes a device including a chip. The chip may be at least partially encompassed in a chip pocket which contains a fraud prevention fluid. The fraud prevention fluid may be contained in a capsule or implemented as an adhesive. One or more connections may be communicatively coupled to at least one surface of the chip. The one or more connections may be placed in close proximity and/or in contact to the fraud prevention fluid.

Abstract: A semiconductor memory device comprising a strained semiconductor layer and a contact etch stop layer, CESL, wherein the strained semiconductor layer and the CESL are both arranged to reduce the probability of an electron tunnelling out of a charge trapping layer of the semiconductor memory device.

Abstract: A light emitting device is provided. The light emitting device includes a light emitting element, which emits blue light, and a light transmissive member having a first principal face bonded to the light emitting element and a second principal face opposite the first principal face. The light transmissive member has a light transmissive base material and wavelength conversion substances, which are contained in the base material and which absorb the light from the light emitting element and emit light. The wavelength conversion substances are localized in the base material towards the first principal face, and include a first phosphor which emits green to yellow light and a second phosphor which emits red light. The first phosphor is more localized towards the first principal face than the second phosphor. The second phosphor is a manganese-activated fluoride phosphor.

Abstract: A MOSFET includes a substrate, a trench, a bottom oxide, a shield poly, two gate polys and an inter-poly oxide. The trench is formed on the substrate. The bottom oxide is formed on the trench. The shield poly is formed on the trench, and a part of the bottom oxide is separated by the shield poly. The two gate polys are formed on the bottom oxide. The inter-poly oxide is formed between the two gate polys. The shield poly is staggered from at least one of the two gate polys in a horizontal direction and a vertical direction. Therefore, the capacitance between a source electrode and a gate electrode is effectively reduced, and the delay time during switching is shorten and the energy loss is reduced at the same time.

Abstract: Discussed is an electroluminescent display device, wherein a first electrode of a first sub pixel includes a first lower electrode and a first upper electrode, a first electrode of a second sub pixel includes a second lower electrode and a second upper electrode, a first electrode of a third sub pixel includes a third lower electrode and a third upper electrode, a distance between the first lower electrode and the first upper electrode, a distance between the second lower electrode and the second upper electrode, and a distance between the third lower electrode and the third upper electrode are different from one another, the third upper electrode includes a third lower layer and a third upper layer, and the third lower layer is formed in the same pattern as that of the third lower electrode in an upper surface of the third lower electrode.

Abstract: Embodiments are directed to a method and resulting structures for a semiconductor device having reduced parasitic capacitance. A semiconductor fin is formed on a substrate. A first bottom spacer is formed on a surface of the substrate and a sidewall of the semiconductor fin. A sacrificial spacer is formed over a channel region of the semiconductor fin and a portion of the first bottom spacer. A second bottom spacer is formed on a surface of the first bottom spacer and adjacent to the sacrificial spacer. The sacrificial spacer is removed and a conductive gate is formed over the channel region of the semiconductor fin.

Abstract: A semiconductor device includes a semiconductor substrate with a collector region formed within the semiconductor substrate. A base region, including a first base region and a second base region, is formed over the collector region. An extrinsic base region is formed laterally adjacent to and coupled to the second base region. A base link region is disposed proximate to the second base region, wherein the base link region couples the extrinsic base sidewall to the second base region. A method for forming a semiconductor device includes forming the collector region within the semiconductor substrate, forming a plurality of dielectric layers over the collector region, forming an extrinsic base layer over the collector region, etching an emitter window, forming the first base region over the collector region, forming the second base region over the first base region, wherein forming the second base region includes forming the base link region.

Abstract: The present disclosure provides a semiconductor structure and a method for preparing the semiconductor structure. The semiconductor structure includes a substrate; a drain disposed in the substrate; a drain contact disposed in the drain; a source disposed in the substrate; a source contact disposed in the source; a gate structure with a bottom disposed in the substrate between the drain and the source; a channel disposed at the bottom of the gate structure connecting the drain and the source; a drain stressor disposed in the drain between the gate structure and the drain contact; a drain strained silicon layer disposed in the substrate surrounding the drain stressor connected to the channel; a source stressor disposed in the source between the source contact and the gate structure; and a source strained silicon layer disposed in the substrate surrounding the source stressor connected to the channel.

Abstract: Example sensor apparatus for microfluidic devices and related methods are disclosed. In examples disclosed herein, a method of fabricating a sensor apparatus for a microfluidic device includes etching a portion of an intermediate layer to form a sensor chamber in a substrate assembly, where the substrate assembly has a base layer and the intermediate layer, and where the base layer comprises a first material and the intermediate layer comprises a second material different than the first material. The method includes forming a first electrode and a second electrode in the sensor chamber. The method also includes forming a fluidic transport channel in fluid communication with the sensor chamber, where the fluidic transport channel comprises a third material different than the first material and the second material.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a gate electrode having a two-sided staircase shape above the substrate, a blocking layer on the gate electrode, a plurality of discrete charge trapping layers each extending laterally on the blocking layer, a tunneling layer on the plurality of charge trapping layers, and a plurality of discrete channel layers each extending laterally on the tunneling layer. The plurality of charge trapping layers are disposed corresponding to stairs of the two-sided staircase shape of the gate electrode, respectively. The plurality of channel layers are disposed corresponding to the stairs of the two-sided staircase shape, respectively.

Abstract: A method of manufacturing an OLED device includes: preparing a substrate on which a first conductive layer and a pixel defining film defining a plurality of pixels and exposing the first conductive layer for each of the plurality of pixels; disposing a photoresist pattern on the pixel defining film, the photoresist pattern comprising an opening exposing a first pixel of the plurality of pixels; disposing a first material layer onto an entire surface of the substrate to simultaneously dispose an organic light-emitting layer and a first deposition layer; disposing a second material layer onto the entire surface of the substrate to simultaneously dispose a second conductive layer and a second deposition layer; disposing a third material layer onto the entire surface of the substrate to simultaneously dispose a protection layer and a third deposition layer; and removing the photoresist pattern and the first, second, and third deposition layers.

Abstract: A semiconductor structure and a forming method thereof are disclosed. The forming method includes: providing a base; forming a first electrode layer on the base; forming a capacitance dielectric layer on a top and a sidewall of the first electrode layer; and forming a second electrode layer conformally covering the capacitance dielectric layer. Compared with a solution in which the capacitance dielectric layer only covers the top of the first electrode layer, in the present disclosure, an effective area between the second electrode layer and the first electrode layer is increased, the second electrode layer, the first electrode layer, and the capacitance dielectric layer located on the top of the first electrode layer construct one capacitance, and the second electrode layer, the first electrode layer, and the capacitance dielectric layer located on the sidewall of the first electrode layer construct other four capacitances. That is, the formed capacitor structure includes five parallel capacitances.

Abstract: Bipolar junction transistor structures and methods for making the same are provide. The method includes: providing a substrate with an insulator layer and a device layer over the insulator layer, forming an intrinsic base from the device layer, forming emitter and collector regions from the device layer, and after forming i) the intrinsic base and ii) the emitter and collector regions, depositing a single crystalline extrinsic base over the intrinsic base.

Abstract: A method of trimming the refractive index of material forming at least part of one or more structures integrated in one or more pre-fabricated devices, the method comprising: implanting one or more first regions of material of one or more pre-fabricated devices, encompassing at least partially one or more device structures, with ions to alter the crystal form of the material within the one or more first regions and change the refractive index of the material within the one or more first regions; and heat treating one or more second regions of material of the one or more devices, encompassing at least partially the one or more first regions, to alter the crystal form of the material within the one or more first regions encompassed by the one or more second regions and change the refractive index thereof, thereby trimming the refractive index of the material of at least part of the one or more device structures, such that the one or more device structures provide one or more predetermined device outputs.

Abstract: A magnetic tunneling junction sensor includes a free ferromagnetic layer of material, a pinned ferromagnetic layer of material, the free ferromagnetic layer and the pinned ferromagnetic layer separated by a thin insulating layer of material through which electrons can tunnel, an oxidized silicon wafer, the free ferromagnetic layer, thin insulating layer and the pinned ferromagnetic layer deposited on the oxidized silicon wafer, and extrinsic magnetic flux.

Abstract: Embodiments of the present disclosure relate to a method of forming a low-k dielectric material, for example, a low-k gate spacer layer in a FinFET device. The low-k dielectric material may be formed using a precursor having a general chemical structure comprising at least one carbon atom bonded between two silicon atoms. A target k-value of the dielectric material may be achieved by controlling carbon concentration in the dielectric material.

Abstract: Magnetic tunnel junction pillars are encapsulated by an oxidized diffusion barrier layer. Oxygen within the encapsulating material is used to oxidize metallic residue outside the pillars, converting the residue to a non-conductive material such as a metal oxide or metal oxynitride. Selective deposition of manganese on the metal layers of the pillars can be followed by oxidation of the manganese to form a manganese oxide diffusion barrier. Alternatively, manganese deposition can be followed by deposition of silicon dioxide and subsequent annealing to form a manganese silicate diffusion barrier.

Abstract: A LCD device having a large pixel holding capacitance includes opposedly facing first and second substrates, and liquid crystal between them. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode connected to the video signal line and a second electrode connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film above the first silicon nitride film, a capacitance electrode above the organic insulation film, and a second silicon nitride film above the capacitance electrode and below the pixel electrode. A contact hole etched in both the first and second silicon nitride films connects the second electrode and the pixel electrode to each other. A holding capacitance is formed by the pixel electrode, the second silicon nitride film and the capacitance electrode.