Patents Examined by Andre? C. Stevenson
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Patent number: 11251279Abstract: A high voltage transistor structure includes a substrate. A metal gate is disposed on the substrate. At least one insulating material structure penetrates the metal gate. A metal compound layer is disposed between the metal gate and the substrate, between the insulating material structure and the substrate. The metal compound layer is a continuous structure. Agate dielectric layer is disposed under the metal compound layer and contacts the substrate.Type: GrantFiled: July 23, 2020Date of Patent: February 15, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhi-Cheng Lee, Kai-Lin Lee, Wei-Jen Chen
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Patent number: 11251088Abstract: A semiconductor device includes an active area having source and drain regions and a channel region between the source and drain regions, an isolation structure surrounding the active area, and a gate structure over the channel region of the active area and over the isolation structure, wherein the isolation structure has a first portion under the gate structure and a second portion free from coverage by the gate structure, and a top of the first portion of the isolation structure is lower than a top of the second portion of the isolation structure.Type: GrantFiled: June 15, 2020Date of Patent: February 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Long-Jie Hong, Chih-Lin Wang, Kang-Min Kuo
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Patent number: 11245007Abstract: A semiconductor device includes a semiconductor body of a wide-bandgap semiconductor material. A plurality of first bond areas is connected to a first load terminal of the semiconductor device. First gate fingers are arranged between the first bond areas. The first gate fingers extend in a first lateral direction and branch off from at least one of a first gate line portion and a second gate line portion. Second gate fingers extend in the first lateral direction. A first length of any of the first gate fingers along the first lateral direction is greater than a second length of any of the second gate fingers along the first lateral direction. A sum of the first length and the second length is equal to or greater than a lateral distance between the first gate line portion and the second gate line portion along the first lateral direction.Type: GrantFiled: May 14, 2018Date of Patent: February 8, 2022Assignee: Infineon Technologies AGInventor: Dethard Peters
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Patent number: 11244864Abstract: A method for fabricating a semiconductor device includes forming a shared source/drain connection at a first planar level to connect a first source/drain contact structure disposed on a first source/drain region to a second source/drain contact structure disposed on a second source/drain region, and forming a shared gate connection to connect a first gate structure to a second gate structure. The shared gate connection is formed at a second planar level different from the first planar level to reduce parasitic capacitance between the shared source/drain connection and the shared gate connection.Type: GrantFiled: April 21, 2020Date of Patent: February 8, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ruilong Xie, Reinaldo Vega, Alexander Reznicek, Kangguo Cheng
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Patent number: 11244868Abstract: A method for producing a component is provided, a base of which is formed by transistors on a substrate, including: forming a gate area, spacers, and a protective coating partly covering the spacers and a sidewall portion of a cavity without covering a top face of the gate area and a base portion of the cavity; forming a contact module, the gate located in beneath the module; and removing part of the coating with an isotropic light-ion implantation to form modified superficial parts in a thickness, respectively, of the contact module, of the coating, and of the base portion, and with an application of a plasma to: etch the modified superficial parts to only preserve, in the coating, a residual part of the coating, and to form a silicon oxide-based film on exposed surfaces, respectively, of the contact module, of the cavity, and of the coating.Type: GrantFiled: August 21, 2020Date of Patent: February 8, 2022Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventor: Nicolas Posseme
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Patent number: 11233130Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of semiconductor nanosheets, a bottom dielectric layer, and a gate stack. The substrate includes at least one fin. The plurality of semiconductor nanosheets are stacked on the at least one fin. The bottom dielectric layer is disposed between the at least one fin and the plurality of semiconductor nanosheets. The gate stack wraps the plurality of semiconductor nanosheets.Type: GrantFiled: February 24, 2020Date of Patent: January 25, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chi-On Chui
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Patent number: 11217487Abstract: A method for forming a semiconductor arrangement includes forming a first gate structure over a first active region. The first gate structure includes a first conductive layer. An etch process is performed using a process gas mixture to recess the first gate structure and define a recess. The etch process comprises a first phase to form a polymer layer over the first conductive layer and to modify a portion of the first conductive layer to form a modified portion of the first conductive layer and a second phase to remove the polymer layer and to remove the modified portion of the first conductive layer.Type: GrantFiled: November 19, 2019Date of Patent: January 4, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Yi-Chen Lo, Li-Te Lin, Pinyen Lin
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Patent number: 11211471Abstract: The present invention discloses a metal gate process. A sacrificial nitride layer is introduced during the fabrication of metal gates. The gate height can be well controlled by introducing the sacrificial nitride layer. Further, the particle fall-on problem can be effectively solved.Type: GrantFiled: September 10, 2020Date of Patent: December 28, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Fu-Shou Tsai, Yong-Yi Lin, Yang-Ju Lu, Yu-Lung Shih, Ji-Min Lin, Ching-Yang Chuang, Kun-Ju Li
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Patent number: 11211475Abstract: A method of forming a method of forming a semiconductor device includes providing a semiconductor structure, etching back each gate structure of a plurality of gate structures to form an opening, forming a barrier layer over the dielectric layer, forming a sacrificial layer over the barrier layer, planarizing the sacrificial layer till a surface of the sacrificial layer is substantially flat, and using a gas cluster ion beam (GCIB) process to planarize the sacrificial layer and the barrier layer, and to remove the sacrificial layer and to provide a planarized barrier layer. The semiconductor structure includes a semiconductor substrate, a fin, the plurality of gate structures, and a dielectric layer over the semiconductor substrate between adjacent gate structures. A top of the dielectric layer is coplanar with a top of each of the plurality of gate structures.Type: GrantFiled: June 28, 2020Date of Patent: December 28, 2021Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Haiyang Zhang, Jian Chen, Bo Su
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Patent number: 11205609Abstract: A semiconductor structure with an air gap includes a dielectric stack having a first dielectric layer on a substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer. A first conductive layer and a second conductive layer are disposed in the dielectric stack. The first conductive layer and the second conductive layer are coplanar. A cross-like-shaped air gap is disposed in the dielectric stack between the first and second conductive layers. An oxide layer is disposed on a sidewall of the second dielectric layer within the cross-like-shaped air gap.Type: GrantFiled: March 31, 2020Date of Patent: December 21, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Pin Hsu, Chih-Jung Wang, Chu-Chun Chang, Kuo-Yuh Yang, Chia-Huei Lin, Purakh Raj Verma
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Patent number: 11201169Abstract: A memory device includes: a first bit line located on a dielectric layer and a second bit line located over the dielectric layer; a first word line and a second word line located between the first bit line and the second bit line; a source line located between the first word line and the second word line; a channel pillar penetrating through the first word line and the source line and the second word line, and being connected to the first bit line, the source line and the second bit line; and a charge storage structure including an upper portion surrounding an upper sidewall of the channel pillar and located between the second word line and the channel pillar; and a lower portion surrounding a lower sidewall of the channel pillar and located between the first word line and the channel pillar.Type: GrantFiled: March 31, 2020Date of Patent: December 14, 2021Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chih-Hsiung Lee, Shaw-Hung Ku
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Patent number: 11195724Abstract: A method of manufacturing a semiconductor structure includes the following operations. A substrate embedded with a shallow trench isolation is received. A first dielectric layer is formed on the substrate. An etching process is performed to form a hole in the first dielectric layer and form a pit in the substrate, wherein an upper surface of the shallow trench isolation is exposed from the hole, and the pit is adjacent to the shallow trench isolation. A second dielectric layer is formed on the first dielectric layer and the shallow trench isolation and in the pit. The second dielectric layer is treated with a plasma to convert a first portion of the second dielectric layer substantially on the first dielectric layer and the shallow trench isolation to a plasma-treated layer. The plasma-treated layer is removed to remain a second portion of the second dielectric layer in the pit.Type: GrantFiled: July 1, 2020Date of Patent: December 7, 2021Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Jen-I Lai, Chun-Heng Wu
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Patent number: 11195934Abstract: The present disclosure provides embodiments of a semiconductor structure having bi-layer self-aligned contact. The semiconductor structure includes a gate stack disposed on a semiconductor substrate and having a first height, a spacer disposed on a sidewall of the gate stack and having a second height greater than the first height, and a first etch stop layer disposed on a sidewall of the gate spacer and having a third height greater than the second height. The semiconductor structure further includes a first dielectric layer disposed over the gate stack and contacting the gate spacer and the first etch stop layer and a second dielectric layer disposed on the first dielectric layer and contacting the first etch stop layer.Type: GrantFiled: June 8, 2020Date of Patent: December 7, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
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Patent number: 11183395Abstract: A semiconductor device and its fabrication method are provided. The method includes forming a core layer on a first region of a base substrate layer; forming sidewall spacer layers on sidewalls of two sides of the core layer along a first direction; forming a filling layer on a second region between adjacent sidewall spacer layers which are arranged along the first direction; forming a first dividing trench in the filling layer on the second region to divide the filling layer along a second direction, where sidewalls of the first dividing trench, arranged along the first direction, expose corresponding sidewall spacer layers; forming a second dividing trench in the core layer to divide the core layer along the second direction; forming a second dividing layer in the second dividing trench when forming a first dividing layer in the first dividing trench; and removing the filling layer and the core layer.Type: GrantFiled: April 22, 2020Date of Patent: November 23, 2021Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Linlin Sun, Bo Su
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Patent number: 11177336Abstract: A method for repairing a display substrate includes detecting whether there is a fault point on signal lines. If a fault point is detected on a signal line, short-circuiting is performed of two sides of the at least one fault point through line portions of two drive power lines respectively located at two sides of the at least one fault point and perpendicular to the signal line where the at least one fault point is located and a line portion of a drive power line located at one side of the at least one fault point and parallel to the signal line where the at least one fault point is located.Type: GrantFiled: August 31, 2018Date of Patent: November 16, 2021Assignee: BOE Technology Group Co., Ltd.Inventors: Cuili Gai, Baoxia Zhang, Ling Wang
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Patent number: 11177138Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method includes forming a first hard mask layer over a substrate and forming a second hard mask layer over the first hard mask layer. The second hard mask layer is patterned to define an island having a first width along a first direction. The island is patterned to form a patterned island having a second width along the first direction that is less than the first width. A sacrificial mask is formed over the first hard mask layer and the first hard mask layer is patterned according to the patterned island and the sacrificial mask.Type: GrantFiled: April 1, 2020Date of Patent: November 16, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Ying Lee, Jyu-Horng Shieh
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Patent number: 11177145Abstract: A method of manufacturing a plurality of electronic circuits is disclosed. Each electronic circuit comprises a respective first portion, comprising a respective group of contact pads, and a respective integrated circuit, IC, comprising a respective group of terminals and mounted on the respective group of contact pads with each terminal in electrical contact with a respective contact pad. The method comprises: providing a first structure comprising the plurality of first portions; providing a second structure comprising the plurality of ICs and a common support arranged to support the plurality of ICs; transferring said ICs from the common support onto a first roller having a removable surface portion; and transferring said ICs from the first roller onto the first structure such that each group of terminals is mounted on a respective group of contact pads.Type: GrantFiled: June 18, 2018Date of Patent: November 16, 2021Assignee: PRAGMATIC PRINTING LTD.Inventors: Neil Davies, Richard Price, Stephen Devenport, Stuart Speakman
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Patent number: 11174153Abstract: A microelectromechanical (MEMS) device may be coupled to a dielectric material at an upper planar surface or lower planar surface of the MEMS device. One or more temperature sensors may be attached to the dielectric material layer. Signals from the one or more temperature sensors may be used to determine a thermal gradient along on axis that is normal to the upper planar surface and the lower planar surface. The thermal gradient may be used to compensate for values measured by the MEMS device.Type: GrantFiled: August 21, 2019Date of Patent: November 16, 2021Assignee: INVENSENSE, INC.Inventors: Ilya Gurin, Matthew Julian Thompson, Vadim Tsinker
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Patent number: 11170990Abstract: Aspects of the disclosure provide a method including depositing an underlayer comprising silicon oxide over a substrate, depositing a polysilicon liner on the underlayer, and depositing an amorphous silicon layer on the polysilicon liner. Aspects of the disclosure provide a device intermediate including a substrate, an underlayer comprising silicon oxide formed over the substrate, a polysilicon liner disposed on the underlayer, and an amorphous silicon layer disposed on the polysilicon liner.Type: GrantFiled: February 19, 2020Date of Patent: November 9, 2021Assignee: APPLIED MATERIALS, INC.Inventors: Krishna Nittala, Rui Cheng, Karthik Janakiraman, Praket Prakash Jha, Jinrui Guo, Jingmei Liang
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Patent number: 11164775Abstract: A method of manufacturing a semiconductor device includes depositing a first insulation film in a via hole of a semiconductor substrate and above a first surface thereof, the semiconductor substrate having a circuit substrate on a second surface thereof, depositing a second insulation film having a covering property lower than the first insulation film in the via hole and above the first surface, and removing the first and second insulation films deposited at the bottom of the via hole by anisotropic etching.Type: GrantFiled: March 2, 2020Date of Patent: November 2, 2021Assignee: KIOXIA CORPORATIONInventors: Kazuki Takahashi, Shinya Okuda
