Abstract: A packaging substrate is fabricated using two plating steps for respectively plating the gold-plating areas defined on two opposite sides of the substrate. Before plating, the gold-plating areas are defined by a layer of solder mask. By doing this, the plated gold layer will not overlap with the solder mask, thereby preventing peeling or reliability problems.

Abstract: Exemplary embodiments of the present invention provide a pattern forming method that secures sufficient alignment accuracy when a pattern is formed by droplet ejection. Exemplary embodiments provide a pattern on a substrate by placing a liquid material including a pattern forming material onto the substrate by droplet ejection, including placement of the liquid material including an alignment mark forming material, onto the substrate by the droplet ejection prior to forming the pattern; and placement of the pattern forming material by making use of a placed alignment mark.

Abstract: Disclosed is a method for fabricating a capacitor in a semiconductor memory device. The method includes the steps of: sequentially forming a first insulation layer and a first etch stop layer on a substrate; forming a plurality of contact holes by etching the first insulation layer and the first etch stop layer; forming a plurality of contact plugs on the plurality of contact holes such that the contact plugs are more projected than the first etch stop layer; sequentially forming a second etch stop layer and a capacitor insulation layer; forming a plurality of openings by etching the second etch stop layer and the capacitor insulation layer to expose the contact plugs; sequentially forming a storage node material and a sacrificial layer; etching the storage node material and the sacrificial layer, thereby obtaining isolated storage node material; and removing remaining portions of the sacrificial layer and the capacitor insulation layer.

Abstract: A technique for manufacturing a low-cost, small volume, and highly integrated semiconductor device is provided. A characteristic of the present invention is that a semiconductor element formed by using a semiconductor thin film is transferred over a semiconductor element formed by using a semiconductor substrate by a transfer technique in order to manufacture a semiconductor device. Compared with the conventional manufacturing method, mass production of semiconductor devices with lower cost and higher throughput can be realized, and production cost per semiconductor device can be reduced.

Abstract: Determining the maximum number of dies that fit on a semiconductor wafer is disclosed. The x- and y-coordinates of an initial starting position on a semiconductor wafer are determined. The delta-x and delta-y offsets for subsequent starting positions are also determined. Starting at a current position equal to the initial starting position, the following is repeated for each of a predetermined number of times. First, the semiconductor wafer is covered with fields. Second, the number of dies that are completely covered by the semiconductor wafer is counted. Third, the current starting position is increased by the delta-x and the delta-y offsets. Once this has been repeated, the actual starting position is set as the current starting position at which the number of dies completely covered by the semiconductor wafer is maximized.

Abstract: The present invention is generally directed to various methods of controlling gate electrode doping, and various systems for accomplishing same. In one illustrative embodiment, the method disclosed herein comprises performing at least one process operation to form a doped layer of gate electrode material, measuring a sheet resistance of the doped layer of gate electrode material and adjusting at least one parameter of at least one process if the measured sheet resistance does not fall within acceptable limits. In one embodiment, the system is comprised of a process tool for performing at least one process operation to form a doped layer of gate electrode material, a metrology tool for measuring a sheet resistance of the doped layer of gate electrode material and a controller for adjusting at least one parameter of at least one process operation if the measured sheet resistance of the doped layer of gate electrode material does not fall within acceptable limits.

Abstract: Disclosed is apparatus and method for decreasing diffusive damage effects to a primary structure (406, 506) within a semiconductor device (400, 500). The device typically comprises a first interconnect (402, 502), and a second interconnect (404, 504). The primary structure is disposed between the first and second interconnects to electrically intercouple them. An active diffusion volume (410, 514) is determined, within which the primary structure is located. A buffer structure (408, 508) is disposed upon the first interconnect in proximity to the primary structure and adapted to buffer the primary via structure from diffusive voiding occurring at a contact point between the primary structure and the first interconnect.

Abstract: A semiconductor manufacturing method whereby reactive gas processing such as selective epitaxial growth can be carried out with high precision by correctly adjusting conditions during processing is performed by a semiconductor manufacturing apparatus which can restrict increases in the moisture content, prevent heavy metal pollution and the like, and investigate the correlation between moisture content in the process chamber and outside regions. The moisture content in a reaction chamber and in a gas discharge system of the reaction chamber are measured when a substrate is provided, and the conditions for reactive gas processing are adjusted based on the moisture content.

Abstract: In a cantilever sensor and a fabrication thereof, by forming piezoelectric films on the same surface, it is possible to sense various information by an electric measuring method.

Abstract: A semiconductor device is formed to have a shape that reduces the thermal resistance of the semiconductor device.

Abstract: A carrier substrate includes at least one die-attach location and one or more terminals that protrude from a surface of the carrier substrate so as to prevent adhesive material from contaminating connection surfaces thereof. A solder mask for use on a carrier substrate includes a device-securing region positionable over at least a portion of a die-support location of the carrier substrate. Dams of the solder mask are positionable laterally adjacent to at least portions of the peripheries of corresponding terminals of the carrier substrate. The carrier substrate and solder mask may each include one or more recessed areas that laterally surround at least portions of their die-attach location and device-securing region, respectively, to receive some of the excess adhesive. Assemblies and packages including one or both of the carrier substrate and solder mask are also disclosed, as are assembly methods and methods for designing the carrier substrate and solder mask.

Abstract: A multi-layered circuit substrate for a semiconductor device comprises a multi-layered circuit substrate body having first and second surfaces and comprising a plurality of conductive pattern layers integrally laminated one on the other from the first surface to the second surface, so that a plurality of semiconductor device elements can be arranged on the first surface of the substrate body; and a plate member, a rigidity thereof being higher than that of the substrate body, attached to the second surface of the substrate body. A plurality of semiconductor elements can be mounted on the semiconductor element mounting surface defined on the first surface of the substrate body.

Abstract: A thermopile-based detector for monitoring and/or controlling semiconductor processes, and a method of monitoring and/or controlling semiconductor processes using thermopile-based sensing of conditions in and/or affecting such processes.

Abstract: A method of forming a wafer backside interconnecting wire includes forming a mask layer on the back surface, the mask layer including at least an opening corresponding to the bonding pad, performing a first etching process from the back surface to remove the wafer unprotected by the mask layer to form a recess, removing the mask layer, and forming an interconnecting wire on the back surface.

Abstract: This invention provides a method of manufacturing a substrate having a thin buried insulating film. An insulating layer (12) is formed on a single-crystal Si substrate (11). Ions are implanted into the substrate (11) through the insulating layer (12) to form an ion-implanted layer (13). The insulating layer (12) is thinned down to form a thin insulating layer (12a). A thus prepared first substrate is placed on a second substrate (20) to form a bonded substrate stack (30). After that, the bonded substrate stack (30) is split at the ion-implanted layer (13).

Abstract: A capacitor is arranged at the closest position to a semiconductor element and the generation of switching noise is reduced as low as possible by increasing the processing speed, arranging the components highly intensively and reducing the operation voltage. One face of the capacitor is connected to an electrode of the electrode forming face of the semiconductor element and the other face of the capacitor is connected to the connection pads on the wiring board so that the capacitor is interposed between the electrode forming face of the semiconductor element and the semiconductor mounting face of the wiring board, the other face of the capacitor is connected to the connection pads on the wiring board, and at the same time, flip-chip connection is conducted on the connection pads on the wiring board via the solder bumps connected to the electrodes of the semiconductor element.

Abstract: A test structure for assessing the reliability of a dielectric of a circuit element in an integrated circuit includes a plurality of test circuit elements and a plurality of contact pads, wherein at least some of the test circuit elements share one or more of the contact pads. In this way, a failure event can be detected with a reduced number of contact pads, thereby significantly reducing the area of floor space occupied by the test structure.

Abstract: A semiconductor device has a substrate having electrode pads, a first semiconductor chip mounted on the substrate with a first adhesion layer interposed therebetween, a second semiconductor chip mounted on the first semiconductor chip with a second adhesion layer interposed therebetween and having electrode pads on the upper surface thereof, wires for bonding the electrode pads of the substrate and the electrode pads of the second semiconductor chip to each other, and a mold resin sealing therein the first and second semiconductor chips and the wires. The peripheral edge portion of the first adhesion layer is protruding outwardly from the first semiconductor chip and the peripheral edge portion of the second semiconductor chip is protruding outwardly beyond the peripheral edge portion of the first semiconductor chip.

Abstract: A semiconductor device 39. The device includes an interposer 31 having two major surfaces. The first surface 311 includes patterned metal conductors and bond pads 351, and the second surface includes an array of solder balls 33. The device includes a semiconductor chip 30 having a top surface and a back surface, the back surface of the chip adjacent the interposer 31, and the top surface including a plurality of terminals. Also included is a layer of polymeric material 34 disposed on the first surface 311 of the interposer covering the area of the interposer over the solder ball array. At least a portion of the polymeric material layer is between the chip 30 and the interposer 31. The device further includes a plurality of electrical connections 35 between the chip terminals and the bond pads 351 on the interposer.

Abstract: A method for adjusting the resistivity in the surface of a semiconductive substrate including selective measurement and counter-doping of areas on a major surface of a semiconductive substrate.