Abstract: It is an object of the present invention to provide a method for solder bump formation using a combination of eutectic and high lead solders. The present invention provides a method for improving a solder bump composition for a flip chip.

Abstract: In an electric characteristic testing process corresponding to a process of the semiconductor apparatus manufacturing processes, in order to test a large area of the electrode pad of the body to be tested in a lump, an electric characteristic testing is performed by pressing a testing structure provided with electrically independent projections having a number equal to a number of conductor portions to be tested formed on an area to be tested of a body to be tested to the body to be tested.

Abstract: A flip chip bonding method and substrate architecture are disclosed for enhancing bonding performance between a chip and a substrate by forming a bump on the chip or the substrate. The flip chip bonding method includes performing pretreatment of a wafer having chips, dicing, and obtaining the pretreated individual chip; performing pretreatment of a substrate; aligning the pads of the pretreated chip with the pads of the pretreated substrate, and bonding the chip and the substrate together by applying an ultrasonic wave and heat using a collet and simultaneously applying pressure. Post treatment is performed by filling or molding resin after bonding. The chip or the substrate is formed with a plated bump, a stud bump or a wedge bump. The stud bump or the wedge bump can be additionally formed on the plated bump.

Abstract: A method for manufacturing a semiconductor device, comprising determining a first processing condition to apply a predetermined processing to a base body in a reaction chamber of a semiconductor device manufacturing apparatus, processing the base body based on the determined first processing condition, measuring one or more process parameters which vary the processing capability of the process on the base body during the processing, determining a second processing condition during the processing so that the processing amount is a set value, from a reference state representing the relation between the processing capability and the process parameter, and the measured value of the process parameter measured during processing, and changing the processing condition from the first processing condition to the second processing condition during the processing, and performing the processing based on the second processing condition.

Abstract: An apparatus and method of improving impedance matching between a RF signal and a multi-segmented electrode in a plasma reactor powered by the RF signal. The apparatus and method phase shifts the RF signal driving one or more electrode segment of the multi-segmented electrode, amplifies the RF signal, and matches an impedance of the RF signal with an impedance of the electrode segment, where the RF signal is modulated prior to matching of the impedance of the RF signal. The apparatus and method directionally couples an output of the matching of the impedance of the RF signal and the electrode segment, and adjusts the output of the matching of the impedance of the RF signal such that a directionally coupled output signal and a reference signal representing the RF signal at the output of the master RF oscillator produces a demodulated signal of minimal amplitude.

Abstract: A semiconductor device manufacturing method includes forming circuit devices and a plurality of electrode pads within a semiconductor chip formation region. The method also includes forming, on the main surface of the semiconductor wafer, an insulating film which exposes a portion of each of the electrode pads. The method also includes forming a conducting film covering the electrode pads, on the insulating film, and forming a wiring layer on the conducting film. The method also includes forming a negative resist layer in the semiconductor chip formation region and a peripheral region. The method also includes covering protruding electrode formation regions in the semiconductor chip formation region and covering electrode portion formation regions in the peripheral region, and performing optical exposure of the negative resist layer. The method also includes forming aperture portions in the protruding electrode formation regions and a plurality of electrode portions.

Abstract: A leadframe with a chip pad for two-sided stacking including a chip pad and a plurality of leads is disclosed. A dielectric adhesive layer is formed on the lower surface of the chip pad and is adhered onto a first trace layer, which has a connecting pad. At least a through hole passes through the chip pad, the dielectric adhesive layer and the first trace layer. An electrically-conductive material is formed inside the through hole for electrically connecting the connecting pad of the first trace layer to the chip pad. When an electronic component is mounted on the lower surface of the chip pad, a plurality of bonding wires having one ends on the upper surface of the chip pads can electrically connect the electronic component to the leads for achieving two-sided stacking of the chip pad.

Abstract: The present invention provides passive sampling systems and methods for monitoring contaminants in a semiconductor processing system. In one embodiment, that passive sampling system comprises a collection device in fluid communication with a sample line that provides a flow of gas from a semiconductor processing system. The collection device is configured to sample by diffusion one or more contaminants in the flow of gas.

Abstract: A ball grid array assembly includes a package cover that encapsulates a die and a portion of a substrate to which the die is attached, including an edge of the substrate. Encapsulation of the substrate edge by the cover reduces penetration of moisture or other contaminants into the substrate. The cover includes a rib that extends to contact a circuit board to which the ball grid array assembly is connected. With such a rib, planarity between the circuit board and the substrate is maintained during soldering.

Abstract: A system and method for thermally testing integrated circuits, comprising a temperature generation device located within the IC, configured with a primary purpose of affecting a temperature at the IC. A temperature sensor is located within close proximity to the IC, and a temperature controller is coupled to the temperature generation device and to the temperature sensor.

Abstract: A mechanism and methodology is provided for performing high-throughput thin-film experimentation with the use and integration of a heater. A single flange assembly contains an automated two-dimensional shutter system (which provides variable masking schemes for spatially selective shadow deposition) and a rotatable (indexed) chip/wafer/substrate heater. The automated two-dimensional shutter system comprises two shutter plate mounts that move in two perpendicular (x and y) directions, so that mounted shutters overlap with each other in certain regions. The substrate heater can be used in the gradient temperature mode or uniform temperature mode. The shutter plates and the heater plate are detachable and exchangeable from experiment to experiment in order to minimize cross contamination of materials.

Abstract: A method for observing defects in an amorphous material by transmission electron microscopy. The method generates an incident electron beam into the amorphous material, eliminates a generated diffraction wave to form an image only by a transmission wave coming through the amorphous material, and observes the image under an under-focus condition.

Abstract: A semiconductor processing system includes a chamber adapted to process a wafer, the chamber having an opening to facilitate access to the interior of the chamber. The system has a lid coupled to the chamber opening, the lid having an open position and a closed position. An actuator is connected to the lid to move the lid between the closed position and the open position. The system may include a floating pivot coupled to the lid and the actuator to align the lid with the opening when the lid closes.

Abstract: A method and apparatus for performing intra-tool monitoring and control within a multi-step processing system. The method monitors the processing of a workpiece as the workpiece is processed by independently operating processing tools and produces control parameters for the various independently operating processing tools to optimize the processing of the workpiece. More specifically, the apparatus provides a metrology station located between each of a plurality of semiconductor wafer processing tools such that measurements can be made on wafers as they are passed from one tool to another providing intra tool monitoring. The data collected by the metrology station is coupled to a metrology data analyzer, which determines whether any of the plurality of wafer processing tools should be adjusted to improve the processing of the overall wafer.

Abstract: A flip-chip light emitting diode and fabricating methods are disclosed. A soft transparent adhesive layer is utilized to past a transparent conductive substrate onto a light emitting diode epitaxy structure on a substrate, and the substrate is next removed entirely. Then, a mesa-etching process is performed to form a first top surface and a second top surface on the light emitting diode epitaxy structure for respectively exposing an n-type layer and a p-type layer in the light emitting diode epitaxy structure. Next, a metal reflective layer and a barrier layer are formed on the light emitting diode epitaxy structure in turn, and electrodes are finally fabricated on the barrier layer.

Abstract: According to some embodiments, a fin type active region is formed under an exposure state of sidewalls on a semiconductor substrate. A gate insulation layer is formed on an upper part of the active region and on the sidewalls, and a device isolation film surrounds the active region to an upper height of the active region. The sidewalls are partially exposed by an opening part formed on the device isolation film. The opening part is filled with a conductive layer that partially covers the upper part of the active region, forming a gate electrode. Source and drain regions are on a portion of the active region where the gate electrode is not. The gate electrode may be easily separated and problems causable by etch by-product can be substantially reduced, and a leakage current of channel region and an electric field concentration onto an edge portion can be prevented.

Abstract: In a semiconductor device for generating complementary PWM signals for, for example, controlling an inverter, a dead time is flexibly added by using a simple architecture. A dead time addition unit adds time elapsing until a value of a timer reaches a set value of a register as a first dead time at a rise of a first PWM signal. On the other hand, time elapsing until the value of the timer reaches a set value of another register is added as a second dead time at a rise of a second PWM signal.

Abstract: The present invention uses in situ scatterometry to determine if a defect (e.g., photoresist erosion, photoresist bending and pattern collapse) is present on a wafer. In one embodiment, in situ scatterometry is used to detect a pattern integrity defect associated with the layer of photoresist. In situ scatterometry produces diffraction data associated with the thickness of the photoresist patterned mask. This data is compared to a model of diffraction data associated with a suitable photoresist thickness. If the measured diffraction data is within an acceptable range, the next step of the photolithography process is carried out. However, if the measured thickness is outside of the suitable range, a defect is detected, and the wafer may be sent for re-working or re-patterned prior to main etch, thereby preventing unnecessary wafer scrap.

Abstract: Bright and dark field imaging operations in an optical inspection system occur along substantially the same optical path using the same light source by producing either a circular or an annular laser beam. Multiple beam splitting is achieved through the use of a diffractive optical element having uniform diffraction efficiency. A confocal arrangement for bright field and dark field imaging can be applied with multiple beam scanning for suppressing the signal from under-layers. A scan direction not perpendicular to the direction of movement of a target provides for improved die-to-die comparisons.

Abstract: Bright and dark field imaging operations in an optical inspection system occur along substantially the same optical path using the same light source by producing either a circular or an annular laser beam. Multiple beam splitting is achieved through the use of a diffractive optical element having uniform diffraction efficiency. A confocal arrangement for bright field and dark field imaging can be applied with multiple beam scanning for suppressing the signal from under-layers. A scan direction not perpendicular to the direction of movement of a target provides for improved die-to-die comparisons.