Abstract: A design and method for attaching an RFID chip to a conductive pattern is disclosed. According to the invention, multiple die are aligned with respective multiple conductive modules for structural and electrical attachment. As disclosed, the multiple die can be attached near simultaneously and without the need for intermediate handling. Therefore, substantial cost benefits are realized. Also disclosed is a method of making electrical connections employing the use of a laser. A photosensitive adhesive material is used to structurally secure the attachment.

Abstract: A method of fabricating a semiconductor integrated circuit device includes performing a wafer process to a plurality of wafers so as to form a plurality of semiconductor integrated circuit devices over each of the wafers, performing a first electrical test to a first set of wafers selected from the plurality of wafers formed in the wafer process and accommodated in a first wafer cassette placed in a wafer prober, and performing a second electrical test to a second set of wafers selected from the plurality of wafers formed in the wafer process and accommodated in a second wafer cassette placed in the wafer prober by automatically changing a test object to the second set of wafers.

Abstract: A subset test module and associated methodology for utilizing the same are disclosed that facilitate identification of process drift in semiconductor fabrication processing. A test wafer having a plurality of die formed thereon has a plurality of test modules formed within the die. The plurality of test modules are substantially the same from die to die, and the respective modules similarly include a plurality of test structures that are substantially the same from module to module. Corresponding test structures within respective modules on different die are inspected and compared to one another to find structures that are sensitive to process drift. One or more structures that experience differences from module to module on different die are utilized to develop one or more test modules that can be selectively located within production wafers and monitored to determine whether process drift and/or one or more other aberrant processing conditions are occurring.

Abstract: A plurality of semiconductor integrated circuits and a plurality of TEG circuits are aligned and provided on a substrate. In the TEG circuit, a built-in test circuit is provided in a region which faces a semiconductor integrated circuit across a dicing line region. The built-in test circuit and the semiconductor integrated circuit are connected by an interconnection which is provided on the dicing line region. The interconnection is cut for isolation into chips.

Abstract: In order to provide a method of detecting protrusion of an inspection object from a palette improved to be capable of making highly precise detection and reducing a socket breakage ratio, an inspection object is introduced into each of a plurality of pockets provided on the surface of a palette, which in turn is transported. A reflection level of the inspection object stored in each of the plurality of pockets is measured every palette with a reflection type photoelectric sensor. The maximum value and the minimum value of the reflection level are obtained from data of every palette, for calculating a dispersion width defined by the difference between the maximum value and the minimum value. The dispersion width is compared with a previously set determination threshold, for determining whether or not the dispersion width is greater than the determination threshold.

Abstract: A carbon nanotube memory cell for an integrated circuit wherein a chamber is constructed in a layer of a dielectric material such as silicon nitride down to a first electrical contact. This chamber is filled with polysilicon. A layer of a carbon nanotube mat or ribbon is formed over the silicon nitride layer and the chamber. A dielectric material, such as an oxide layer, is formed over the nanotube strips and patterned to form an upper chamber down to the ribbon layer to permit the ribbon to move into the upper chamber or into the lower chamber. The upper chamber is then filled with polysilicon. A silicon nitride layer is formed over the oxide layer and a contact opening is formed down to the ribbon and filled with tungsten that is then patterned to form metal lines. Any exposed silicon nitride is removed. A polysilicon layer is formed over the tungsten lines and anisotropically etched to remove polysilicon on the horizontal surfaces but leave polysilicon sidewall spacers.

Abstract: To enhance and/or improve reliability in a method of forming a semiconductor device. An exemplary method of forming a semiconductor device forms a conductive part within a concave portion which is formed in a first surface of a semiconductor substrate. The semiconductor substrate includes an integrated circuit. The method also thins the substrate by removing a part of a second surface of the semiconductor substrate so as to make the conductive part penetrate from the first surface to the second surface, and cuts the semiconductor substrate into pieces. An electric property of the semiconductor substrate is inspected through the conductive part after the conductive part is formed.

Abstract: A stackable test apparatus is disclosed including a body having a first surface with a raised portion extending from the first surface along a perimeter of the body and a plurality of stacking pins extending away from the first surface arraigned in a stacking pin pattern. Also included is a plurality of stacking pin receivers located on a second surface of the body, the stacking pin receivers arraigned in a pattern to match the stacking pin pattern and sized to accept the stacking pin.

Abstract: The present invention is a system for creating a signature of a substrate manufactured in a semiconductor or data storage fabrication facility. A central processing unit is configured to receive external sensor data from a plurality of equipment-types located within the facility and integrate the external sensor data, by combining the data into a unitary whole, to create the signature for the substrate. Additionally, the present invention is a method for creating a signature of the substrate by selecting a substrate from the facility process line, receiving external sensor data associated with the substrate from a plurality of equipment-types, and integrating the external sensor data associated with the substrate to create the signature of the substrate. The created substrate signature may also be compared with other substrate signatures to electronically diagnose a process, equipment associated with the process, or a processed substrate.

Abstract: A semiconductor wafer protecting unit which enables a semiconductor wafer to be handled as required, without breakage of the semiconductor wafer, even when the back of the semiconductor wafer is ground to decrease the thickness of the semiconductor wafer markedly; and a semiconductor wafer processing method using such a semiconductor wafer protecting unit. The semiconductor wafer protecting unit is composed of a magnetized tape having one surface with tackiness, and a magnetic substrate having many pores formed at least in a central zone thereof.

Abstract: A method, circuit and system for determining burn-in reliability from wafer level burn-in are disclosed. The method according to the present invention includes recording the number of failures in each IC die in nonvolatile elements on-chip at points in time over the duration of wafer level burn-in testing. The number of failures in each IC die, along with their associated points in time, may be used to create burn-in reliability curves which are conventionally derived using other processes that may be less cost effective or not possible to effect with unpackaged IC dice. Circuits and system associated with the method of the present invention are also disclosed.

Abstract: In the manufacturing process of a semiconductor integrated circuit device, a plurality of identification elements having the same arrangement are formed and the relation of magnitude in a physical amount corresponding to variations in the process of the plurality of identification elements is employed as identification information unique to the semiconductor integrated circuit device.

Abstract: Embodiments of the invention provide an apparatus and method to determine the health of a substrate process such as, for example, a pre-clean process using plasma to remove copper oxide from a copper layer on a substrate, and the point at which the process has ended. In one aspect, optical characteristics and/or chamber impedance are used to determine the process end-point and/or process chamber health.

Abstract: The present disclosure pertains to a method of preparing a test specimen for testing of the bonding strength of a layer of additive material to a crystalline substrate, or testing of the bonding strength of one layer of additive material to a second layer of additive material, where both layers of additive material overlie a crystalline substrate. The method includes both test specimen “cutting” from a large sample of material and preparation of an individual test specimen for four-point adhesion testing. Also described is a fixture which is useful for cutting the individual test specimen from the large sample of material.

Abstract: A first set of interferometric measuring beams is used to determine a location of a patterned surface of a reticle and a reticle focus plane for a reticle that is back clamped to a reticle stage. A second set of interferometric measuring beams is used to determine a map of locations of the reticle stage during scanning in a Y direction. The two sets of interferometric measuring beams are correlated to relate the reticle focal plane to the map of the reticle stage. The information is used to control the reticle stage during exposure of a pattern on the patterned surface of the reticle onto a wafer.

Abstract: One embodiment of the present invention provides a system that applies resolution enhancement techniques (RETs) selectively to a layout of an integrated circuit. Upon receiving the layout of the integrated circuit, the system identifies a plurality of critical regions within the layout based on an analysis of one or more of, timing, dynamic power, and off-state leakage current. The system then performs a first set of aggressive RET operations on the plurality of critical regions. The system also performs a second set of less aggressive RET operations on other non-critical regions of the layout.

Abstract: A semiconductor structure is disclosed that enhances quality control inspection of device. The structure includes a substrate having at least one planar face, a first metal layer on the planar face, and covering some, but not all of the planar face in a first predetermined geometric pattern, and a second metal layer on the planar face, and covering some, but not all of the planar face in a second geometric pattern that is different from the first geometric pattern. A quality control method for manufacturing a semiconductor device is also disclosed. The method includes the steps of placing a first metal layer on a semiconductor face of a device in a first predetermined geometric pattern, placing a second metal layer on the same face of the device as the first layer and in a second predetermined geometric pattern that is different from the first geometric pattern, and then inspecting the device to identify the presence or absence of one or both of the patterns on the face.

Abstract: The present invention discloses a method of fabricating and repairing a mask without damage and an apparatus including a holder to mount a substrate; a stage to position the holder in a chamber; a pumping system to evacuate the chamber; an imaging system to locate an opaque defect in the substrate; a gas delivery system to dispense a reactant gas towards the defect; and an electron delivery system to direct electrons towards the opaque defect.

Abstract: A liquid-crystal display device is provided. The liquid-crystal display device comprises a first substrate having a pixel electrode, a signal line, a scanning line, and a driver driving one of the signal line and the scanning line, a second substrate opposing the first substrate and having a common electrode, a liquid-crystal layer formed between the pixel electrode and the common electrode, and a first shield placed opposite the driver so as to shield an electromagnetic wave radiated from the driver.

Abstract: A method and apparatus for a mixed-mode operation of an electrostatic chuck in a semiconductor substrate processing system. The chuck is operated in a voltage mode before and after a processing and is operated in a current mode during the processing to suppress arcing during the processing of a substrate.