Abstract: An array substrate, a manufacturing method thereof and a display device are provided. The array substrate comprises a base substrate, and a gate line and a common electrode provided in the same layer, a gate insulation layer, an active layer, a source electrode and a drain electrode provided in the same layer; and a pixel electrode provided in the same layer as the active layer, sequentially arranged on the base substrate.

Abstract: A light-emitting element includes a light transmissive substrate; a first semiconductor stacked body including: a first n-side semiconductor layer, and a first p-side semiconductor layer, the first p-side semiconductor layer having a hole formed therein; a first p-electrode; a first n-electrode having a portion above the first p-electrode, and a portion extending into the hole, the first n-electrode being electrically connected to the first n-side semiconductor layer through the hole; a second semiconductor stacked body including: a second n-side semiconductor layer located around a periphery of the first semiconductor stacked body, and a second p-side semiconductor layer located above the second n-side semiconductor layer and located outside of an inner edge portion of the second n-side semiconductor layer; a second p-electrode; and a second n-electrode having a portion above the second p-electrode, and being electrically connected to the inner edge portion of the second n-side semiconductor layer.

Abstract: A non-volatile memory device comprises a memory area including a memory cell, and a peripheral area including a circuit that drives the memory cell. The circuit includes a first resistance element. The first resistance element includes a first conductive layer extending in a first direction, a first insulating layer provided on the first conductive layer, and a second conductive layer that includes a portion provided on the first insulating layer and an end portion in contact with the first conductive layer.

Abstract: A method of forming a metallization layer over a semiconductor substrate includes depositing a blanket layer of a diffusion barrier liner over an inter level dielectric layer, and depositing a blanket layer of an intermediate layer over the diffusion barrier liner. A blanket layer of a power metal layer including copper is deposited over the intermediate layer. The intermediate layer includes a solid solution of a majority element and copper. The intermediate layer has a different etch selectivity from the power metal layer. After depositing the power metal layer, structuring the power metal layer, the intermediate layer, and the diffusion barrier liner.

Abstract: The present disclosure relates to a transistor device having an epitaxial carbon layer and/or a carbon implantation region that provides for a low variation of voltage threshold, and an associated method of formation. In some embodiments, the transistor device has an epitaxial region arranged within a recess within a semiconductor substrate. The epitaxial region has a carbon doped silicon epitaxial layer and a silicon epitaxial layer disposed onto the carbon doped silicon epitaxial layer. A gate structure is arranged over the silicon epitaxial layer. The gate structure has a gate dielectric layer disposed onto the silicon epitaxial layer and a gate electrode layer disposed onto the gate dielectric layer. A source region and a drain region are arranged on opposing sides of a channel region disposed below the gate structure.

Abstract: Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.

Abstract: A semiconductor device includes a substrate, upper impurity regions in upper portions of the substrate, metal electrodes electrically connected to the upper impurity regions, metal silicide layers between the metal electrodes and the upper impurity regions, and a lower impurity region in a lower portion of the substrate. A method of fabricating the semiconductor device and an apparatus used in fabricating the semiconductor device is also provided.

Abstract: A method of manufacturing a light emitting device includes providing a light emitting element, a light extracting surface, and a light emitting element lateral surface. A lower mold has an upper surface and a projected portion. The projected portion has a bottom portion. The projected portion has a projected portion upper surface. The projected portion has a projected portion lateral surface provided between the bottom portion and the projected portion upper surface. The light emitting element is arranged on the projected portion such that the light extracting surface contacts the projected portion upper surface. The projected portion lateral surface and the light emitting element lateral surface are covered with a cover member. The lower mold is removed to provide a recessed portion on the light extracting surface surrounded by a sidewall made of the cover member. A first light-transmissive member is provided in the recessed portion.

Abstract: In accordance with some embodiments, a method for forming via holes is provided. The method includes providing a substrate with an etch stop layer and a dielectric layer sequentially formed thereon. The method also includes etching the dielectric layer to form a first via hole of a first size and a second via hole of a second size within the dielectric layer by a plasma generated from an etch gas, until both the first via hole and the second via hole are reaching the etch stop layer. The etch gas includes CH2F2 and an auxiliary gas of N2 or O2.

Abstract: The present examples relate to a semiconductor chip having a level shifter with an electrostatic discharge (ESD) protection circuit and a device applying to multiple power supply lines with high and low power inputs to protect the level shifter from the static ESD stress. More particularly, the present examples relate to using a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device itself.

Abstract: An IC includes first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of tip-to-tip shorts, and the second DOE contains fill cells configured to enable NC detection of corner shorts.

Abstract: Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure are formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose the first source/drain region. At least part of the spacer material is removed to expose the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure.

Abstract: The present disclosure provides a semiconductor structure having an insulating layer positioning on a substrate; a semiconductor fin partially located in the insulating layer; and a metal gate over the semiconductor fin and the insulating layer. The semiconductor fin includes a first region including a first lattice constant and a second region in proximity to the metal gate, including a second lattice constant. At least one dislocation is located only in the second region of the semiconductor fin. The present disclosure provides a method for manufacturing a semiconductor structure, including forming a gate over a first semiconductor layer, removing a portion of the first semiconductor layer in proximity to a sidewall of the gate and obtaining a recess, and forming a second semiconductor layer in the recess. At least one dislocation is in-situ formed in the second semiconductor layer without extending to the first semiconductor layer.

Abstract: An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one GATE-short-related failure mode, one GATECNT-short-related failure mode, and one metal-short-related failure mode.

Abstract: A display apparatus includes a first substrate including a first display region and a first non-display region, a first display device in the first display region of the first substrate, a second substrate including a second display region and a second non-display region, the second display region overlapping the first non-display region of the first substrate, and a second display device in the second display region of the second substrate.

Abstract: A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.

Abstract: In various embodiments, light-emitting devices incorporate graded layers with compositional offsets at one or both end points of the graded layer to promote formation of two-dimensional carrier gases and polarization doping, thereby enhancing device performance.

Abstract: The present invention discloses a packaging device and a packaging method and relates to a field of manufacturing technique of a display panel. The packaging device is used to package a display panel, the display panel comprising a first substrate and a second substrate that are arranged opposed to each other and are able to be packaged by a sealing material, the packaging device comprising a first adsorption part and a second adsorption part that are able to attract each other through a magnetic force, one of the first adsorption part and the second adsorption part configured to be detachably arranged on the outside of the first substrate, and the other of the first adsorption part and the second adsorption part configured to be detachably arranged on the outside of the second substrate.

Abstract: There is provided an electronic device and a method for its manufacture. The device comprises an elongate silicon nanowire less than 0.5 ?m in cross-sectional dimensions and having a hexagonal cross-sectional shape due to annealing-induced energy relaxation. The method, in examples, includes thinning the nanowire through iterative oxidation and etching of the oxidized portion.

Abstract: The present invention relates to the growing of nitride semiconductors, applicable for a multitude of semiconductor devices such as diodes, LEDs and transistors. According to the method of the invention nitride semiconductor nanowires are grown utilizing a CVD based selective area growth technique. A nitrogen source and a metal-organic source are present during the nanowire growth step and at least the nitrogen source flow rate is continuous during the nanowire growth step. The V/III-ratio utilized in the inventive method is significantly lower than the V/III-ratios commonly associated with the growth of nitride based semiconductor.