Abstract: A solar cell includes a metal layer and a chalcopyrite compound semiconductor layer in this order on a polyimide film. A manufacturing method according to the present invention includes the following steps in the order: cast applying a polyimide precursor solution onto a support base containing an alkali metal; imidizing the polyimide precursor by heating to form a stacked body including a polyimide film on the support base; forming a metal layer on the polyimide film of the stacked body; and forming a chalcopyrite compound semiconductor layer on the metal layer.

Abstract: A cascoded junction field transistor (JFET) device comprises a first stage high voltage JFET cascoded to a second stage low voltage JFET wherein one of the first and second stages JFET is connected to a drain electrode of another JFET stage.

Abstract: A display substrate is provided, the display substrate comprising at least one pixel unit, the pixel unit including a pixel driving circuit (A2) located in an active driving circuit backplane, and a light-emitting diode chip (A1) disposed on the active driving circuit backplane; the light-emitting diode chip (A1) being electrically connected with the pixel driving circuit (A2). And a manufacturing method of the display substrate, and a display device comprising the display substrate are further provided.

Abstract: A chip includes a core layer, at least one redistribution layer formed on the core layer, and at least one triple pad connected to a pad of the core layer through the at least one redistribution layer or at least one via connected to the at least one redistribution layer. The at least one triple pad includes a bonding pad, a redistribution layer pad connected to the at least one redistribution layer, and a test pad configured to perform a wafer level test. The bonding pad, the redistribution layer pad and the test pad are connected to one another through the at least one redistribution layer, and the test pad is disposed in a core area that overlaps the core layer.

Abstract: Methods are provided for fabricating photovoltaic cell contacts, which include: providing a block copolymer layer above an electrical contact layer of the photovoltaic cell, the block copolymer layer being self-assembled by phase segregation to include multiple structures of a first polymer material surrounded, at least in part, by a second polymer material; selectively etching the block copolymer layer to remove the multiple structures, forming holes in the block copolymer layer; and using the holes in the block copolymer layer to facilitate providing electrical contacts between a light absorption layer of the photovoltaic cell and the electrical contact layer. For instance, the holes in the copolymer layer may be used in etching a passivation layer over the electrical contact layer to form nano-sized contact openings in the passivation layer to the contact layer. Once provided, the cell's light absorption material forms contacts extending through the contact openings in the passivation layer.

Abstract: A mechanism of a semiconductor structure with composite barrier layer under redistribution layer is provided. A semiconductor structure includes a substrate comprising a top metal layer on the substrate; a passivation layer over the top metal layer having an opening therein exposing the top metal layer; a composite barrier layer over the passivation layer and the opening, the composite barrier layer includes a center layer, a bottom layer, and an upper layer, wherein the bottom layer and the upper layer sandwich the center layer; and a redistribution layer (RDL) over the composite barrier layer and electrically connecting the underlying top metal layer.

Abstract: A wafer is transferred to a holding surface of a chuck table by using a transfer unit having a suction pad. The front side of the wafer is held under suction through a protective tape on the holding surface, and the suction pad is removed from the back side of the wafer. A modified layer is formed on the back side of the wafer along division lines. The wafer is transferred by mounting the wafer held by the suction pad on the holding surface and sandwiching the wafer between the suction pad and the holding surface of the chuck table. A suction force is applied to the holding surface of the chuck table to thereby hold the front side of the wafer through the protective tape on the holding surface of the chuck table under suction, and the suction pad is then removed from the back side of the wafer.

Abstract: The present invention relates to a method of manufacturing a ferrite rod. The method comprises etching cavities into two semiconductor substrates and depositing ferrite layers into the cavities. The semiconductor substrates are attached to each other such that the ferriote layers form a ferrite rod. The present invention employs conventional photolithography and bulk isotropic micromachining of semiconductor wafers to precisely and repeatably form a template or mold, into which magnetic material can be deposited to form a Faraday rotation or phase-shifting element.

Abstract: A flexible display device comprises a back plate coupled to a rear surface of a flexible display panel with a bending portion, having an opening portion overlapped with the bending portion; and a buffer member covering inner sides of the back plate, which are provided by the opening portion.

Abstract: A semiconductor nanowire device includes at least one semiconductor nanowire having a bottom surface and a top surface, an insulating material which surrounds the semiconductor nanowire, and an electrode ohmically contacting the top surface of the semiconductor nanowire. A contact of the electrode to the semiconductor material of the semiconductor nanowire is dominated by the contact to the top surface of the semiconductor nanowire.

Abstract: In various embodiments, light-emitting devices incorporate graded layers with compositional offsets at one or both end points of the graded layer to promote formation of two-dimensional carrier gases and polarization doping, thereby enhancing device performance.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first flowable-material (FM) layer over a substrate. A top surface of the first FM layer in a first region is higher than a top surface of the first FM layer in a second region. The method also includes forming a sacrificial plug to cover the first FM layer in the first region, forming a second FM layer over the sacrificial plug in the first region and over the first FM layer in the second region, performing a first recessing process such that the second FM layer is removed in the first region and performing a second recessing process on the second FM layer in the second region while the first FM layer is protected by the sacrificial plug in the first region.

Abstract: In accordance with some embodiments, a semiconductor device is provided. The semiconductor device structure includes a substrate, and the substrate has a device region and an edge region. The semiconductor device structure also includes a silicon layer formed on the substrate and a transistor formed on the silicon layer. The transistor is formed at the device region of the substrate. The semiconductor device structure further includes a metal ring formed in the silicon layer. The metal ring is formed at the edge region of the substrate, and the transistor is surrounded by the metal ring.

Abstract: A method of forming an integrated DMOS transistor/EEPROM cell includes forming a first mask over a substrate, forming a drift implant in the substrate using the first mask to align the drift implant, simultaneously forming a first floating gate over the drift implant, and a second floating gate spaced apart from the drift implant, forming a second mask covering the second floating gate and covering a portion of the first floating gate, forming a base implant in the substrate using an edge of the first floating gate to self-align the base implant region, and simultaneously forming a first control gate over the first floating gate and a second control gate over the second floating gate. The first floating gate, first control gate, drift implant, and base implant form components of the DMOS transistor, and the second floating gate and second control gate form components of the EEPROM cell.

Abstract: An array substrate, a manufacturing method thereof and a display device are provided. The array substrate comprises a base substrate, and a gate line and a common electrode provided in the same layer, a gate insulation layer, an active layer, a source electrode and a drain electrode provided in the same layer; and a pixel electrode provided in the same layer as the active layer, sequentially arranged on the base substrate.

Abstract: A system is described for time synchronizing digitized measurement signals, such as vibration signals. The digitized signals, which are acquired asynchronously by multiple distributed measurement units, indicate the operational condition of a machine or a process. To measure the phase of the digitized signals relative to a pulse tachometer input, the time between the leading edge of the tachometer pulse and the digitized samples is measured. To achieve phase-coherent synchronization across the distributed measurement units, a local synchronization signal is embedded into the data produced by the measurement units. The systems uses the synchronization signal to align the data in post processing, which phase aligns the data and aligns the data in absolute time. The synchronization signal may be encoded with a timestamp to provide additional timing information.

Abstract: A light-emitting element includes a light transmissive substrate; a first semiconductor stacked body including: a first n-side semiconductor layer, and a first p-side semiconductor layer, the first p-side semiconductor layer having a hole formed therein; a first p-electrode; a first n-electrode having a portion above the first p-electrode, and a portion extending into the hole, the first n-electrode being electrically connected to the first n-side semiconductor layer through the hole; a second semiconductor stacked body including: a second n-side semiconductor layer located around a periphery of the first semiconductor stacked body, and a second p-side semiconductor layer located above the second n-side semiconductor layer and located outside of an inner edge portion of the second n-side semiconductor layer; a second p-electrode; and a second n-electrode having a portion above the second p-electrode, and being electrically connected to the inner edge portion of the second n-side semiconductor layer.

Abstract: A method of forming a metallization layer over a semiconductor substrate includes depositing a blanket layer of a diffusion barrier liner over an inter level dielectric layer, and depositing a blanket layer of an intermediate layer over the diffusion barrier liner. A blanket layer of a power metal layer including copper is deposited over the intermediate layer. The intermediate layer includes a solid solution of a majority element and copper. The intermediate layer has a different etch selectivity from the power metal layer. After depositing the power metal layer, structuring the power metal layer, the intermediate layer, and the diffusion barrier liner.

Abstract: A non-volatile memory device comprises a memory area including a memory cell, and a peripheral area including a circuit that drives the memory cell. The circuit includes a first resistance element. The first resistance element includes a first conductive layer extending in a first direction, a first insulating layer provided on the first conductive layer, and a second conductive layer that includes a portion provided on the first insulating layer and an end portion in contact with the first conductive layer.

Abstract: The present disclosure relates to a transistor device having an epitaxial carbon layer and/or a carbon implantation region that provides for a low variation of voltage threshold, and an associated method of formation. In some embodiments, the transistor device has an epitaxial region arranged within a recess within a semiconductor substrate. The epitaxial region has a carbon doped silicon epitaxial layer and a silicon epitaxial layer disposed onto the carbon doped silicon epitaxial layer. A gate structure is arranged over the silicon epitaxial layer. The gate structure has a gate dielectric layer disposed onto the silicon epitaxial layer and a gate electrode layer disposed onto the gate dielectric layer. A source region and a drain region are arranged on opposing sides of a channel region disposed below the gate structure.