Abstract: An estimate of voltage regulator input power is provide by estimating output power of the voltage regulator based on output voltage and output current of the voltage regulator, estimating power loss of the voltage regulator and estimating input power of the voltage regulator based on the estimated output power and the estimated power loss.

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

Abstract: An optoelectronic semiconductor component and a method for manufacturing an optoelectronic semiconductor component are disclosed. In an embodiment, the component includes a plurality of active regions configured to generate a primary radiation and a plurality of luminescent material particles configured to convert the primary radiation into a secondary radiation, wherein the active regions are arranged spaced apart from each other, wherein each active region has a main extension direction, wherein each active region has a core region comprising a first semiconductor material, wherein each active region has an active layer covering the core region, wherein each active region has a cover layer comprising a second semiconductor material and covering the active layer, wherein at least some of the luminescent material particles are arranged between the active regions, and wherein a diameter of a majority of the luminescent material particles is smaller than a distance between two adjacent active regions.

Abstract: A thermoelectric structure that may be included in a thermoelectric device may include a thin-film structure that may include a plurality of thin-film layers. The thin-film structure may include Tellurium. The thin-film structure may be on a substrate. The substrate may include an oxide, and a buffer layer may be between the substrate and the thin-film structure. The thermoelectric structure may be manufactured via depositing material ablated from a target onto the substrate. Some material may react with the substrate to form the buffer layer, and thin film layers may be formed on the buffer layer. The thin film layers may be removed from the substrate and provided on a separate substrate. Removing the thin-film layers from the substrate may include removing the thin-film layers from the buffer layer.

Abstract: An improvement is achieved in the performance of a semiconductor device. Over a first insulating film formed over a main surface of a semiconductor substrate located in a memory formation region and having an internal charge storage portion and over a second insulating film formed over the main surface of the semiconductor substrate located in a main circuit formation region, a conductive film is formed. Then, in the memory formation region, the conductive film and the first insulating film are patterned to form a first gate electrode and a first gate insulating film while, in the main circuit formation region, the conductive film and the second insulating film are left. Then, in the main circuit formation region, the conductive film and the second insulating film are patterned to form a second gate electrode and a second gate insulating film.

Abstract: A light emitting diode (LED) includes a plurality of Group III-nitride nanowires extending from a substrate, at least one Group III-nitride pyramidal shell layer located on each of the plurality of Group III-nitride nanowires, a continuous Group III-nitride pyramidal layer located over the at least one Group III-nitride pyramidal shell layer, and a continuous pyramidal contact layer located over the continuous Group III-nitride pyramidal layer. The at least one Group III-nitride pyramidal shell layer is located in an active region of the LED. The plurality of Group III-nitride nanowires are doped one of n- or p-type. The continuous Group III-nitride pyramidal layer is doped another one of p- or n-type to form a junction with the plurality of Group III-nitride nanowires. A distance from a side portion of the continuous contact layer to the plurality of Group III-nitride nanowires is shorter than a distance of an apex of the continuous contact layer to the plurality of Group III-nitride nanowires.

Abstract: In one embodiment, an overvoltage protection device may include a semiconductor substrate comprising an n-type body region. The overvoltage protection device may further include a first p-type region disposed in a first surface region of the semiconductor substrate, and forming a first P/N junction with the n-type body region, and a second p-type region disposed in a second surface region of the semiconductor substrate opposite the first surface, and forming a second P/N junction with the n-type body region, wherein the n-type body region, first p-type region, and second p-type region form a breakdown device having a breakdown voltage greater than 100 V when an external voltage is applied between the first surface region and second surface region.

Abstract: Embodiments of the present invention provide a thin film transistor and a manufacturing method thereof, an array substrate including the thin film transistor, and a manufacturing method of the array substrate. The thin film transistor comprises an active layer, a gate insulation layer, a gate, an interlayer insulation layer, a source and a drain formed on a base substrate, the interlayer insulation layer and the gate insulation layer are provided therein with through holes corresponding to the source and the drain; the active layer comprises a source ohmic contact region connected with the source, a drain ohmic contact region connected with the drain, a channel region serving as a channel located below the gate, and a lightly doped region between the drain ohmic contact region and the channel region.

Abstract: A process for making an integrated circuit, either in the form of a wafer, die, or chip, includes instantiating multiple standard cell-compatible fill cells, configured to enable non-contact electrical measurements. Such instantiated fill cells include mesh pads that contain at least three conductive stripes disposed between adjacent gate stripes. Such instantiated fill cells further include geometry to enable non-contact evaluation of Tip-to-Side shorts and/or leakages.

Abstract: An embodiment is MEMS device including a first MEMS die having a first cavity at a first pressure, a second MEMS die having a second cavity at a second pressure, the second pressure being different from the first pressure, and a molding material surrounding the first MEMS die and the second MEMS die, the molding material having a first surface over the first and the second MEMS dies. The device further includes a first set of electrical connectors in the molding material, each of the first set of electrical connectors coupling at least one of the first and the second MEMS dies to the first surface of the molding material, and a second set of electrical connectors over the first surface of the molding material, each of the second set of electrical connectors being coupled to at least one of the first set of electrical connectors.

Abstract: An integrated circuit, in the form of a wafer, die, or chip, includes multiple standard cell-compatible fill cells, configured to enable non-contact electrical measurements. Such fill cells include mesh pads that contain at least three conductive stripes disposed between adjacent gate stripes. Such fill cells further include geometry to enable non-contact evaluation of snake opens and/or resistances.

Abstract: A semiconductor memory device includes a stacked body including a first electrode layer and a second electrode layer stacked on the first electrode layer, and first and second interconnections on a first surface of the stacked body. The first and second electrode layers have first and second end surfaces respectively in the first surface. The first interconnection is electrically connected to the first electrode layer through a first region of the first end surface; and the second interconnection is electrically connected to the second electrode layer through a second region of the second end surface. The first and second interconnections extend in a first direction on the first surface. The first and second regions are arranged in a second direction crossing the first direction with a crossing angle smaller than 90 degrees. The first region and the second region each have a boundary along the second direction.

Abstract: A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.

Abstract: A semiconductor package includes a semiconductor die comprising a control transistor and a sync transistor, an integrated output inductor comprising a winding around a core, and coupled to the semiconductor die. The winding comprises a plurality of conductive clips situated above a printed circuit board (PCB) and connected to a plurality of conductive segments in the PCB. The control transistor and the sync transistor are configured as a half-bridge. The integrated output inductor is coupled to a switched node of the half-bridge. At least one of the plurality of conductive clips includes a partially etched portion and a non-etched portion. The semiconductor die is attached to the integrated output inductor by a die attach material. The semiconductor die and the integrated output inductor are encapsulated in a molding compound.

Abstract: An integrated circuit, in the form of a wafer, die, or chip, includes multiple standard cell-compatible fill cells, configured to enable non-contact electrical measurements. Such fill cells include mesh pads that contain at least three conductive stripes disposed between adjacent gate stripes. Such fill cells further include geometry to enable non-contact evaluation of corner shorts and/or leakages.

Abstract: An integrated circuit, in the form of a wafer, die, or chip, includes multiple standard cell-compatible fill cells, configured to enable non-contact electrical measurements. Such fill cells include mesh pads that contain at least three conductive stripes disposed between adjacent gate stripes. Such fill cells further include geometry to enable non-contact evaluation of via opens and/or resistances.

Abstract: Methods of forming self-aligned non-mandrel cuts during the fabrication of an interconnect structure. A first dielectric hardmask layer is formed on a metal hardmask layer. A plurality of mandrels are formed on the first dielectric hardmask layer, and a plurality of spacers are formed on the first dielectric hardmask layer. The spacers are located adjacent to the mandrels. A first sacrificial layer is formed that fills spaces between the spacers, and a second dielectric hardmask layer is formed on the first sacrificial layer, the spacers, and the mandrels. A plurality of sections of a second sacrificial layer are formed on the second dielectric hardmask layer and cover the second dielectric hardmask layer over a plurality of areas that are used to form the non-mandrel cuts.

Abstract: In a semiconductor device including an oxide semiconductor, a change in electrical characteristics is inhibited and reliability is improved. The semiconductor device is manufactured by a method including first to fourth steps. The first step includes a step of forming an oxide semiconductor film, the second step includes a step of forming an oxide insulating film over the oxide semiconductor film, the third step includes a step of forming a protective film over the oxide insulating film, and the fourth step includes a step of adding oxygen to the oxide insulating film through the protective film. In the first step, the oxide semiconductor film is formed under a condition in which an oxygen vacancy is formed. The oxygen from the oxide insulating film fills the oxygen vacancy after the fourth step.

Abstract: A process for making an integrated circuit, either in the form of a wafer, die, or chip, includes instantiating multiple standard cell-compatible fill cells, configured to enable non-contact electrical measurements. Such instantiated fill cells include mesh pads that contain at least three conductive stripes disposed between adjacent gate stripes. Such instantiated fill cells further include geometry to enable non-contact evaluation of interlayer overlap shorts and/or leakages.

Abstract: The present disclosure relate to an integrated chip having long-channel and short-channel transistors having channel regions with different doping profiles. In some embodiments, the integrated chip includes a first gate electrode arranged over a first channel region having first length, and a second gate electrode arranged over a second channel region having a second length greater than the first length. The first channel region and the second channel region have a dopant profile, respectively along the first length and the second length, which has a dopant concentration that is higher by edges than in a middle of the first channel region and the second channel region. The dopant concentration is also higher by the edges of the first channel region than by the edges of the second channel region.