Abstract: According to one embodiment, a memory controller includes a first controller issuing one command which includes read commands for reading data from a nonvolatile memory, a second controller sequentially issuing the read commands and a dummy command which continues the read commands when the one command is received, and a third controller sequentially executing the read commands and the dummy command and informing an information of a read error to the second controller when the read error occurred, the second controller informing a completion of the one command to the first controller when the command which corresponds to the read error is the dummy command.

Abstract: A pseudo-dual-port (PDP) memory system includes a memory array, timing and control logic, and multiplexer-latch (MUX-latch). The MUX-latch comprises integrated address selection logic and latching logic, such that the combination multiplexes and latches an address in a single change in response to a state change in the read select or write select signals. The multiplexing and latching defines a single operation or state change in the MUX-latch. Since the multiplexing delay and the latching delay for a read operation are coincident with each other rather than being incurred one after the other, memory read operations are fast.

Abstract: A method and apparatus for selective calibrations of a memory subsystem is disclosed. The memory subsystem includes a memory and a memory controller. The memory controller is configured to periodically perform calibrations of a data strobe signal conveyed to the memory and a reference voltage used to distinguish between a logic 0 and a logic 1. The memory subsystem is also coupled to receive a clock signal (e.g., at the memory controller). If a pending change of frequency of the clock signal is indicated to the memory controller during performance of a periodic calibration, the reference voltage calibration may be aborted prior to or during the performance thereof, while the data strobe calibration may be completed.

Abstract: Apparatus and method for placing data based on the content of the data in random access memory such that indexing operations are not required. A strong (e.g., cryptographic) hash is applied to a data element resulting in a signature. A weaker hash function is then applied to the signature to generate a storage location in memory for the data element. The weaker hash function assigns multiple data elements to the same storage location while the signature comprises a unique identifier for locating a particular data element at this location. In one embodiment a plurality of weak hash functions are applied successively to increase storage space utilization. In other embodiments, the assigned storage location can be determined by one or more attributes of the data element and/or the storage technology, e.g, long-lived versus short-lived data and/or different regions of the memory having different performance (e.g., access latency memory lifetime) characteristics.

Abstract: A method of processing input/output (I/O) in a storage device includes adjusting a read anticipation time based on a change of a resource management status related to operations of the storage device and performing an I/O processing operation at the storage device based on the adjusted read anticipation time. The I/O processing operation is performed to postpone an operation regarding a program command and perform a read command at higher priority than a write command at the storage device in a period from completion of a read operation at the storage device until the read anticipation time has elapsed.

Abstract: In addition to caching I/O operations at a host, at least some data management can migrate to the host. With host side caching, data sharing or deduplication can be implemented with the cached writes before those writes are supplied to front end storage elements. When a host cache flush to distributed storage trigger is detected, the host deduplicates the cached writes. The host aggregates data based on the deduplication into a “change set file” (i.e., a file that includes the aggregation of unique data from the cached writes). The host supplies the change set file to the distributed storage system. The host then sends commands to the distributed storage system. Each of the commands identifies a part of the change set file to be used for a target of the cached writes.

Abstract: Techniques are described for formally expressing whether sequences of operations performed on block storage devices are sequential or random. In embodiments, determinations of whether these sequences of operations are sequential or random may be used to predict latencies involved with running particular workloads, and to predict representative workloads for particular latencies.

Abstract: An address translation capability in which information is obtained from an address translation structure to be used to translate a first address to a second address, the first address being of a first address type and the second address being of a second address type. The address translation structure includes a first set of information to translate the first address to one address of the second address type and a second set of information to translate the first address to another address of the second address type. To obtain the information, the first set of information or the second set of information is selected as the information to be used to translate the first address to the second address, based on an attribute of the first address.

Abstract: An address translation capability in which information is obtained from an address translation structure to be used to translate a first address to a second address, the first address being of a first address type and the second address being of a second address type. The address translation structure includes a first set of information to translate the first address to one address of the second address type and a second set of information to translate the first address to another address of the second address type. To obtain the information, the first set of information or the second set of information is selected as the information to be used to translate the first address to the second address, based on an attribute of the first address.

Abstract: In one embodiment, a system includes a back-end storage device, a cache storage device, and a processor and logic integrated with and/or executable by the processor. The logic is configured to store data to the cache storage device using fine block descriptors (FBDs) configured for fine-grained mapping of variable-size cache allocations. The logic is also configured to store data to the back-end storage device using cache block descriptors (CBDs) configured for coarse-grained mapping of large blocks of data. At least some FBDs are smaller in size than any of the CBDs, and all FBDs are equal to or smaller in size than any of the CBDs.

Abstract: Data access is monitored in order to calculate priorities for extents of data based on extent access activity and priority of a business process associated with the extent. The priorities of the extents are used to generate priority hints for a tiered storage array. The priority may be time-dependent, including being indicative of anticipated future activity.

Abstract: A mechanism is provided for object-based storage management. A detection is made of an event being performed on or by the object. A determination is made as to whether the event meets with one or more rules in a set of rules that identify a backup or replication needing to be performed. Responsive to determining that the event meets with one or more rules in the set of rules that identify the backup or replication needing to be performed, an indication is made in a backup/replication field in metadata of the object that the backup and/or replication of the object needs to be performed. The indication in the backup/replication field in the metadata of the object causes one or more portions of the object to be backed up and/or replicated.

Abstract: A primary physical storage device has effectively limitless apparent free space. Responsive to receiving a request to dynamically allocate an amount of desired free space on the primary device to store new data on the primary device, and responsive to determining that an amount of actual free space on the primary device is insufficient to permit such allocation, existing data stored on the primary device is moved to a secondary storage device. The first existing data appears to still be stored on the primary device. Responsive to receiving a request to retrieve existing data from the primary device, and to determining that the existing data has been moved to the secondary device, the existing data is moved back to the primary device. The existing data was originally stored on the primary device, and is currently stored on the primary device or has been moved to the secondary device.

Abstract: A group address range is mapped to a memory address range of a nonvolatile memory. A first memory address of the memory address range is to be copied to a volatile memory if the first memory address is mapped to the group address range and a write access is requested for the first memory address. The group address range is transferred from a first node to a second node in response to a synch command. The copied address is to be written the NVM after the group address range is transferred.

Abstract: Method and apparatus for storing records in non-uniform access memory. In various embodiments, the placement of records is localized in one or more regions of the memory. This can be accomplished utilizing different ordered lists of hash functions to preferentially map records to different regions of the memory to achieve one or more performance characteristics or to account for differences in the underlying memory technologies. For example, one ordered list of hash functions may localize the data for more rapid access. Another list of hash functions may localize the data that is expected to have a relatively short lifetime. Localizing such data may significantly improve the erasure performance and/or memory lifetime, e.g., by concentrating the obsolete data elements in one location. Thus, the two or more lists of ordered hash functions may improve one or more of access latency, memory lifetime, and/or operation rate.

Abstract: A method includes, in a memory including analog memory cells, storing first data in a group of the memory cells using a first type of storage command that writes respective analog values to the memory cells in the group. Second data is stored in the memory cells in the group, in addition to the first data, using a second type of storage command that modifies the respective analog values of the memory cells in the group. Upon detecting imminent interruption of electrical power to the memory during storage of the second data, a switch is made to perform an alternative storage operation that is faster than the second type of storage command and protects at least the first data from the interruption.

Abstract: A method begins by a dispersed storage (DS) processing module monitoring processing status of a plurality of pending dispersed storage network (DSN) access requests, where less than a desired number of DS units have favorably responded to a set of access requests. The method continues with the DS processing module interpreting the processing status of the plurality of pending DSN access requests to detect a processing anomaly. The method continues with the DS processing module reprioritizing further processing of at least one of the plurality of pending DSN access requests having the processing anomaly and another one or more of the plurality of pending DSN access requests. The method continues with the DS processing module sending notice of the reprioritized further processing to one or more DS units.

Abstract: A computing node includes an active Non-Volatile Random Access Memory (NVRAM) component which includes memory and a sub-processor component. The memory is to store data chunks received from a processor core, the data chunks comprising metadata indicating a type of post-processing to be performed on data within the data chunks. The sub-processor component is to perform post-processing of said data chunks based on said metadata.

Abstract: When an update instruction for updating task data stored in a memory is transmitted through a transaction process performed by an application server, an active node apparatus generates, based on the update instruction, an update log indicating update contents of the task data stored in the memory, and then distributes, in a multicast manner, the generated update log to other standby node apparatuses each with a memory. With this, mirroring among the plurality of memories is controlled.

Abstract: A modular block allocator receives a cleaner message requesting dirty buffers associated with an inode be cleaned. The modular block allocator provides at least one bucket cache comprising a plurality of buckets, wherein each bucket represents a plurality of free data blocks. The dirty buffers are cleaned by allocating the data blocks of one of the buckets to the dirty buffers. The allocated data blocks are mapped to a stripe set and when the stripe set is full, the stripe set is sent to a storage system. In one embodiment of the invention, a modular block allocator includes a front end module and a back end module communicating with each other via an application programming interface (API). The front end module contains write allocation policies that define how blocks are laid out on disk. The back end module creates data structures for execution of the policies.