Patents Examined by Andy Huynh
  • Patent number: 11043382
    Abstract: Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The method may include the steps of selecting a diamond semiconductor material having a surface, exposing the surface to a source gas in an etching chamber, forming a carbide interface contact layer on the surface; and forming a metal layer on the interface layer.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: June 22, 2021
    Assignee: AKHAN SEMICONDUCTOR, INC.
    Inventor: Adam Khan
  • Patent number: 11037897
    Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: June 15, 2021
    Assignee: Rohm Co., Ltd.
    Inventors: Tadahiro Morifuji, Shigeyuki Ueda
  • Patent number: 11024634
    Abstract: A method of making a semiconductor device includes forming a first memory device, connecting a first word line to the first memory device, forming at least a first via, forming a second memory device, connecting a second word line to the second memory device, connecting a bit line to the first memory device and connecting the bit line to the second memory device by the first via. The first and second memory devices are separated by an inter-layer dielectric, and the first via connects the first memory device and the second memory device.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Hsien Huang, Hong-Chen Cheng, Cheng Hung Lee, Hung-Jen Liao
  • Patent number: 10998377
    Abstract: The present disclosure provides a semiconductor structure, including a memory region, a first metal line in the memory region, a magnetic tunneling junction (MTJ) cell over the first metal line, a carbon-based layer between the first metal line and the MTJ cell, a second metal line over the MTJ cell, a logic region adjacent to the memory region, wherein the logic region is free from a coverage of the carbon-based layer.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Harry-Hak-Lay Chuang, Sheng-Huang Huang, Keng-Ming Kuo, Hung Cho Wang
  • Patent number: 10991677
    Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection hump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: April 27, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-kyoung Seo, Cha-jea Jo, Soo-hyun Ha
  • Patent number: 10978471
    Abstract: A semiconductor memory device includes first structure bodies and second structure bodies arranged alternately along a first direction. The first structure body includes electrode films arranged along a second direction. The second structure body includes columnar members, first insulating members, and second insulating members. The columnar member includes a semiconductor member extending in the second direction and a charge storage member provided between the semiconductor member and the electrode film. The second insulating members are arranged along a third direction. Lengths in the first direction of the second insulating members are longer than lengths in the first direction of the first insulating members. Positions of the second insulating members in the third direction are different from each other between the second structure bodies adjacent to each other in the first direction. The columnar members and the first insulating members are arranged alternately between the second insulating members.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: April 13, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Keisuke Nakatsuka
  • Patent number: 10978618
    Abstract: A semiconductor light emitting device includes a light emitting structure having a first conductivity-type semiconductor layer, an active layer and a second conductivity-type semiconductor layer, a transparent electrode layer on the second conductivity-type semiconductor layer and spaced apart from an edge of the second conductivity-type semiconductor layer, a first insulating layer on the light emitting structure to cover the transparent electrode layer and including a plurality of holes connected to the transparent electrode layer, and a reflective electrode layer on the first insulating layer and connected to the transparent electrode layer through the plurality of holes.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: April 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: JuHeon Yoon, Jung Hwan Kil, Tae Hun Kim, Hwa Ryong Song, Jae In Sim
  • Patent number: 10978422
    Abstract: A method includes forming a fin structure over a semiconductor substrate; forming a liner covering the fin structure; etching back the liner to expose an upper portion of the fin structure; forming a spacer covering the upper portion of the fin structure; etching the liner to expose a middle portion of the fin structure, wherein the remaining liner covers a lower portion of the fin structure; etching the middle portion of the fin structure; and forming a first source/drain structure surrounding the middle portion of the fin structure.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Sheng Yun, Shao-Ming Yu, Chih-Chieh Yeh
  • Patent number: 10971489
    Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: April 6, 2021
    Assignee: STMicroelectronics SA
    Inventor: Johan Bourgeat
  • Patent number: 10971659
    Abstract: There is provided a white light emitting device comprising: first and second LEDs operable to generate excitation light having a dominant wavelength in a range from 440 nm to 480 nm and mounted on a substrate; a first photoluminescence material which generates light having a peak emission wavelength in a range from 500 nm to 590 nm; and a second photoluminescence material which generates light having a peak emission wavelength in a range from 600 nm to 650 nm, wherein the first LED is covered by the first photoluminescence material, and the second LED is covered by the first and second photoluminescence materials.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: April 6, 2021
    Assignee: Bridgelux, Inc.
    Inventor: Tao Xu
  • Patent number: 10957853
    Abstract: Embodiments of the invention are directed to a method to modify material properties of a functional material of a nanoscale device post-fabrication. The method includes performing one or more conditioning steps. The conditioning steps include applying electrical conditioning signals of predefined form to the nanoscale device, thereby performing an in-situ heating of the functional material and inducing thermally a displacement of atoms, molecules or ions of the functional material of the nanoscale device. Embodiments of the invention further concerns a related electronic device.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Iason Giannopoulos, Abu Sebastian, Vara S. P. Jonnalagadda
  • Patent number: 10950656
    Abstract: A method for fabricating a semiconductor memory device is provided. The method includes: etching a first region of the semiconductor memory device to expose a first capping layer; forming a second capping layer on the first capping layer; etching a portion of the first capping layer and a portion of the second capping layer to form a first trench reaching a first metal line; and forming a second metal line in the first trench to contact the first metal line.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Harry-Hak-Lay Chuang, Sheng-Huang Huang, Shih-Chang Liu, Chern-Yow Hsu
  • Patent number: 10950735
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer and a first layer. The semiconductor layer includes a first portion including a first element and oxygen. The first element includes at least one selected from the group consisting of In, Ga, Zn, Al, Sn, Ti, Si, Ge, Cu, As, and W. The first layer includes a second element including at least one selected from the group consisting of W, Ti, Ta, Mo, Cu, Al, Ag, Hf, Au, Pt, Pd, Ru, Y, V, Cr, Ni, Nb, In, Ga, Zn, and Sn. The first portion includes a first region and a second region. The second region is provided between the first region and the first layer. The first region includes a bond of the first element and oxygen. The second region includes a bond of the first element and a metallic element.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: March 16, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Junji Kataoka, Tomomasa Ueda, Tomoaki Sawabe, Keiji Ikeda, Nobuyoshi Saito
  • Patent number: 10943875
    Abstract: A method comprising bonding a first substrate to a second substrate. The first substrate includes a layer of one or more pairs of reactive material. The method comprising triggering a reaction between the one or more pairs of reactive material and fragmenting the second substrate.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: March 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Kenneth P. Rodbell
  • Patent number: 10937802
    Abstract: Various embodiments include methods and apparatus having a number of charge trap structures, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric region, the blocking dielectric region located on a charge trap region of the charge trap structure. At least a portion of the gate can be separated by a void from a region which the charge trap structure is directly disposed. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: March 2, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Chris M. Carlson
  • Patent number: 10930576
    Abstract: A micro-electromechanical system (MEMS) device includes a support structure comprising a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a conductive layer coupled to the first adhesion layer, a second adhesion layer coupled to the conductive layer, and a barrier layer coupled to the second adhesion layer. The support structure defines a cavity. The MEMS device also includes a III-V membrane coupled to a portion of the support structure. A portion of the III-V membrane is suspended over the cavity defined by the support structure and defines a MEMS structure.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: February 23, 2021
    Assignee: QROMIS, INC.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens, Ozgur Aktas
  • Patent number: 10930785
    Abstract: A semiconductor device is provided. The semiconductor device includes a base substrate; a first dielectric layer on the base substrate; a target gate structure in the first dielectric layer and on the base substrate. The target gate structure includes a target structure body and a target spacer wall on sidewalls of the target gate structure body. The semiconductor device further includes a protective layer on a top surface of the target gate structure, in the first dielectric layer. The semiconductor device further includes conductive plugs in the first dielectric layer on sides of the target gate structure and the protective layer.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: February 23, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Yong Li
  • Patent number: 10930652
    Abstract: Methods of forming semiconductor device structures include forming trenches in an array region and in a buried digit line end region, forming a metal material in the trenches, filling the trenches with a mask material, removing the mask material in the trenches to expose a portion of the metal material, and removing the exposed portion of the metal material. A plurality of conductive contacts is formed in direct contact with the metal material in the buried digit line end region. Methods of forming a buried digit line contact include forming conductive contacts physically contacting metal material in trenches in a buried digit line end region. Vertical memory devices and apparatuses include metallic connections disposed between a buried digit line and a conductive contact in a buried digit line end region.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shyam Surthi, Suraj Mathew
  • Patent number: 10930627
    Abstract: A semiconductor device package includes a first semiconductor device having a first surface, an interconnection element having a surface substantially coplanar with the first surface of the first semiconductor device, a first encapsulant encapsulating the first semiconductor device and the interconnection element, and a second semiconductor device disposed on and across the first semiconductor device and the interconnection element.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: February 23, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang-Yu Lin, Chi-Han Chen, Chieh-Chen Fu
  • Patent number: 10923568
    Abstract: A semiconductor device includes a p-type SiC layer, a gate electrode, and a gate insulating layer between the SiC layer and the gate electrode. The gate insulating layer includes first and second layers and first and second regions. The second layer is between the first layer and the gate electrode and has a higher oxygen density than the first layer. The first region is across the first layer and the second layer, and includes at least one first element selected from the group consisting of N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), and Bi (bismuth) and the first region having a first concentration peak of the at least one first element. The second region is provided in the first layer, includes a second element from Ta (tantalum), Nb (niobium), and V (vanadium) and, the second region having a second concentration peak of the at least one second element.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: February 16, 2021
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Ryosuke Iijima