Patents Examined by Andy Huynh
  • Patent number: 10840272
    Abstract: A display device includes a first substrate including a display region and a non-display region, the non-display region being positioned on an outside of the display region, a first dam in the non-display region of the substrate, the first dam including a first barrier and a first stopper, the first stopper being on the first barrier and having a concave groove formed thereon, and a first alignment layer covering the display region of the first substrate, at least a part of the first alignment layer extending to the non-display region and contacting a surface of the first stopper.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: November 17, 2020
    Assignee: SAMSUNG DISPLAY CO. LTD.
    Inventors: Se Hee Han, Tae Gyun Kim
  • Patent number: 10840203
    Abstract: An assembly platform for arrangement as an interposer device between an integrated circuit and a substrate to interconnect the integrated circuit and the substrate through the assembly platform, the assembly platform comprising: an assembly substrate; a plurality of conducting vias extending through the assembly substrate; at least one nanostructure connection bump on a first side of the assembly substrate, the nanostructure connection bump being conductively connected to the vias and defining connection locations for connection with at least one of the integrated circuit and the substrate, wherein each of the nanostructure connection bumps comprises: a plurality of elongated conductive nanostructures vertically grown on the first side of the assembly substrate, wherein the plurality of elongated nanostructures are embedded in a metal for the connection with at least one of the integrated circuit and the substrate, at least one connection bump on a second side of the assembly substrate, the second side being
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: November 17, 2020
    Assignee: SMOLTEK AB
    Inventors: M Shafiqul Kabir, Anders Johansson, Vincent Desmaris, Muhammad Amin Saleem
  • Patent number: 10840421
    Abstract: An optoelectronic component including a first optoelectronic semiconductor chip configured to emit light includes a wavelength from an infrared spectral range, and a second optoelectronic semiconductor chip configured to emit light including a wavelength from a visible spectral range, wherein the optoelectronic component includes a reflector body including a top side and an underside, the reflector body includes a cavity opened toward the top side, a wall of the cavity constitutes a reflector, and the first optoelectronic semiconductor chip is arranged at a bottom of the cavity.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: November 17, 2020
    Assignee: OSRAM OLED GmbH
    Inventors: Thomas Kippes, Jason Rajakumaran, Ulrich Frei, Claus Jäger
  • Patent number: 10840171
    Abstract: A packaged semiconductor device includes a semiconductor die mounted on a leadframe, a housing for the semiconductor die defining a horizontal plane and a horizontal direction. The leadframe includes leads each having an inner lead portion inside the housing and an outer lead portion that includes a first portion that extends out in the horizontal direction from one of the sidewalls of the housing, a transition portion that includes a vertical direction component, and a distal end portion, wherein the distal end portion of the leads are all on the horizontal plane. The outer lead portions alternate between a gull wing lead shape having the distal end portions extending in the horizontal direction outward from the housing and inward extending leads that have their distal end portions extending in the horizontal direction inward toward the housing. The leadframe consists of a single leadframe.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: November 17, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Michael L. Meyers, Scott F. Eisenhart, Richard J. Saye, Sreenivasan K. Koduri
  • Patent number: 10840346
    Abstract: Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yong-Yan Lu, Hou-Yu Chen, Shyh-Horng Yang
  • Patent number: 10840198
    Abstract: A semiconductor device includes a substrate, a conductive pad region electrically coupled to the substrate, a first dielectric layer over the conductive pad region, and a passivation layer over the first dielectric layer, wherein the passivation layer includes a laterally-extending portion covering the first dielectric layer and a vertically-extending portion on a sidewall of the first dielectric layer. The laterally-extending portion and the vertically-extending portion of the passivation layer are joined along a vertically-extending boundary.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hung-Shu Huang, Ming-Chyi Liu
  • Patent number: 10833098
    Abstract: According to one embodiment, a semiconductor memory device includes a first conductive member, a first semiconductor member, and a first stacked member provided between the first conductive member and the first semiconductor member. The first stacked member includes a first insulating film, a second insulating film provided between the first insulating film and the first semiconductor member, first and second layers. The first layer includes aluminum and nitrogen and is provided between the first and second insulating films. A first thickness of the first layer along a first direction is 3 nm or less. The first direction is from the first semiconductor member toward the first conductive member. The second layer contacts the first layer, includes silicon and nitrogen, and is provided at one of a position between the first layer and the second insulating film or a position between the first layer and the first insulating film.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: November 10, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Akira Takashima, Tsunehiro Ino, Yuuichi Kamimuta, Ayaka Suko
  • Patent number: 10825484
    Abstract: A method of forming an integrated assembly includes providing a construction having laterally-spaced digit-line-contact-regions and having intervening regions between the laterally-spaced digit-line-contact-regions; forming an expanse of non-conductive-semiconductor-material which extends across the digit-line-contact-regions and the intervening regions; a lower surface of the non-conductive-semiconductor-material being vertically-spaced from upper surfaces of the digit-line-contact-regions; forming openings extending through the non-conductive-semiconductor-material to the digit-line-contact-regions; forming conductive-semiconductor-material-interconnects within the openings and coupled with the digit-line-contact-regions, upper surfaces of the conductive-semiconductor-material-interconnects being beneath the lower surface of the non-conductive-semiconductor-material; and forming metal-containing-digit-lines over the non-conductive-semiconductor-material.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Deepak Chandra Pandey, Si-Woo Lee
  • Patent number: 10818795
    Abstract: A semiconductor device comprising a pixel portion comprising a capacitor and a transistor is provided. The capacitor comprises a first oxide semiconductor film and a transparent conductive material. The transistor comprises a second oxide semiconductor film, a source electrode, and a drain electrode. The transistor is electrically connected to the capacitor. The capacitor is provided to overlap with a first opening portion in an insulating film and a second opening portion in an organic resin film. The transparent conductive material comprises a region over the organic resin film. The second oxide semiconductor film comprises a channel formation region and a first region outside the channel formation region. Each of a carrier density of the first oxide semiconductor film and a carrier density of the first region is higher than a carrier density of the channel formation region.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: October 27, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Masami Jintyou, Yukinori Shima, Takashi Hamochi, Yasutaka Nakazawa
  • Patent number: 10818625
    Abstract: An electronic device is provided. The electronic device includes a substrate, at least one contact pad disposed on the substrate, and a redistribution layer including a strip-shaped portion. The redistribution layer is electrically connected to the contact pad. The strip-shaped portion includes at least two strip-shaped steps, and each of the strip-shaped steps includes a plurality of peaks and valleys.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: October 27, 2020
    Assignee: Nanya Technology Corporation
    Inventor: Shing-Yih Shih
  • Patent number: 10818656
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, second, third and fourth semiconductor regions of a second conductivity type, a first insulating film, a second insulating film, a first electrode contacting the first insulating film, and a second electrode contacting the second insulating film. The second and third semiconductor regions contact the first semiconductor region. The fourth semiconductor region contacts the first semiconductor region, is disposed between the second semiconductor region and the third semiconductor region. The first insulating film contacts a first portion of the first semiconductor region between the second semiconductor region and the fourth semiconductor region. The second insulating film contacts a second portion of the first semiconductor region between the third semiconductor region and the fourth semiconductor region. The second insulating film is thicker than the first insulating film.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: October 27, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hidekazu Inoto, Osamu Takata, Itaru Tamura, Naozumi Terada, Hiroyoshi Kitahara
  • Patent number: 10807864
    Abstract: The invention includes a method of promoting interfacial mechanical bonding of two or more components through the use of suspended and/or freestanding structures fabricated using an atom-scale assembly process on at least a portion of the surfaces of such components.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: October 20, 2020
    Assignee: The Regents of the University of Colorado, a body corporate
    Inventors: Joseph J. Brown, Victor M. Bright
  • Patent number: 10811549
    Abstract: A quantum-dot based avalanche photodiode (QD-APD) may include a silicon substrate and a waveguide on which a quantum dot (QD) stack of layers is formed having a QD light absorption layer, a charge multiplication layer (CML), and spacer layers. The QD stack may be formed within a p-n junction. The waveguide may include a mode converter to facilitate optical coupling and light transfer from the waveguide to the QD light absorption layer. The QD absorption layer and the CML layer may be combined or separate layers. The CML may generate electrical current from the absorbed light with more than 100% quantum efficiency when the p-n junction is reverse-biased.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: October 20, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Geza Kurczveil, Di Liang, Bassem Tossoun, Chong Zhang, Xiaoge Zeng, Zhihong Huang, Raymond Beausoleil
  • Patent number: 10811365
    Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-? dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: October 20, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Shams U. Arifeen, Hyunsuk Chun, Sheng Wei Yang, Keizo Kawakita
  • Patent number: 10796989
    Abstract: A semiconductor device having a first die and a second die is provided. The first die of the device includes a first surface and a through-substrate via (TSV) extending at least substantially through the first die, the TSV having a portion extending past the first surface. The first die further includes a first substantially helical conductor disposed around the TSV. The second die of the device includes a second surface, an opening in the second surface in which the portion of the TSV is disposed, and a second substantially helical conductor disposed around the opening.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kyle K. Kirby
  • Patent number: 10797130
    Abstract: A semiconductor device is disclosed that includes a substrate; a first semiconductor region arranged in the cell region on a first surface side of the substrate; a second semiconductor region arranged in a cell region; a channel stopper electrode arranged in a termination region; a first electrode arranged on the first surface and electrically connected to the second semiconductor region; an insulation film arranged between the channel stopper electrode and the first electrode; first conductors arranged inside the insulation film; second conductors arranged on the insulation film; and a second electrode arranged on a second surface side of the substrate. A width of an overlapping portion in a height direction of the first conductor and the second conductor on the first electrode side is larger than a width of an overlapping portion in the height direction of the first and second conductors on the channel stopper electrode side.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: October 6, 2020
    Assignee: SANKEN ELECTRIC CO., LTD.
    Inventor: Naoki Morikawa
  • Patent number: 10790328
    Abstract: To achieve a size reduction of a semiconductor package while securing stability in mounting. Three terminals t1, t2, and t4 are individually arranged on a semiconductor package 10 having a rectangular shape as viewed in plan in such a manner that the center in the longitudinal direction of the semiconductor package 10 of each of the three terminals t1, t2, and t4 and the center in the longitudinal direction of each of the other terminals are not overlapped with each other as viewed from the side of the long side.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: September 29, 2020
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Osamu Shirata, Yusuke Hidaka
  • Patent number: 10790362
    Abstract: The present disclosure provides a semiconductor structure, including providing a metal layer, an adhesion-enhancing layer over the metal layer, a dielectric stack over the adhesion-enhancing layer, a contact penetrating the dielectric stack and the adhesion-enhancing layer and connecting with the metal layer, a barrier layer disposed between the contact and the dielectric stack, and a high-k dielectric layer disposed between the contact and the barrier layer.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: September 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yao-Wen Chang, Gung-Pei Chang, Ching-Sheng Chu, Chern-Yow Hsu
  • Patent number: 10790475
    Abstract: A display device includes: a substrate; pixels on the substrate; and a polarization film on the pixels and stretched in a first direction and a second direction opposite to the first direction. The polarization film is cut at an end portion of the polarization film along a third direction, the third direction forming an acute angle with the first direction toward an outside of the polarization film.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: September 29, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Won Je Cho
  • Patent number: 10784179
    Abstract: A method for fabricating a semiconductor device includes sequentially laminating a separation layer and a first substrate layer on a sacrificial substrate, and forming a heat dissipation plate comprising a first region and a second region on the first substrate layer. The method further includes removing the sacrificial substrate and the separation layer, and patterning the first substrate layer to form a first substrate exposing the heat dissipation plate in the second region and contacting the heat dissipation plate in the first region, and forming a first element on the first substrate. The method still further includes forming a plurality of conductive pads disposed on the heat dissipation plate in the second region and a first line connecting at least one of the plurality of conductive pads to the first element, and forming a second element on the conductive pads in the second region.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: September 22, 2020
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hyung Seok Lee, Zin-Sig Kim, Sung-Bum Bae