Patents Examined by Andy Huynh
  • Patent number: 10475932
    Abstract: A transistor structure includes a first oxide semiconductor layer, a source structure and a drain structure, and a second oxide semiconductor layer. The first oxide semiconductor layer is doped with sulfur. The source structure and the drain structure are disposed on the first oxide semiconductor layer, and a region of the first oxide semiconductor layer between the source structure and the drain structure forms a channel region. The second oxide semiconductor layer doped with sulfur is at least formed on the channel region of the first oxide semiconductor layer.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: November 12, 2019
    Assignee: Untied Microelectronics Corp.
    Inventors: Shao-Hui Wu, Yu-Cheng Tung
  • Patent number: 10475995
    Abstract: A variable resistance memory cell with a wide difference (“window”) between threshold voltages is provided. The window between threshold voltages is increased by amplifying the stoichiometry gradient by means of an asymmetry in the memory cell architecture to provide a greater margin for detecting different logic states of the memory cell.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: November 12, 2019
    Assignee: Intel Corporation
    Inventor: Paolo Fantini
  • Patent number: 10465284
    Abstract: A method for producing an apparatus, an apparatus and an optoelectronic component are disclosed. In an embodiment the method includes providing a carrier, depositing an amorphous ALD layer on the carrier using an ALD method and recrystallizing the amorphous ALD layer into a crystalline layer.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: November 5, 2019
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventor: Andreas Rückerl
  • Patent number: 10453915
    Abstract: A semiconductor device includes a semiconductor body having a semiconductor substrate of a first conductivity type and a semiconductor layer of the first conductivity type on the substrate. A trench structure extends into the semiconductor body from a first surface and includes a gate electrode and at least one field electrode arranged between the gate electrode and a bottom side of the trench structure. A body region adjoins the trench structure and laterally extends from a transistor cell area into an edge termination area. A pn junction is between the body region and semiconductor layer. A doping concentration of at least one of the body region and semiconductor layer is lowered at a lateral end of the pn junction in the edge termination area compared to a doping concentration of the at least one of the body region and semiconductor layer at the pn junction in the transistor cell area.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: October 22, 2019
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Karl-Heinz Bach, Christian Kampen, Dietmar Kotz, Andrew Christopher Graeme Wood, Markus Zundel
  • Patent number: 10446468
    Abstract: Methods of fabricating compound semiconductor device structures having polycrystalline CVD diamond. The method includes: providing a substrate that has a layer of single crystal compound semiconductor material; forming a bonding layer on a surface of the substrate, the bonding layer having a thickness of less than 25 nm and a thickness variation of no more than 15 nm; and growing a layer of polycrystalline diamond on the bonding layer using a chemical vapor deposition technique. The effective thermal boundary resistance at the interface between the layer of single crystal compound semiconductor material and the layer of polycrystalline CVD diamond material is less than 25 m2K/GW. The layer of single crystal compound semiconductor material has one or both of the following characteristics: a charge mobility of at least 1200 cm2V?1s?1; and a sheet resistance of no more than 700 ?/square.
    Type: Grant
    Filed: February 24, 2019
    Date of Patent: October 15, 2019
    Assignee: RFHIC CORPORATION
    Inventors: Frank Yantis Lowe, Daniel Francis, Firooz Nasser-Faili, Daniel James Twitchen
  • Patent number: 10446572
    Abstract: Various embodiments include methods and apparatus having a number of charge trap structures, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric region, the blocking dielectric region located on a charge trap region of the charge trap structure. At least a portion of the gate can be separated by a void from a region which the charge trap structure is directly disposed. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Chris M Carlson
  • Patent number: 10439117
    Abstract: An optical device includes a substrate, a conductive layer formed over the substrate, an insulating layer formed over the conductive layer, a first optical element disposed over the conductive layer, and a sealing resin part configured to cover the first optical element. The conductive layer includes a first conductive section, a second conductive section spaced apart from the first conductive section, and a first conductive portion extending in a first direction from the first conductive section. The first conductive portion is spaced apart from the second conductive section in a second direction intersecting with the first direction, and the insulating layer includes a first insulating part formed over the first conductive portion, and the first insulating part includes a portion overlapping with the second conductive section in the first direction.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: October 8, 2019
    Assignee: Rohm Co., Ltd.
    Inventor: Riki Shimabukuro
  • Patent number: 10411134
    Abstract: A display device includes a gate electrode on a substrate of a semiconductor device, a gate insulating film over the gate electrode, an active layer comprising an oxide including indium, zinc and gallium on the gate insulating film, and overlapping the gate electrode, and a source electrode and a drain electrode that are spaced apart from each other, wherein the active layer is formed from a zinc-rich target material, and an atomic % ratio of indium, zinc and gallium in the active layer is different from an atomic % ratio of the zinc-rich target material.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: September 10, 2019
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Min-Cheol Kim, Youn-Gyoung Chang, Kwon-Shik Park, So-Hyung Lee, Ho-Young Jung, Ha-Jin Yoo, Jeong-Suk Yang
  • Patent number: 10403817
    Abstract: A memory device may include a first conductive line, a second conductive line extending in a direction intersecting the first conductive line, such that the first conductive line and the second conductive line vertically overlap at a cross-point between the first conductive line and the second conductive line, and a memory cell pillar at the cross-point. The memory cell pillar may include a heating electrode layer and a resistive memory layer contacting the heating electrode layer. The resistive memory layer may include a wedge memory portion having a width that increases continuously in proportion with increasing distance from the heating electrode layer, and a body memory portion connected to the wedge memory portion such that the body memory portion and the wedge memory portion comprise an individual and continuous layer, the body memory portion having a greater width than the wedge memory portion.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seul-ji Song, Sung-won Kim, Il-mok Park, Jong-chul Park, Ji-Hyun Jeong
  • Patent number: 10396313
    Abstract: A manufacturing method of a display device includes: forming pixels on a mother substrate including a display area and a non-display area; attaching a polarization film stretched in a first direction and a second direction opposite to the first direction on the mother substrate having the pixels thereon; and cutting at least a portion of the polarization film along a third direction, wherein the third direction forms an acute angle with the first direction toward an outside of the polarization film.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: August 27, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventor: Won Je Cho
  • Patent number: 10396147
    Abstract: An on-chip metal-insulator-metal (MIM) capacitor with enhanced capacitance is provided by forming the MIM capacitor along sidewall surfaces and a bottom surface of each trench of a plurality of trenches formed in a back-end-of-the-line (BEOL) metallization stack to increase a surface area of the MIM capacitor.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10379440
    Abstract: According to one embodiment, a pattern forming method includes forming a resist pattern on a substrate, forming a first silicone resin layer so as to bury the resist pattern on the substrate, pressing a film on the surface of the first silicone resin layer to adhere the film thereto, curing the first silicone resin layer after the adhesion of the film, peeling the film from the first silicone resin layer before or after the curing of the first silicone resin layer, and removing the resist pattern after the peeling of the film.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: August 13, 2019
    Assignee: KABUSHIKI KASHIA TOSHIBA
    Inventors: Michihiko Nishigaki, Yutaka Onozuka, Shouhei Kousai, Yosuke Akimoto, Miyu Nagai, Kaita Imai
  • Patent number: 10381599
    Abstract: A highly reliable light-emitting device is provided. Damage to an element due to externally applied physical power is suppressed. Alternatively, in a process of pressure-bonding of an FPC, damage to a resin and a wiring which are in contact with a flexible substrate due to heat is suppressed. A neutral plane at which stress-strain is not generated when a flexible light-emitting device including an organic EL element is deformed, is positioned in the vicinity of a transistor and the organic EL element. Alternatively, the hardness of the outermost surface of a light-emitting device is high. Alternatively, a substrate having a coefficient of thermal expansion of 10 ppm/K or lower is used as a substrate that overlaps with a terminal portion connected to an FPC.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: August 13, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Shingo Eguchi
  • Patent number: 10373935
    Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer; and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: August 6, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-kyoung Seo, Cha-jea Jo, Soo-hyun Ha
  • Patent number: 10374077
    Abstract: A semiconductor device includes a source region disposed in a substrate and having a first conductivity type, a drain region disposed in the substrate and having the first conductivity type, a first drift region having the first conductivity type and extending in a channel length direction between the source and drain regions, a second drift region having a second conductivity type and extending parallel to the first drift region, a field plate region disposed in an upper portion of the second drift region, an auxiliary electrode disposed in an upper portion of the field plate region, and a gate electrode disposed on the substrate and electrically connected with the auxiliary electrode. Such devices can reduce the specific on-resistance while also reducing electric field concentrations at the edge portions of the gate electrode, and the breakdown voltage of the device can therefore be significantly improved.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: August 6, 2019
    Assignee: DB Hitek Co., Ltd
    Inventor: Yong Keon Choi
  • Patent number: 10347634
    Abstract: Methods of forming semiconductor device structures include forming trenches in an array region and in a buried digit line end region, forming a metal material in the trenches, filling the trenches with a mask material, removing the mask material in the trenches to expose a portion of the metal material, and removing the exposed portion of the metal material. A plurality of conductive contacts is formed in direct contact with the metal material in the buried digit line end region. Methods of forming a buried digit line contact include forming conductive contacts physically contacting metal material in trenches in a buried digit line end region. Vertical memory devices and apparatuses include metallic connections disposed between a buried digit line and a conductive contact in a buried digit line end region.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Shyam Surthi, Suraj Mathew
  • Patent number: 10340265
    Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: July 2, 2019
    Assignee: STMicroelectronics SA
    Inventor: Johan Bourgeat
  • Patent number: 10340243
    Abstract: A circuit substrate includes: a base material; and a capacitor layer. The capacitor layer includes a first metal layer that is provided on the base material, a dielectric layer that is provided on the first metal layer, and a second metal layer that is provided on the dielectric layer. The first metal layer includes a first electrode region which is provided on the base material and is exposed from the dielectric layer and to which a first terminal of a capacitor element for supplying current to a circuit part through the capacitor layer is connected. The second metal layer includes a second electrode region in which the second metal layer is exposed and to which a second terminal of the capacitor element is connected.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: July 2, 2019
    Assignees: FUJI XEROX CO., LTD., NODA SCREEN CO., LTD.
    Inventors: Daisuke Iguchi, Atsunori Hattori
  • Patent number: 10340349
    Abstract: A method of forming a semiconductor structure is disclosed. A substrate having a first area and a second area is provided, wherein a first surface of the first area is lower than a second surface of the second area. A first insulating layer, a first gate, a first dielectric layer and a first dummy gate are sequentially formed on the first surface of the first area. A second dielectric layer and a second dummy gate are formed on the second surface of the second area. An inter-layer dielectric layer is formed around the first gate, the first dummy gate and the second dummy gate. The first dummy gate and the second dummy gate are removed, so as to form a first trench and a second trench in the inter-layer dielectric layer. A second gate and a third gate are filled respectively in the first trench and the second trench.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: July 2, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Huang Yu, Shih-Yin Hsiao
  • Patent number: 10340328
    Abstract: A display device includes a first substrate arranged with a plurality of pixels on a first surface, the plurality of pixels having a display element including a transistor, and a first wiring connected to the transistor, a through electrode arranged in a first contact hole reaching the first wiring from a second surface facing the first surface of the first substrate, a second wiring connected with the through electrode, a first insulation film arranged covering the second wiring on the second surface of the first substrate, and a terminal connected with a second wiring via a second contact hole arranged in the first insulation film.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: July 2, 2019
    Assignee: Japan Display Inc.
    Inventors: Kazuto Tsuruoka, Norio Oku