Abstract: A transistor. In some embodiments, the transistor includes a first superconducting source-drain, a second superconducting source-drain, a graphene channel including at least a portion of a graphene sheet, and a conductive gate. The first superconducting source-drain, the second superconducting source-drain, and the graphene channel together form a Josephson junction having a critical current. The graphene channel forms a current path between the first superconducting source-drain and the second superconducting source-drain. The conductive gate is configured, upon application of a electric field across the conductive gate and the graphene channel by applying a voltage, to modify the critical current.

Abstract: A method for fabricating a semiconductor device includes sequentially laminating a separation layer and a first substrate layer on a sacrificial substrate, and forming a heat dissipation plate comprising a first region and a second region on the first substrate layer. The method further includes removing the sacrificial substrate and the separation layer, and patterning the first substrate layer to form a first substrate exposing the heat dissipation plate in the second region and contacting the heat dissipation plate in the first region, and forming a first element on the first substrate. The method still further includes forming a plurality of conductive pads disposed on the heat dissipation plate in the second region and a first line connecting at least one of the plurality of conductive pads to the first element, and forming a second element on the conductive pads in the second region.

Abstract: A semiconductor device includes a carrier having a first central axis extending along a first direction and a second central axis extending along a second direction, a plurality of dies disposed on a surface of the carrier, and a plurality of scribing lines separating the plurality of dies from each other. The plurality of scribing lines include a plurality of continuous lines along the first direction and a plurality of discontinuous lines along the second direction, at least one of the plurality of continuous lines overlaps the first central axis, at least one of the plurality of discontinuous lines overlaps the second central axis. The plurality of dies are symmetrically arranged on the carrier about the first central axis and the second central axis.

Abstract: A semiconductor light emitting device includes a light emitting structure having a first conductivity-type semiconductor layer, an active layer and a second conductivity-type semiconductor layer, a transparent electrode layer on the second conductivity-type semiconductor layer and spaced apart from an edge of the second conductivity-type semiconductor layer, a first insulating layer on the light emitting structure to cover the transparent electrode layer and including a plurality of holes connected to the transparent electrode layer, and a reflective electrode layer on the first insulating layer and connected to the transparent electrode layer through the plurality of holes.

Abstract: Provided are an integrated circuit device and a method of manufacturing the same. The integrated circuit device includes: a semiconductor substrate; a device isolation layer defining an active region of the semiconductor substrate; a gate insulating layer on the active region; a gate stack on the gate insulating layer; a spacer on a sidewall of the gate stack; and an impurity region provided on both sides of the gate stack, wherein the gate stack includes a metal carbide layer and a metal layer on the metal carbide layer, wherein the metal carbide layer includes a layer having a carbon content of about 0.01 at % to about 15 at %.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing word lines and drain select gate electrodes located over a substrate, and memory stack structures containing a respective vertical semiconductor channel and a memory film including a tunneling dielectric and a charge storage layer. A first portion of a first charge storage layer located in a first memory stack structure at level of a first drain select gate electrode is thicker than a first portion of a second charge storage layer located in a second memory stack structure at the level of the first drain select electrode.

Abstract: A stack type power module includes: a power semiconductor having a gate and an emitter, each of which has a pad shape, adjacent to each other on one surface of the power semiconductor, and a collector having a pad shape on another surface of the power semiconductor; an upper substrate layer stacked on an upper portion of the power semiconductor, and electrically connected to a metal layer that has a lower surface with which the collector is in contact; and a lower substrate layer stacked on a lower portion of the power semiconductor, and electrically connected to the metal layer that has an upper surface with which each of the gate and the emitter is in contact.

Abstract: A semiconductor device and fabrication method are provided. The method includes: providing a base substrate; forming a first dielectric layer on the base substrate; forming a target gate structure in the first dielectric layer and on the base substrate, where a first groove is formed above the target gate structure and in the first dielectric layer; forming a second groove by etching the first dielectric layer on sidewalls of the first groove to expand an opening of the first groove; forming a protective layer in the second groove; and forming conductive plugs in the first dielectric layer on sides of the target gate structure and the protective layer. The protective layer has a dielectric constant greater than the first dielectric layer.

Abstract: A method for manufacturing a semiconductor light-emitting apparatus includes: forming multiple eutectic material layers on multiple first electrode patterns, respectively, of a wiring substrate; mounting multiple semiconductor light-emitting elements on the multiple eutectic material layers, respectively; mounting a plate on the multiple semiconductor light-emitting elements via multiple eutectic temperature liquid layers, respectively, the multiple eutectic temperature liquid layers maintaining a liquid state even at a eutectic temperature of the multiple eutectic material layers; and heating and cooling the multiple eutectic material layers and the multiple temperature liquid layers while the plate is adhered via the multiple eutectic temperature liquid layers to the multiple semiconductor light-emitting elements by the surface tension phenomenon.

Abstract: An electronic device includes a support structure comprising a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a conductive layer coupled to the first adhesion layer, a second adhesion layer coupled to the conductive layer, and a barrier layer coupled to the second adhesion layer. The electronic device also includes a buffer layer coupled to the support structure, a contact layer coupled to the buffer layer, and a field-effect transistor (FET) coupled to the contact layer.

Abstract: The present disclosure provides a semiconductor structure, including a logic region and a memory region. The memory region includes a first Nth metal line of an Nth metal layer, a magnetic tunneling junction (MTJ) over first Nth metal line, a carbon-based layer between the first Nth metal line and the MTJ, and a first (N+M)th metal via of an (N+M)th metal layer. A method of manufacturing the semiconductor structure is also disclosed.

Abstract: Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures are provided. In some embodiments methods may include contacting a substrate with a first reactant comprising a transition metal precursor, contacting the substrate with a second reactant comprising a niobium precursor and contacting the substrate with a third reactant comprising a nitrogen precursor. In some embodiments related semiconductor device structures may include a semiconductor body and an electrode comprising a transition metal niobium nitride disposed over the semiconductor body.

Abstract: A method of fabricating a semiconductor device structure includes: providing a substrate comprising a layer of compound semiconductor material; forming a seed layer of nano-crystalline diamond having a layer thickness in a range 5 to 50 nm on the layer of compound semiconductor material; and growing a layer of polycrystalline CVD diamond on the seed layer using a chemical vapour deposition (CVD) technique. An effective thermal boundary resistance (TBReff) at an interface between the layer of compound semiconductor material and the layer of polycrystalline CVD diamond material is no more than 50 m2K/GW.

Abstract: Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium. In some instances, the anneal process may be performed at pressures of up to 50 atmospheres to increase the amount of deuterium that penetrates the integrated circuit structure and reaches the interfaces to be passivated. Interfaces to be passivated may include, for example, an interface between the transistor conductive channel and bordering transistor gate dielectric and/or an interface between sub-channel semiconductor and bordering shallow trench isolation oxides.

Abstract: A method for forming a semiconductor structure includes: providing a semiconductor substrate having a first pad and a second pad on a top surface of the semiconductor substrate; providing a circuit board having an active pad and a non-metallic surface; providing a first solder ball and a second solder ball on the active pad and the non-metallic surface respectively; attaching the first pad and the second pad on the first solder ball and the second solder ball respectively; and reflowing the first solder ball and the second solder ball to form a first bump wetted on the active pad and a second bump not wetted on the non-metallic surface.

Abstract: An image sensor having a plurality of pixels along a first direction includes: a first pixel having a first photoelectric conversion unit that generates an electric charge through photoelectric conversion and a reflecting portion disposed at least in a part of an area located in the first direction relative to a center of the first photoelectric conversion unit, which reflects part of light having been transmitted through the first photoelectric conversion unit toward the first photoelectric conversion unit; and a second pixel having a second photoelectric conversion unit that generates an electric charge through photoelectric conversion and a second reflecting portion disposed at least in a part of an area located in a direction opposite from the first direction relative to a center of the second photoelectric conversion unit, which reflects part of light having been transmitted through the second photoelectric conversion unit toward the second photoelectric conversion unit.

Abstract: A semiconductor structure includes an insulating substrate, an engineered layer, a semiconductor layer, and an isolation structure. The engineered layer is surrounding the insulating substrate. The semiconductor layer, which includes a first region and a second region,. is formed over the engineered layer. The isolation structure is formed in the semiconductor layer and located between the first region and the second region. A first transistor and a second transistor are formed in the first region and the second region respectively.

Abstract: A micro light-emitting diode display device including a driving transistor and a micro light-emitting diode is provided. The driving transistor includes a substrate, a gate, a gate insulator, a semiconductor layer, a drain electrode, and a source electrode. The gate insulator has a thickness less than or equal to about 500 angstroms. The micro light-emitting diode has a lateral length less than or equal to about 50 ?m and is electrically connected to one of the source electrode and the drain electrode. A current injection channel is extended within one of a first type semiconductor layer and a second type semiconductor layer of the micro light-emitting diode and is spaced apart from a side surface of the micro light-emitting diode. A lateral length a light-emitting portion of an active layer of the micro light-emitting diode is less than or equal to about 10 ?m.

Abstract: A package includes a substrate, an Under-Bump Metallurgy (UBM) penetrating through the substrate, a solder region over and contacting the UBM, and an interconnect structure underlying the substrate. The interconnect structure is electrically coupled to the solder region through the UBM. A device die is underlying and bonded to the interconnect structure. The device die is electrically coupled to the solder region through the UBM and the interconnect structure. An encapsulating material encapsulates the device die therein.

Abstract: A vertical transistor device and its fabrication method are provided. The vertical transistor device includes a semiconductor substrate, first sources/drains and second sources/drains. The semiconductor substrate includes a bottom portion and a fin portion. The fin portion is located on the bottom portion. The fin portion includes an upper portion and a lower portion located between the bottom portion of the semiconductor substrate and the upper portion. The lower portion includes a narrow portion having a width smaller than a width of the upper portion, and the narrow portion contacts an interface portion of the upper portion. The sources/drains are disposed on the on the narrow portion of the lower portion of the fin portion. In the method for fabricating the vertical transistor device, the lower portions of the fin portions are patterned to form the narrow portions where the sources are disposed.