Abstract: A method of producing an optoelectronic semiconductor component includes providing a carrier, arranging at least one optoelectronic semiconductor chip at a top side of the carrier, applying a phosphor layer at the at least one semiconductor chip, forming a shaped body around the at least one optoelectronic semiconductor chip, wherein the shaped body surrounds all side areas of the at least one optoelectronic semiconductor chip, and removing the carrier, wherein the phosphor layer is applied before forming the shaped body.

Abstract: Disclosed is an organic electroluminescent element including a first electrode, a hole transport layer, a light emitting layer, an electron transport layer and a second electrode in this order. The light emitting layer has a first light emitting layer including a coating film on the hole transport layer side, and has a second light emitting layer including a vapor-deposited film on the electron transport layer side.

Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection hump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.

Abstract: A FET IC structure made using a back-side access process that mitigates or eliminates thermal conductivity problems. In some embodiments, electrically-isolated thermal paths are formed adjacent the FET and configured to conduct heat laterally away from the FET to generally orthogonal thermal pathways, and thence to thermal pads externally accessible at the “top” of the completed IC. In some embodiments having a thermally-conductive handle wafer, electrically-isolated thermal paths are formed adjacent a FET and configured to conduct heat laterally away from the FET. Thermal vias are formed sufficiently so as to be in thermal contact with the handle wafer and with the conventional metallization layers of the device superstructure, at least one of which is in thermal contact with the lateral thermal paths. In some embodiments, the lateral thermal paths may use dummy gates configured to conduct heat laterally away from a FET to generally orthogonal thermal pathways.

Abstract: An optical component for optical semiconductor includes a wavelength converting member including a fluorescent part having an upper surface, a lower surface, and one or more lateral surfaces, and containing a fluorescent material, and a light-reflecting part disposed adjacently surrounding the one or more lateral surfaces of the fluorescent part when viewed from above, and a light-transmissive member disposed below the wavelength converting member. A dielectric multilayer film is disposed on an upper surface of the light-transmissive member at least at a region facing the fluorescent part, the dielectric multilayer film is configured to transmit excitation light incident from below the light-transmissive member and to reflect fluorescent light emitted from the fluorescent part. Further, a space is formed between the fluorescent part and the dielectric multilayer film, and the light-reflecting part and the light-transmissive member are connected by a connecting member made of a metal material.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.

Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a heat dissipation plate including a first region and a second region, a first element disposed on the heat dissipation plate in the first region, and a second element disposed on the heat dissipation plate in the second region. The first element includes a first substrate, the second element includes a second substrate, the first substrate includes a material different from a material of the second substrate, the first substrate contacts the heat dissipation plate, and the second element is bonded to the heat dissipation plate in a flip-chip bonding manner.

Abstract: An electronic package includes a metal member including a supporting plate and a plurality of conductive pillars disposed on the supporting plate. A circuit structure is coupled to the conductive pillars. An electronic component is disposed on the metal member and electrically connected to the circuit structure. An encapsulant encapsulates the conductive pillars and the electronic component. Any mold can be used for fabricating the electronic package, no matter what the size of the electronic package is. Therefore, the fabricating cost of the electronic package is reduced.

Abstract: A light-emitting diode (LED) package includes: an LED having a polygonal shape in a plan view; a light-transmissive layer directing light from the LED in an upward direction; a wavelength conversion layer changing a wavelength of the light emitted through the light-transmissive layer; and a coating layer covering the light-transmissive layer and reflecting the light emitted through the light-transmissive layer in the upward direction. In a plan view of the light-transmissive layer, a length from a first point corresponding to a vertex of the LED to a second point corresponding to an end of an extension of a diagonal of the LED is greater than or equal to a length from the first point to a third point corresponding to an end of an extension of a side of the LED.

Abstract: An organic light emitting diode display device is disclosed. The organic light emitting diode display device includes a first substrate having a plurality of pixels in which a thin film transistor and an organic light emitting diode connected to the thin film transistor are arranged, a second substrate having a power supply wiring to which a power supply voltage is applied, and a conductive filler layer interposed between the first substrate and the second substrate and having a conductive medium. A cathode of the organic light emitting diode and the power supply wiring are electrically connected through the conductive filler layer.

Abstract: A method of producing a carrier substrate for an optoelectronic semiconductor component includes: providing a leadframe including a first electrically conductive contact section and a second electrically conductive contact section, and injection molding a housing including a housing frame embedding the leadframe by an injection-molding material free of epoxy such that the leadframe embedded in the housing frame of the injection-molded housing forms a carrier substrate for an optoelectronic semiconductor component.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed with stepped surfaces. Sacrificial metal plates are formed on the top surfaces of the sacrificial material layers, and a retro-stepped dielectric material portion is formed over the sacrificial metal plates. Contact via cavities are formed through the retro-stepped dielectric material portion employing the sacrificial metal plates as etch stop structures. The sacrificial metal plates are replaced with portions of insulating spacer layers. Sacrificial via fill structures within remaining volumes of the contact via cavities. The sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are replaced with portions of staircase-region contact via structures that contact the electrically conductive layers.

Abstract: A display device includes: a substrate including a bending area at least partially bent around a bending axis extending in a first direction; a first organic layer on the substrate, where a plurality of first openings is defined in a portion of the first organic layer corresponding to the bending area; a first conductive layer on the portion of the first organic layer and covering at least a portion of the plurality of first openings; a second organic layer on the first conductive layer, where a plurality of second openings is defined in the second organic layer; and a second conductive layer on the second organic layer, covering at least a portion of the plurality of second openings, and electrically connected to the first conductive layer through the plurality of second openings.

Abstract: Disclosed are a thin film transistor and a display device including the thin film transistor. The thin film transistor comprises: a bottom gate electrode on a substrate; a semiconductor layer overlapping with the bottom gate electrode, wherein the semiconductor layer comprises a N-type semiconductor layer and a P-type semiconductor layer, and the N-type semiconductor layer is overlapped partly with the P-type semiconductor layer; a first source electrode and a first drain electrode respectively connected to the P-type semiconductor layer; a second source electrode and a second drain electrode respectively connected to a portion of the N-type semiconductor layer which is not overlapped with the P-type semiconductor layer; and a top gate electrode above the semiconductor layer. According to the embodiment of the present disclosure, a complexity of a manufacturing process of the thin film transistor is reduced.

Abstract: The present disclosure provides a semiconductor ESD protection device. The semiconductor ESD protection device includes a substrate including a first conductivity type, a gate formed on the substrate, a source region and a drain region formed in the substrate, and a body region formed in the substrate. The substrate and the body region include a first conductivity type. The source region and the drain region include a second conductivity type. And the first conductivity type and the second conductivity type are complementary to each other. The body region is electrically connected to the gate.

Abstract: A semiconductor structure is provided that contains a non-volatile battery which controls gate bias and has increased output voltage retention and voltage resolution. The semiconductor structure may include a semiconductor substrate including at least one channel region that is positioned between source/drain regions. A gate dielectric material is located on the channel region of the semiconductor substrate. A battery stack is located on the gate dielectric material. The battery stack includes, a cathode current collector located on the gate dielectric material, a cathode material located on the cathode current collector, a first ion diffusion barrier material located on the cathode material, an electrolyte located on the first ion diffusion barrier material, a second ion diffusion barrier material located on the electrolyte, an anode region located on the second ion diffusion barrier material, and an anode current collector located on the anode region.

Abstract: A memory cell includes a first transistor coupled to a source line, wherein the first transistor is in a first well. The memory cell further includes a second transistor coupled to the first transistor and a bit line, wherein the second transistor is in the first well. The memory cell further includes a first capacitor coupled to a word line and the second transistor, wherein the first capacitor is in a second well. The memory cell further includes a second capacitor coupled to the second transistor and an erase gate, wherein the second capacitor is in the second well. In some embodiments, the first well contacts the second well on a first side of the first well.

Abstract: A semiconductor device according to embodiments described herein includes a p-type SiC layer, a gate electrode, and a gate insulating layer between the SiC layer and the gate electrode. The gate insulating layer includes a first layer, a second layer, a first region, and a second region. The second layer is between the first layer and the gate electrode and has a higher oxygen density than the first layer. The first region is provided across the first layer and the second layer, includes a first element from F, D, and H, and has a first concentration peak of the first element. The second region is provided in the first layer, includes a second element from Ge, B, Al, Ga, In, Be, Mg, Ca, Sr, Ba, Sc, Y, La, and lanthanoid, and has a second concentration peak of the second element and a third concentration peak of C.

Abstract: Disclosed are an organic light-emitting device and an organic light-emitting display device capable of improving reliability thereof. The organic light-emitting device or the organic light-emitting display device includes an organic encapsulation layer disposed on a light-emitting element, and the organic encapsulation layer includes a first organic encapsulation layer disposed on an inorganic encapsulation layer and a second organic encapsulation layer disposed so as to surround the first organic encapsulation layer and including a moisture-absorbent material. As such, it is possible to achieve a reduction in cost and to prevent moisture or oxygen from being introduced from the outside into the side surface of the organic light-emitting device.

Abstract: Some embodiments include an integrated assembly which has digit-line-contact-regions laterally spaced from one another by intervening regions. Non-conductive-semiconductor-material is over the intervening regions. Openings extend through the non-conductive-semiconductor-material to the digit-line-contact-regions. Conductive-semiconductor-material-interconnects are within the openings and are coupled with the digit-line-contact-regions. Upper surfaces of the conductive-semiconductor-material-interconnects are beneath a lower surface of the non-conductive-semiconductor-material. Metal-containing-digit-lines are over the non-conductive-semiconductor-material. Conductive regions extend downwardly from the metal-containing-digit-lines to couple with the conductive-semiconductor-material-interconnects. Some embodiments include methods of forming integrated assemblies.