Abstract: A memory device for efficient word line, bit line and precharge tracking is provided. The memory device includes a memory array, one or more address decoders, a word line driver, a plurality of sense amplifiers, a reference word line column, a reference bit line column, and a control circuit. The control circuit generates a control signal to perform read and write operations on the memory device. The address decoder selects a bit line and a word line. The selected word line is activated by the word line driver. While the reference word line column is used for vertical tracking of the word line, the reference bit line column is used for vertical tracking of the bit line. The sense amplifiers are activated to read the bit line.

Abstract: A magnetic memory includes a magnetoresistive effect device comprising: a first ferromagnetic layer that has magnetic anisotropy in a direction perpendicular to a film plane thereof; a first nonmagnetic layer that is provided on the first ferromagnetic layer; a first reference layer that is provided on the first nonmagnetic layer, has magnetic anisotropy in a direction perpendicular to a film plane thereof, has magnetization antiparallel to a magnetization direction of the first ferromagnetic layer, and has a film thickness that is 1/5.2 to 1/1.

Abstract: The present disclosure includes methods, devices, modules, and systems for sensing memory cells using a state machine. One method embodiment includes generating a first sensing reference according to a first output of a state machine. The method includes bifurcating a range of possible programmed levels to which a memory cell can be programmed with the first sensing reference. The method also includes generating a second sensing reference according to a second output of the state machine. The method further includes determining a programmed level of the memory cell with the second generated sensing reference.

Abstract: A semiconductor storage device includes: a memory cell array including a plurality of first wirings, a plurality of second wirings intersecting with the first wirings, and a plurality of memory cells respectively arranged at intersections of the first and second wirings; a plurality of drivers that drive the first wirings; a dummy wiring continuously extending in a direction of the first wirings and in a direction of the second wirings, a part of the dummy wiring extending in the direction of the second wirings being connected to the plurality of drivers; a plurality of switch circuits connected to respective connection portions of the plurality of drivers and the dummy wiring; and a replica line extending in the direction of the second wirings and connected to the dummy wiring through the plurality of switch circuits.

Abstract: A phase-change memory is provided. The phase-change memory comprises a substrate. A first electrode is formed on the substrate. A circular or linear phase-change layer is electrically connected to the first electrode. A second electrode formed on the phase-change layer and electrically connected to the phase-change layer, wherein at least one of the first electrode and the second electrode comprises phase-change material.

Abstract: A non-volatile electrochemical memory cell formed of a stack of thin films comprising at least one first active layer, suited to releasing and accepting, in a reversible manner, at least one ion species, at least one second active layer, suited to releasing and accepting said ion species, in a reversible manner, the active layers being based on materials having different compositions and electrochemical potential profiles.

Abstract: A ferroelectric memory device includes a field effect transistor formed on a semiconductor substrate, an interlayer insulation film formed on the semiconductor substrate so as to cover the field effect transistor, a conductive plug formed in the interlayer insulation film in contact with the first diffusion region, and a ferroelectric capacitor formed over the interlayer insulation in contact with the conductive plug, wherein the ferroelectric capacitor includes a ferroelectric film and upper and lower electrodes sandwiching the ferroelectric film respectively from above and below, the lower electrode being connected electrically to the conductive plug, a layer containing oxygen being interposed between the conductive plug and the lower electrode, a layer containing nitrogen being interposed between the layer containing oxygen and the lower electrode, a self-aligned layer being interposed between the layer containing nitrogen and the lower electrode.

Abstract: A semiconductor memory device includes a cell block including a first bit line, a sense amplifier unit including a second bit line and configured to amplify a data signal applied to the second bit line, a connection unit configured to selectively connect the first bit line and the second bit line, a connection control unit configured to receive a control signal for driving the sense amplifier unit and a selection signal for selecting the cell block and generate a connection signal for activating the connection unit at a first time, and a sense amplifier driving control unit configured to receive the control signal and generate a sense amplifier driving signal for driving the sense amplifier unit at a second time after the first time.

Abstract: A storage device that improves ability of adjusting a resistance value level in recording and enables stable verification control is provided. VWL supplied from a second power source to a control terminal of a transistor is increased (increase portion: ?VWL) for every rerecording by verification control by a WL adjustment circuit. In the case where a variable resistive element is able to record multiple values, ?VWL is a value variable for every resistance value level of multiple value information. That is, ?VWL is a value variable according to magnitude relation of a variation range of recording resistance of the variable resistive element due to a current. In the region where the variation range of the recording resistance is large (source-gate voltage VGS of the transistor is small), ?VWL is small, while in the region where the variation range of the recording resistance is small (VGS is large), ?VWL is large.

Abstract: A nonvolatile memory device, including an X decoder coupling global lines to respective word lines to which memory cells are coupled, a voltage supply unit comprising voltage selection circuits corresponding to the respective global lines and configured to generate operating voltages, wherein each of the voltage selection circuits latches control signals, each determined according to a corresponding line enable signal and a corresponding voltage control signal, and selects and supplies one of the operating voltages in response to the control signals, and a control unit supplying a number of the line enable signals and a number of the voltage control signals to the voltage supply unit.

Abstract: A semiconductor memory device includes a first bitline pair equalized to a first voltage level by a first equalizer circuit, a second bitline pair equalized to a second voltage level by a second equalizer circuit, an isolation circuit disposed between the first bitline pair and the second bitline pair, the isolation unit configured to electrically connect or isolate the first bitline pair to or from the second bitline pair, and a sense amplifier electrically connected to the second bitline pair, the sense amplifier configured to sense a voltage difference of the second bitline pair, wherein the isolation circuit isolates one of the connections between the first bitline pair and the second bitline pair while the sense amplifier senses the voltage difference of the second bitline pair.

Abstract: A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data from a selected memory cell and adjacent memory cells to the selected memory cell in response to a request for a read operation with respect to MSB data stored in the selected memory cell. A compare circuit is configured to compare data read from the adjacent memory cells to the selected memory cell provided from the multi-bit flash memory device and to correct data read from the selected memory cells based upon the comparison result.

Abstract: A magnetic random access memory includes a magnetoresistive effect element which has a fixed layer, a recording layer and a non-magnetic layer provided between the fixed layer and the recording layer and in which the magnetization directions of the fixed layer and the recording layer are brought into a parallel state or an anti-parallel state in accordance with a direction of a current flowing between the fixed layer and the recording layer, a first contact which is connected to the recording layer and in which a contact area between the recording layer and the first contact is smaller than an area of the recording layer, and a cap layer which is provided between the first contact and the recording layer and which directly comes in contact with the first contact and which has a resistance higher than a resistance of the recording layer.

Abstract: The present invention provides a readout circuit including: a memory cell array that includes a readout target memory cell that is a data readout target; a reference memory cell having the same configuration as this memory cell; a first constant current source and a second constant current source which have the same characteristics; and a reference current source that generates, as a reference current for determining the logic level of the readout target memory cell, a current obtained by adding one constant current, out of a first constant current flowing through the first constant current source or a second constant current flowing through the second constant current source, with a reference memory cell current flowing in the reference memory cell, and by subtracting the other constant current, out of the first constant current or the second constant current, from the added current.

Abstract: The nitride semiconductor device includes an insulating layer and a metal layer formed on a nitride semiconductor layer. The insulating layer makes contact with the nitride semiconductor layer. A separation preventing layer is formed between the insulating layer and the metal layer so as to make contact with each of these layers. The separation preventing layer includes, as a main component, at least one oxide of a metal selected from a group of metals consisting of tungsten, molybdenum, chromium, titanium, nickel, hafnium, zinc, indium and yttrium.

Abstract: A nonvolatile memory cell may include a bidirectional switch having a first threshold voltage when a forward current is applied to the bidirectional switch and a second threshold voltage when a reverse current is applied to the bidirectional switch; and a variable resistor connected to the bidirectional switch in series. A state of resistance of the variable resistor may be controlled according to voltage applied to the variable resistor. A sum of a magnitude of the first threshold voltage and a magnitude of the second threshold voltage may be greater than a write voltage that is used to perform a write operation on the variable resistor.

Abstract: In an embodiment, a semiconductor memory device including a cell array with NAND strings arranged therein, wherein the device has such a program mode that bit lines and cell's channels of the NAND strings coupled thereto are initially charged in accordance with program data, and then program voltage is applied to memory cells selected in the cell array. In the program mode, a certain bit line and a program-inhibited cell's channel coupled thereto, which are initially charged to Vdd, are boosted to be higher than Vdd by capacitive coupling from the cell source line prior to the program voltage application.

Abstract: A nonvolatile memory device for preventing program disturbances includes a memory cell array block, a word line driver, and a well bias control unit. The memory cell array block includes at least one cell string having a plurality of memory cells serially connected to a bit line and alternately connected to even word lines and odd word lines. After a program verification, the word line driver drives the even word lines with a first voltage and then the odd word lines with the first voltage to drop the even word line to a voltage lower than the first voltage. The well bias control unit floats a bias of a p-well formed by high voltage NMOS transistors that apply corresponding driving voltages to the even word lines and the odd word lines according to an operation mode of a program operation, a read operation, and an erase operation.

Abstract: A nonvolatile semiconductor memory device comprises: a bit line; a source line; a memory string having a plurality of electrically data-rewritable memory transistors connected in series; a first select transistor provided between one end of the memory string and the bit line; a second select transistor provided between the other end of the memory string and the source line; and a control circuit configured to control a read operation. A plurality of the memory strings connected to one bit line via a plurality of the first select transistors. During reading of data from a selected one of the memory strings, the control circuit renders conductive the first select transistor connected to an unselected one of the memory strings and renders non-conductive the second select transistor connected to unselected one of the memory strings.

Abstract: A semiconductor memory integrated circuit having an X-row controller which includes a high-speed-operation control circuit by which when receiving a bank active signal, a period for stopping a latch circuit from receiving the X address is produced after a predetermined time has elapsed, and in the other periods, the latch circuit receives and holds the X address; a low-current-operation control circuit by which when receiving no bank active signal, the latch circuit stops receiving the X address, and when receiving the bank active signal, the latch circuit holds the X address after a predetermined time has elapsed; a circuit for selecting whether the bank active signal is output to the high-speed-operation control circuit or the low-current-operation control circuit; and a circuit for selecting whether the latch-circuit control signal from the high-speed-operation control circuit or the latch-circuit control signal from the low-current-operation control circuit is output to the latch circuit.