Patents Examined by Anita Alanko
  • Patent number: 9484215
    Abstract: In accordance with this disclosure, there is provided several inventions, including a method for etching a plurality of features in a stack comprising alternating layers above a substrate, comprising: providing a steady state flow of an etching gas, wherein the etching gas comprises: a molecule A comprising sulfur and fluorine; a molecule B comprising carbon, fluorine, and hydrogen; and a molecule C comprising carbon and fluorine and not hydrogen; forming the etching gas into a plasma; and etching the features into the stack through the plurality of alternating layers.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: November 1, 2016
    Assignee: Lam Research Corporation
    Inventors: Sanghyuk Choi, Joseph James Vegh, Kyeong-Koo Chi
  • Patent number: 9478429
    Abstract: A sacrificial-post templating method is presented for directing block copolymer (BCP) self-assembly to form nanostructures of monolayers and bilayers of microdomains. The topographical post template can be removed after directing self-assembly and, therefore, is not incorporated into the final microdomain pattern. The sacrificial posts can be a material removable using a selective etchant that will not remove the material of the final pattern block(s). The sacrificial posts may be removable, at least in part, using a same etchant as for removing one of the blocks of the BCP, for example, a negative tone polymethylmethacrylate (PMMA) when a non-final pattern block of polystyrene is removed and polydimethylsiloxane (PDMS) remains on the substrate.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: October 25, 2016
    Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Amir Tavakkoli Kermani Ghariehali, Samuel Mospens Nicaise, Karl K. Berggren, Kevin Willy Gotrik, Caroline A. Ross
  • Patent number: 9478354
    Abstract: An inductor manufacturing method includes a first step of press bonding a Cu foil onto a non-magnetic resin sheet, a second step of forming a conductor pattern by performing etching on the Cu foil, a third step of press bonding another non-magnetic resin sheet onto the conductor pattern, and a via conductor formation step of forming a via conductor that penetrates through the other resin sheet and leads to the conductor pattern. The method further includes a step of forming a body in which resin having magnetism is provided outside of a coil, by press bonding magnetic-powder-containing resin sheets onto a multilayer body, obtained by a manufacturing method including the first to third steps and the via conductor formation step, and then thermally curing the magnetic-powder-containing resin sheets.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: October 25, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hironori Suzuki, Yasushi Takeda, Noriko Shimizu, Yoichi Nakatsuji, Gota Shinohara, Junji Kurobe, Kuniaki Yosui
  • Patent number: 9460896
    Abstract: A plasma processing method performs an etching process (S101) of supplying a first fluorine-containing gas into a plasma processing space and etching a target substrate with plasma of the first fluorine-containing gas. Then, the plasma processing method performs a carbon-containing material removal process (S102) of supplying an O2 gas into the plasma processing space and removing, with plasma of the O2 gas, a carbon-containing material deposited on a member, of which a surface is arranged to face the plasma processing space, after the etching process. Thereafter, the plasma processing method performs a titanium-containing material removal process (S103) of supplying a nitrogen-containing gas and a second fluorine-containing gas into the plasma processing space and removing, with plasma of the nitrogen-containing gas and the second fluorine-containing gas, the titanium-containing material deposited on the member after the etching process.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: October 4, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Akitoshi Harada
  • Patent number: 9457502
    Abstract: Provided is a method of preparing an aluminum-resin complex in which an aluminum alloy and a resin composition are integrated with each other. More particularly, the present invention is relates to a method of preparing an aluminum-resin complex having improved bonding strength by preparing an aluminum alloy having a more uniform etching surface using an alkaline aqueous solution to which a chelating agent and a cycloamine are added and an acidic aqueous solution to which a chelating agent is added and injection-molding a resin composition using the aluminum alloy.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: October 4, 2016
    Assignee: ILKWANGPOLYMER CO., LTD.
    Inventors: Eun Kyung Lee, Yong Wan Jo
  • Patent number: 9443701
    Abstract: Disclosed is an etching method for selectively etching an oxidation layer made of silicon from a processing target object having the oxidation layer within a processing chamber of a plasma processing apparatus. The etching method includes: forming an altered layer by generating plasma of a gas containing hydrogen, nitrogen, and fluorine to alter the oxidation layer; and after the forming the altered layer, irradiating secondary electrons to the processing target object to remove the altered layer within the processing chamber, in which a negative direct current voltage is applied on an upper electrode of the plasma processing apparatus so that positive ions generated from plasma collide against the upper electrode and thus the secondary electrons are emitted from the upper electrode.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: September 13, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Hikaru Watanabe
  • Patent number: 9434146
    Abstract: A method of using a multi-layer biocidal structure includes providing a multi-layer biocidal structure having a support and a structured bi-layer on or over the support. The structured bi-layer includes a first cured layer on or over the support and a second layer in a spatial relationship to the first cured layer on a side of the first cured layer opposite the support. The structured bi-layer has at least one depth greater than the thickness of the second layer and multiple biocidal particles located only in the second layer. The multi-layer biocidal structure is located on a surface.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: September 6, 2016
    Assignee: EASTMAN KODAK COMPANY
    Inventors: Ronald Steven Cok, Mitchell Stewart Burberry
  • Patent number: 9431284
    Abstract: In a device for machining, in particular etching and/or developing, substrates, in particular wafers, in particular etching and/or developing, having a turntable, the turntable has a Venturi gap.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: August 30, 2016
    Assignee: solar-semi GmbH
    Inventor: Pirmin Muffler
  • Patent number: 9431219
    Abstract: A method that uses both electron beam (e-beam) lithography and directed self-assembly (DSA) of block copolymers (BCPs) makes guiding lines with oxidized sidewalls for use in subsequent DSA of BCPs. A series of films is deposited on a substrate including a first cross-linked polymer mat layer, a layer of resist, an etch stop layer resistant to oxygen reactive-ion-etching, a second cross-linked polymer mat layer, and an e-beam resist. After patterning and etching the second mat layer, a BCP self-assembles onto the patterned second mat layer and one of the BCP components is removed. Then the second mat layer is etched, using the remaining BCP component as an etch mask. Additional etching steps then create guiding lines of the first mat layer with oxidized sidewalls. The resulting guiding lines have better quality and lower roughness than guiding lines made with just e-beam lithography.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: August 30, 2016
    Assignee: HGST Netherlands B.V.
    Inventors: Julia Cushen, Ricardo Ruiz, Lei Wan
  • Patent number: 9431261
    Abstract: Technologies for a process used to reduce the height of a raised profile of a device. One or more raised profiles on one or more layers of a device are removed using a combined chemical-mechanical polishing/etching process. In some implementations, a protective layer is applied to a top layer of a device grown on a substrate. A combined chemical-mechanical polishing/etching process may commence whereby one or more raised profiles of the protective layer are removed through a planarization process, exposing at least a portion of a raised profile of a layer below the protective layer. Material may be removed using an etchant to reduce the height of the raised profile.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: August 30, 2016
    Assignee: THE BOEING COMPANY
    Inventors: Scott B. Singer, Joseph C. Boisvert, Daniel C. Law, Christopher M. Fetzer
  • Patent number: 9428382
    Abstract: A method for manufacturing a composite compensating balance spring is provided, the method including providing a first wafer made of a first material; providing at least one second wafer made of at least one second material having Young's modulus variations with temperature that are of opposite sign as those of the first material; joining the first wafer to the at least one second wafer to form a substrate; etching a pattern through the substrate to form a composite compensating balance spring including a first thickness of the first material and at least a second thickness of the at least one second material; and releasing the composite compensating balance spring from the substrate.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: August 30, 2016
    Assignee: The Switch Group Research and Development Ltd.
    Inventor: Thierry Hessler
  • Patent number: 9422628
    Abstract: The invention relates to a process for improving the electrical and optical performance of a transparent electrically conductive material having silver nanowires. The invention also relates to a process for manufacturing a film made of a transparent electrically conductive material, such as a transparent electrode, a transparent heating film, or a film for electromagnetic shielding. The process of the invention includes the following steps: a) a step of bringing silver nanowires into contact with an acid solution, this solution having a pH lower than 7, preferably lower than 3; and b) a step of eliminating the acid. The field of application of the invention is in particular the field of optoelectronics.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: August 23, 2016
    Assignee: Commissariat a L'Energie Atomique et aux Energies Alternatives
    Inventors: Jean-Pierre Simonato, Alexandre Carella, Caroline Celle
  • Patent number: 9418869
    Abstract: A method for etching a tungsten containing layer is provided. An etch gas is provided comprising O2 and a fluorine containing component, wherein the etch gas has at least as many oxygen atoms as fluorine atoms. A plasma is formed from the etch gas. The tungsten containing layer is etched with the plasma formed from the etch gas.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: August 16, 2016
    Assignee: Lam Research Corporation
    Inventors: Hua Xiang, Qian Fu
  • Patent number: 9412639
    Abstract: Embodiments of the invention are directed towards improving on-wafer process performance and processing at increased processing fluid/wafer temperature while maintaining good process performance. A method for processing a wafer in a process chamber is described where the process chamber includes a wafer holder having first and second sets of edge grippers for independently securing the wafer at the wafer edge during processing, treating the wafer with a first processing fluid while securing the wafer with the first set of edge grippers, but not with the second set of edge grippers, treating the wafer with a second processing fluid while securing the wafer with the first set of edge grippers, but not with the second set of edge grippers, and treating the wafer with a third processing fluid while securing the wafer with the second set of edge grippers, but not with the first set of edge grippers.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: August 9, 2016
    Assignee: TEL FSI, INC.
    Inventors: Kevin L. Siefering, David DeKraker
  • Patent number: 9411234
    Abstract: Implementations disclosed herein provide a method of reducing the topography at the alignment and overlay marks area during the writer pole photolithography process in order to reduce the wafer scale variation and reduce the writer pole photolithography process rework rate. In one implementation, an intermediate stage of a wafer for writer pole formation is generated by removing a part of at least one metallic writer pole layer on top of an intermediate stage writer pole wafer to form a recovery trench, depositing an optically transparent material on top of the wafer, wherein the thickness of the optically transparent material is higher than a target recovery trench topography, forming a photoresist pattern on top of the optically transparent material over the recovery trench, etching the optically transparent material, and removing the photoresist pattern and at least part of the remaining optically transparent material.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: August 9, 2016
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Yi Liu, Aaron M. Bowser, Dan Yu, Xiaohong Zhang
  • Patent number: 9412607
    Abstract: An isotropic etching process can be performed with high uniformity. A plasma etching method of etching an etching target layer containing silicon includes preparing a processing target object having the etching target layer in a processing chamber; removing an oxide film on a surface of the etching target layer by generating plasma of a first processing gas that contains a fluorocarbon gas or a fluorohydrocarbon gas but does not contain oxygen; removing a carbon-based reaction product generated when the removing of the oxide film by generating plasma of a second processing gas that does not contain oxygen; and etching the etching target layer without applying a high frequency bias power to a lower electrode serving as a mounting table configured to mount the processing target object thereon by generating plasma of a third processing gas containing a fluorocarbon gas or a fluorohydrocarbon gas with a microwave.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: August 9, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tomiko Kamada, Akinori Kitamura, Hiroto Ohtake, Yutaka Osada, Yuji Otsuka, Masayuki Kohno, Yusuke Takino, Eiji Suzuki
  • Patent number: 9411191
    Abstract: A method of manufacturing a linear grid for a display panel, the method including: applying a material layer for the linear grid to a substrate; laminating a negative photoresist layer having a pattern of the linear grid to a target area within an entire area of the material layer; laminating a positive photoresist layer to the entire area of the material layer; covering, with a mask for blocking ultraviolet light, areas within the entire area not including the target area, and emitting the ultraviolet light; etching the material layer according to the negative photoresist layer exposed by the ultraviolet light; and forming the pattern of the linear grid on the material layer by removing the negative photoresist layer and the positive photoresist layer from the entire area.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: August 9, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong-eun Chung, Tae-bae Kim, Il-yong Jung
  • Patent number: 9403237
    Abstract: A monolithic resonator that has a plurality of mode families is modified so that portions of the resonator have a different index of refraction than other portions of the resonator. This degrades the Q factor of one or more of the mode families, allowing pre-selection of one or more mode families over others.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: August 2, 2016
    Assignee: Oewaves, Inc.
    Inventors: Lute Maleki, Andrey Matsko, Anatoliy A. Savchenkov, Iouri Solomatine
  • Patent number: 9406978
    Abstract: The present invention relates to a power storage device including: a positive electrode having a positive-electrode current collector, a positive-electrode active material with a plurality of first projections on the positive-electrode current collector, and a first insulator on an end of each of the plurality of first projections; a negative electrode having a negative-electrode current collector, a negative-electrode active material with a plurality of second projections on a surface of the negative-electrode current collector, and a second insulator on an end of each of the plurality of second projections; a separator between the positive electrode and the negative electrode; and an electrolyte provided in a space between the positive electrode and the negative electrode and containing carrier ions. In each of the first projections and the second projections, a ratio of the height to the width is 3 or more and 1000 or less to 1, i.e. (3 to 1000):1.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: August 2, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Konami Izumi
  • Patent number: 9396911
    Abstract: A determination method, a control method, a determination apparatus, a pattern forming system, and a storage medium can determine a replacement time of a focus ring accurately and quickly. The determination method is capable of determining the replacement time of a focus ring that surrounds a substrate to increase uniformity of a pattern in a surface of the substrate when the pattern is formed by etching a film on the substrate. The determination method includes measuring a shape or a critical dimension of the pattern; and determining the replacement time of the focus ring based on the measured shape or the measured critical dimension of the pattern.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: July 19, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Keisuke Tanaka, Kazuo Sawai, Hiroshi Nagahata