Abstract: A surge protection circuit comprises a surge detection circuit 14 for detecting a surge applied to a semiconductor integrated circuit, and a protection element 15 for absorbing the surge. The protection element is connected between a signal terminal for supplying a signal to the semiconductor integrated circuit and a power source terminal for supplying a power source voltage. When the power source voltage is not larger than a voltage enough to normally operate the semiconductor integrated circuit and the surge detection circuit does not detect the surge, the protection element is set in a current limiting state. When the power source voltage is not larger than a voltage enough to normally operate the semiconductor integrated circuit and the surge detection circuit detects the surge, the protection element is set in a current non-limiting state.

Abstract: An improved ESD protection circuit having an ESD device and a triggering device to provide a continuously adjustable trigger voltage. This can be accomplished by various techniques such as placing a selected number of triggering elements in series, modifying the gate control circuitry and varying the size of the triggering elements.

Abstract: A dynamic switch contact protection circuit and technique to protect a channel switch within an electrical system by limiting transients when the switch is turned on or turned off. The protection circuit comprises switching between a high resistance path and a low resistance path. The high resistance path comprises a resistor. A bypass switch is connected in parallel to the resistor to affect the low resistance path. The protection circuit can connect or disconnect switch cards to the electrical system enabling the creation of a larger switching structure. Disconnected switch cards within a switching structure preserves system bandwidth by limiting capacitive loading. Electing which switch to close last or open first can prolong the length of usage of the switches.

Abstract: The present invention relates to an ionizer, a static charge eliminating system, an ion balance adjusting method, and a workpiece static charge eliminating method. In an ionizer, when positive and negative voltages are applied to an electrode, an amplitude Vm of the negative voltage is set to be smaller than an amplitude Vp of the positive voltage, and further, the time Tm for which the negative voltage is applied to the electrode is set to be longer than the time Tp for which the positive voltage is applied thereto.

Abstract: A power semiconductor device for an igniter comprises: a semiconductor switching device causing a current to flow through a primary side of an ignition coil or shutting off the current; and an integrated circuit driving and controlling the semiconductor switching device, wherein the integrated circuit includes: a first discharge device discharging charge accumulated on a control terminal of the semiconductor switching device and shutting off the semiconductor switching device so as to generate ignition plug spark voltage on a secondary side of the ignition coil during a normal operation; and a second discharge device slower discharging the charge accumulated on the control terminal in comparison with the first discharge device and shutting off the semiconductor switching device so that a voltage on the second side of the ignition coil is equal to or lower than the ignition plug spark voltage during an abnormal state.

Abstract: A polarity reversal protection device for motor vehicles has a detection device (10), a first connection element (22) electrically connected to a supply tap (94), a second connection device (24) having the electrical potential of the vehicle body. In case of a polarity reversal, the first connection element (22) is electrically connected to the first connection element (24) via the detector device (10). Further, the reverse polarity protection device is characterized in that a insulating layer (26) is provided between the first connection element (22) and the second connection element (24), that each of the connection elements (22, 24) has at least one receptacle (36, 38) and that the detection device (10) is at least positively engaged in at least one receptacle (36, 38).

Abstract: A MOS-type semiconductor input capacitor protection circuit and system is described. In one embodiment, the system includes a MOS device configured as an input capacitor and configured to receive an input bias voltage. A bias monitor circuit is configured to monitor the input bias voltage and apply a selective capacitor bias voltage to the input capacitor so as to limit the voltage across the input capacitor to a level below a threshold voltage.

Abstract: A DC circuit breaker arrangement for interrupting a current on a transmission line or in a HVDC circuit is provided. The DC circuit breaker arrangement comprises a first DC breaker and a second DC breaker, identical to the first DC breaker. The second DC breaker is connected in parallel with the first DC breaker on the transmission line or in the HVDC circuit and the current is divided between the first and the second DC breakers. By means of the invention, a DC circuit breaker arrangement is provided able to handle very high currents. The invention also relates to a corresponding method.

Abstract: A method for protecting against a failure within a multi-phase capacitor bank including a plurality of capacitor units each including a plurality of capacitor elements connected to each other, wherein capacitor units are connected to each other and the failure may involve two neighboring capacitor units. The method includes steps of measuring the current of each individual phase of the capacitor bank, calculating the magnitude of an unbalanced current based on the measured currents, measuring the voltage of each individual phase of the capacitor bank, calculating the magnitude of an unbalanced voltage based on the measured voltages, determining an operating point based on the calculated magnitudes of the unbalanced current and the unbalanced voltage, examining where the defined operating point is located in a specified operating region, and initializing a trip signal based on the location of the defined operating point in the specified operating region.

Abstract: A method for identifying a signal perturbation characteristic of a dechucking event within a processing chamber of a plasma processing system is provided. The method includes executing a dechucking step within the processing chamber to remove a substrate from a lower electrode, wherein the dechucking step includes generating plasma capable of providing a current to neutralize an electrostatic charge on the substrate. The method also includes employing a probe head to collect a set of characteristic parameter measurements during the dechucking step. The probe head is on a surface of the processing chamber, wherein the surface is within close proximity to a substrate surface. The method further includes comparing the set of characteristic parameter measurements against a pre-defined range. If the set of characteristic parameter measurements is within the pre-defined range, the electrostatic charge is removed from the substrate and the signal perturbation characteristic of the dechucking event is detected.

Abstract: Provided is a semiconductor apparatus which includes a power transistor that is placed between an input terminal and an output terminal, a temperature detection diode that has a cathode connected to the input terminal and an anode connected to the output terminal, a current amplifier that outputs a detection current generated by amplifying a backward leakage current flowing from the cathode to the anode of the temperature detection diode, a first conversion resistor that outputs an overheat detection signal generated by converting the detection current into a voltage, a gating circuit that performs gating of a control signal according to the overheat detection signal, and a driver circuit that outputs a drive signal to a control terminal of the power transistor based on an output signal of the gating circuit.

Abstract: Systems and methods for dynamically defending a site from lightning strikes are provided. The systems and methods involve dynamically altering electrostatic fields above the site and/or dynamically intervening in lightning discharges processes in the vicinity of the site.

Abstract: A device for providing electrostatic discharge (ESD) protection is described which includes a silicon controlled rectifier (SCR), a mechanism for triggering the SCR, and a pair of contact regions of opposing conductivity type distinct from regions of the SCR that are interposed between the cathodic and anodic regions of the SCR. The contact regions are configured to collect charge generated by the SCR. In some embodiments, the device may include a transistor and the cathodic region of the SCR may dually serve as a source contact region of the transistor. A circuit is described which includes an ESD protection device coupled between high and low voltage power supply bus bars, wherein the ESD protection device includes an SCR as well as a pair of contact regions of opposing conductivity type distinct from the SCR and interposed between the cathodic and anodic regions of the SCR.

Abstract: The invention is a photovoltaic-specific, DC load-break disconnect switch intended for applications where load-break capability is only required under abnormal operating conditions or in an emergency due to the catastrophic failure or other system components. Under normal operating conditions, the load will be switched off before a DC disconnect switch is opened. Under conditions where a load-break disconnect operation is required, an alternate path is automatically provided through a sacrificial fuse to divert current from opening contacts such that the fuse interrupts the current and not the contacts, thereby providing a substantially arcless load break. The current rating of the sacrificial fuse may be orders of magnitude less than the normal carry current. Equipment based on this invention will provide a one-time load break function that is renewable by the replacement of a fuse. The invention leverages the superior, cost-effective fault clearing capability of fuses in DC applications.

Abstract: A method includes receiving N power signals, each having a different one of N phases, over N power supply lines, where N is an integer greater than two. The method further includes selectively activating a first switch to allow a first current to flow from a first one of the N power supply lines to a second one of the N power supply lines. The method includes generating a signal based on the first current, and selectively generating a phase failure signal when the signal is less than a predetermined threshold.

Abstract: A circuit arrangement including at least two capacitors that are connected in series to a voltage is provided. The circuit arrangement also includes a voltage divider, arranged in parallel to the at least two capacitors, the voltage divider divides the voltage to the at least two capacitors, and a protective diode arranged in parallel to every capacitor in series to a series resistance in such a manner that the threshold voltage of the protective diode is lower than the admissible voltage of the capacitor arranged in parallel to the protective diode. In addition a protective circuit is arranged in parallel to the series resistances.

Abstract: A fault current limiter including: a ferromagnetic circuit formed from a ferromagnetic material and including at least a first limb, and a second limb; a saturation mechanism surrounding a limb for magnetically saturating the ferromagnetic material; a phase coil wound around a second limb; a dielectric fluid surrounding the phase coil; a gaseous atmosphere surrounding the saturation mechanism.

Abstract: A DC arc fault device and methodology includes acquiring a signal in response to a DC current. A software module identifies a parallel DC arc event when a difference between a maximum signal value and a minimum signal value exceeds a threshold. The software module also determines average signal values over multiple selected time periods and identifies a series DC arc event in response to the difference between the average values exceeding a predetermined threshold.

Abstract: A first voltage dividing circuit is connected between a power feeding line to feed power from an external power supply to an internal circuit, and a fixed potential to divide a voltage of the power feeding line. A first comparator compares a divided voltage, which has been divided by the first voltage dividing circuit, with a reference voltage, and outputs a signal to turn off a power switch inserted into the power feeding line when the divided voltage exceeds the reference voltage. A first transistor is connected between a first node where the divided voltage, which has been divided by the first voltage dividing circuit, is generated, and the fixed potential, and is turned on when the voltage of the first node exceeds a set voltage.

Abstract: An ESD circuit includes a plurality of MOS devices arranged in a stack, wherein each of the MOS devices comprises a source, a drain, and a gate; a voltage source inputting a supply voltage to the stack of MOS devices; a first plurality of resistors dividing the supply voltage to each source and each drain of the MOS devices in the stack; a second plurality of resistors biasing the supply voltage to each gate of the MOS devices in the stack; an inverter device operatively connected to the second plurality of resistors; a time lag circuit that turns the inverter device on and off; and a plurality of capacitors pulling the voltage to each gate of the MOS devices in the stack to the supply voltage upon the inverter device turning off.