Patents Examined by Anthan Tran
  • Patent number: 10468109
    Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: November 5, 2019
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Chung-Zen Chen, Yang-Chieh Lin, Chung-Shan Kuo
  • Patent number: 10460780
    Abstract: Magneto-resistive random access memory (MRAM) employing an integrated physically unclonable function (PUF) memory. The MRAM includes an MRAM array comprising an MRAM data array of data MRAM bit cells and an MRAM PUF array comprising PUF MRAM bit cells to form an integrated MRAM PUF array in the MRAM array. A resistance sensed from the PUF MRAM bit cells is compared to a reference resistance between the reference MRAM bit cells in the accessed MRAM bit cell row circuit in response to a read operation to cancel or mitigate the effect of process variations on MRAM bit cell resistance. The difference in sensed resistance and reference resistance is used to generate a random PUF output. By integrating the MRAM PUF array into an MRAM array containing an MRAM data array, access circuitry can be shared to control access to the MRAM data array and MRAM PUF, thus saving memory area.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: October 29, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Sungryul Kim, Chando Park, Seung Hyuk Kang
  • Patent number: 10424374
    Abstract: Methods, systems, and devices for programming enhancement in memory cells are described. An asymmetrically shaped memory cell may enhance ion crowding at or near a particular electrode, which may be leveraged for accurately reading a stored value of the memory cell. Programming the memory cell may cause elements within the cell to separate, resulting in ion migration towards a particular electrode. The migration may depend on the polarity of the cell and may create a high resistivity region and low resistivity region within the cell. The memory cell may be sensed by applying a voltage across the cell. The resulting current may then encounter the high resistivity region and low resistivity region, and the orientation of the regions may be representative of a first or a second logic state of the cell.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: September 24, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Redaelli, Agostino Pirovano, Innocenzo Tortorelli, Fabio Pellizzer
  • Patent number: 10410705
    Abstract: A memory includes a first memory cell; and a second memory cell. A selectable current path is coupled between the first memory cell and the second memory cell. The selectable current path includes a first transistor. A first amplifier is coupled in a first feedback arrangement between the first memory cell and the first transistor. During a read operation of the first memory cell, a current through the first memory cell is substantially equal to a current through the second memory cell. The memory cell may include a magnetic tunnel junction (MTJ).
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: September 10, 2019
    Assignee: NXP USA, INC.
    Inventors: Bruce L. Morton, Michael A. Sadd
  • Patent number: 10403355
    Abstract: A phase change memory device may include a plurality of word lines, a plurality of bit lines, a phase change memory cell, and a discharging circuit. The word lines and the bit lines may intersect each other. The phase change memory cell may be positioned at an intersection point between the word lines and the bit lines. The discharging circuit may be configured to apply a ground voltage to a non-selected word line adjacent to a selected word line or a non-selected bit line adjacent to a selected bit line.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: September 3, 2019
    Assignee: SK hynix Inc.
    Inventors: Jeong Ho Yi, Jun Ho Cheon
  • Patent number: 10403368
    Abstract: A non-volatile memory device includes a matrix memory plane with columns of memory words respectively formed on each row of the memory plane by groups of memory cells and control elements respectively associated with the memory words of each row. At least some of the control elements associated with the memory words of the corresponding row form at least one control block of B control elements disposed next to one another, adjacent to a memory block containing the B memory words disposed next to one another and associated with these B control elements, a first electrically-conducting link connecting one of the B control elements to all the control electrodes of the state transistors of the corresponding group of memory cells and B-1 second electrically-conducting link(s) respectively connecting the B-1 control element(s) to all the control electrodes of the state transistors of the B-1 corresponding group(s) of memory cells.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: September 3, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Fran├žois Tailliet, Marc Battista
  • Patent number: 10396276
    Abstract: The present invention has the purpose of providing an electric-current-generated magnetic field assist type spin-current-induced magnetization reversal element that utilizes magnetization reversal based on pure spin current. The electric-current-generated magnetic field assist type spin-current-induced magnetization reversal element of the present invention includes a first ferromagnetic metal layer with a varying magnetization direction; spin-orbit torque wiring that adjoins the first ferromagnetic metal layer and that extends in a second direction in a plane orthogonal to a first direction normal to the first ferromagnetic metal layer; and electric-current-generated magnetic field assist wiring that is arranged so as to be electrically insulated from the first ferromagnetic metal layer by an insulating layer and in which flows an electric current I0 for forming a magnetic field H0 that assists magnetization reversal of the first ferromagnetic metal layer.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: August 27, 2019
    Assignee: TDK CORPORATION
    Inventors: Tomoyuki Sasaki, Yohei Shiokawa
  • Patent number: 10388335
    Abstract: A sense component of a memory device in accordance with the present disclosure may selectively employ components having a relatively high voltage isolation characteristic in a portion of the sense component associated with relatively higher voltage signals (e.g., signals associated with accessing a ferroelectric random access memory (FeRAM) cell), and components having a relatively low voltage isolation characteristic in a portion of the sense component associated with relatively lower voltage signals (e.g., input/output signals according to some memory architectures). Voltage isolation characteristics may include isolation voltage, activation threshold voltage, a degree of electrical insulation, and others, and may refer to such characteristics as a nominal value or a threshold value. In some examples the sense component may include transistors, and the voltage isolation characteristics may be based at least in part on gate insulation thickness of the transistors in each portion of the sense component.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Kyoichi Nagata
  • Patent number: 10388368
    Abstract: Adaptive read reference voltage tracking techniques are provided that employ charge leakage mitigation. An exemplary device for use with multi-level memory cells, comprises a controller configured to: after a predefined time interval that approximates a settling time after a programming of the multi-level memory cells until a charge leakage of one or more of the multi-level memory cells has settled, determine a plurality of read reference voltages for the multi-level memory cells using a post-programming adaptive tracking algorithm; and employ the plurality of read reference voltages to read data from the multi-level memory cells. The reference voltage offsets are optionally determined based on a shift in the read reference voltages after the predefined time interval since the programming of the multi-level memory cells.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: August 20, 2019
    Assignee: Seagate Technology LLC
    Inventors: Ludovic Danjean, Sundararajan Sankaranarayanan, Erich F. Haratsch
  • Patent number: 10381086
    Abstract: Embodiments describe techniques and configurations for an apparatus including a three-dimensional (3D) memory array having a plurality of strings of memory cells, where individual strings may have memory cells that correspond to different memory blocks (e.g., multiple memory blocks per string). For example, a first set of memory cells of a string may be included in a first memory block, and a second set of memory cells of the string may be included in a second memory block. The memory device may include separator wordlines disposed between wordlines associated with the first memory block and wordlines associated with the second memory block. The separator wordlines may receive different bias voltages during various operations of the memory device. Additionally, a wordline biasing scheme may be selected to program the first memory block based on whether the second memory block is programmed. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Akira Goda, Graham Richard Wolstenholme, Tomoharu Tanaka
  • Patent number: 10360957
    Abstract: Disclosed are a semiconductor device and a semiconductor system. The semiconductor device includes a command processing circuit for generating a write enable signal and a read enable signal in response to a command, a data strobe signal processing circuit for generating a data strobe signal in response to a clock and the read enable signal or for receiving the data strobe signal in response to the write enable signal and outputting a write data strobe signal, and a data processing circuit for converting analog data into digital data in response to the write data strobe signal and the write enable signal and converting the digital data into the analog data in response to the read enable signal.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: July 23, 2019
    Assignee: SK hynix Inc.
    Inventor: Jae Young Lee
  • Patent number: 10354714
    Abstract: Systems and apparatuses for memory devices utilizing a continuous self-refresh timer are provided. An example apparatus includes a self-refresh timer configured to generate a signal periodically, wherein a period of the signal is based on a self-refresh refresh time interval, wherein the self-refresh refresh time interval is dependent on temperature information. The apparatus may further include a memory bank comprising at least a first subarray and in communication with a first subarray refresh circuit, which may include a first refresh status counter. The first refresh status counter may be in communication with the self-refresh timer and configured to receive the signal from the self-refresh timer, change a count value of the first refresh status counter in a first direction each time the signal is received, and change the count value of the first refresh status counter in a second direction each time the first subarray is refreshed.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Donald M. Morgan
  • Patent number: 10354708
    Abstract: A storage device according to one embodiment of the present technology includes a magnetization fixed layer, an intermediate layer, and a storage layer. The magnetization fixed layer is configured to have magnetization in an orientation perpendicular to a film surface and a constant magnetization direction. The intermediate layer includes a non-magnetic body and is disposed on the magnetization fixed layer. The storage layer includes an outer circumferential portion and a center portion, is disposed to face the magnetization fixed layer with the intermediate layer sandwiched therebetween, and is configured to have a variable magnetization direction, the outer circumferential portion having magnetization in an orientation perpendicular to a film surface, the center portion being formed by being surrounded by the outer circumferential portion and having magnetization inclined from the orientation perpendicular to the film surface.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: July 16, 2019
    Assignee: SONY CORPORATION
    Inventors: Hiroyuki Ohmori, Masanori Hosomi, Kazuhiro Bessho, Yutaka Higo, Kazutaka Yamane, Hiroyuki Uchida
  • Patent number: 10347335
    Abstract: A retainer node circuit is provided that can retain state information of a volatile circuit element (e.g., a flip-flop, latch, switch, register, etc.) of an electronic device for planned or unplanned power-down events. The retainer node circuit can include a resistive-switching memory cell that is nonvolatile, having very fast read and write performance. Coupled with power management circuitry, the retainer node circuit can be activated to receive and store a signal (e.g., bit) output by the volatile circuit element, and activated to output the stored signal. Various embodiments disclose non-volatile retention of state information for planned shut-down events as well as unplanned shut-down events. With read and write speeds in the tens of nanoseconds, sleep mode can be provided for volatile circuit elements between clock cycles of longer time-frame applications, enabling intermittent power-down events between active periods. This enables reduction in power without loss of activity for an electronic device.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: July 9, 2019
    Assignee: CROSSBAR, INC.
    Inventors: Mehdi Asnaashari, Hagop Nazarian
  • Patent number: 10347820
    Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, first to fourth magnetic layers, first and second intermediate layers, and a controller. The conductive layer includes first, to fifth portions. The first magnetic layer is separated from the third portion. The second magnetic layer is provided between the third portion and the first magnetic layer. The first intermediate layer is provided between the first and second magnetic layers. The third magnetic layer is separated from the fourth portion. The fourth magnetic layer is provided between the fourth portion and the third magnetic layer. The second intermediate layer is provided between the third and fourth magnetic layers. The controller is electrically connected to the first and second portions. The controller implements a first operation of supplying a first current to the conductive layer, and a second operation of supplying a second current to the conductive layer.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: July 9, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Altansargai Buyandalai, Satoshi Shirotori, Yuichi Ohsawa, Hideyuki Sugiyama, Mariko Shimizu, Hiroaki Yoda, Tomoaki Inokuchi
  • Patent number: 10340013
    Abstract: A memory device includes a semiconductor column extending above a substrate, a first conductive layer on a first side of the semiconductor column, a second conductive layer on a second side of the semiconductor column, opposite to the first conductive layer, a third conductive layer above or below the first conductive layer and on the first side of the semiconductor column, a fourth conductive layer on the second side of the semiconductor column, opposite to the third conductive layer, and a bit line connected to the semiconductor column. During reading in which a positive voltage is applied to the bit line, first, second, third, and fourth voltages applied to the first, second, third, and fourth conductive layers, respectively, wherein the first voltage and the third voltage are higher than each of the second voltage and the fourth voltage, and the third voltage is higher than the first voltage.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: July 2, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Takuya Futatsuyama, Kenichi Abe
  • Patent number: 10332579
    Abstract: The present disclosure provides a dynamic random access memory (DRAM) including a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data. The second cell is configured to have a stored electrical energy by being programmed with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a refresh rate of the refresh unit to a first refresh rate when the stored electrical energy of the second cell becomes lower than a threshold electrical energy, wherein the threshold electrical energy is higher than a standard electrical energy for determining binary logic.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: June 25, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Patent number: 10304523
    Abstract: A memory device with low power consumption is provided. The memory device includes a sense amplifier, bit lines, memory cells, and first transistors. The bit lines are provided over a layer comprising the sense amplifier. The memory cells are provided over a layer comprising the bit lines. The memory cell includes a second transistor and a capacitor. The sense amplifier and the bit lines are electrically connected to each other through the first transistors. The sense amplifier may include at least one layer of a conductor.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: May 28, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Tatsuya Onuki
  • Patent number: 10304525
    Abstract: The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SKAM cell inverters may be asymmetrical in size. The memory may comp rise various boost circuits to allow low voltage operation or application of distinguished supply voltages.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: May 28, 2019
    Assignee: Xenergic AB
    Inventors: Babak Mohammadi, Joachim Neves Rodrigues
  • Patent number: 10297337
    Abstract: Apparatuses and techniques for counting 0 or 1 bits in a set of bits using both serial and parallel processes. The counting process includes a hierarchy in which the count from different parallel processes at one level in the hierarchy are passed to a smaller number of different parallel processes at a lower level in the hierarchy. A final count is obtained by an accumulator below the lowest level of the hierarchy. The position and configuration of the circuits can be set to equalize a number of circuits which process the different bits, so that a maximum delay relative to the accumulator is equalized.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: May 21, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Wanfang Tsai, Hung-Szu Lin, Yi-Fang Chen