Patents Examined by Anthan Tran
  • Patent number: 11176983
    Abstract: Some embodiments of the present disclosure relate to a memory device. The memory device includes an active current path including a magnetic tunnel junction (MTJ); and a reference current path including a reference resistance element. The reference resistance element has a resistance that differs from a resistance of the MTJ. An asynchronous, delay-sensing element has a first input coupled to the active current path and a second input coupled to the reference current path. The asynchronous, delay-sensing element is configured to sense a timing delay between a first rising or falling edge voltage on the active current path and a second rising or falling edge voltage on the reference current path. The asynchronous, delay-sensing element is further configured to determine a data state stored in the MTJ based on the timing delay.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jack Liu, Charles Chew-Yuen Young
  • Patent number: 11164632
    Abstract: A nonvolatile memory device includes a memory cell array, an input current generator, an operation cell array and an analog-to-digital converter. The memory cell array includes NAND strings storing multiplicand data, wherein first ends of the NAND strings are connected to bitlines and second ends of the NAND strings output multiplication bits corresponding to bitwise multiplication of the multiplicand data stored in the NAND strings and multiplier data loaded on the bitlines. The input current generator generates input currents. The operation cell array includes switching transistors. Gate electrodes of the switching transistors are connected to the second ends of the NAND strings. The switching transistors selectively sum the input currents based on the multiplication bits to output the output currents. The analog-to-digital converter converts the output currents to digital values.
    Type: Grant
    Filed: February 27, 2021
    Date of Patent: November 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Se-Hwan Park
  • Patent number: 11158389
    Abstract: A memory device includes a semiconductor column extending above a substrate, a first conductive layer on a first side of the semiconductor column, a second conductive layer on a second side of the semiconductor column, opposite to the first conductive layer, a third conductive layer above or below the first conductive layer and on the first side of the semiconductor column, a fourth conductive layer on the second side of the semiconductor column, opposite to the third conductive layer, and a bit line connected to the semiconductor column. During reading in which a positive voltage is applied to the bit line, first, second, third, and fourth voltages applied to the first, second, third, and fourth conductive layers, respectively, wherein the first voltage and the third voltage are higher than each of the second voltage and the fourth voltage, and the third voltage is higher than the first voltage.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: October 26, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Takuya Futatsuyama, Kenichi Abe
  • Patent number: 11152075
    Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: October 19, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Kiwamu Watanabe, Kengo Kurose
  • Patent number: 11152060
    Abstract: Some embodiments include apparatuses having non-volatile memory cells, each of the non-volatile memory cells to store more than one bit of information; data lines, at most one of the data lines electrically coupled to each of the non-volatile memory cells; a circuit including transistors coupled to the data lines, the transistors including gates coupled to each other; and an encoder including input nodes and output nodes, the input nodes to receive input information from the data lines through the transistors, and the output nodes to provide output information having a value based on a value of the input information.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: October 19, 2021
    Assignee: Intel Corporation
    Inventors: Xiaofei Wang, Dinesh Somasekhar, Clifford Ong, Eric A Karl, Zheng Guo, Gordon Carskadon
  • Patent number: 11139005
    Abstract: An internal voltage generation device includes: a voltage detection circuit generating a first detection signal by comparing a first voltage with a target voltage; a voltage difference detection circuit enabled in response to an operation enable signal, generating a second detection signal by comparing a voltage difference between the first voltage and a second voltage with a target gap voltage; a control circuit generating a first up/down code and the operation enable signal according to the first detection signal, and generating a second up/down code according to the second detection signal; a first voltage generation circuit generating the first voltage by down-converting a supply voltage, and adjusting a level of the first voltage according to the first up/down code; and a second voltage generation circuit generating the second voltage by boosting up the supply voltage, and adjusting a level of the second voltage according to the second up/down code.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: October 5, 2021
    Assignee: SK hynix Inc.
    Inventor: Sang-Hoon Lee
  • Patent number: 11114163
    Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: September 7, 2021
    Assignee: SK hynix Inc.
    Inventors: Hee Joung Park, Kyeong Seung Kang, Won Chul Shin
  • Patent number: 11100973
    Abstract: Systems and apparatuses for memory devices utilizing a continuous self-refresh timer are provided. An example apparatus includes a self-refresh timer configured to generate a signal periodically, wherein a period of the signal is based on a self-refresh refresh time interval, wherein the self-refresh refresh time interval is dependent on temperature information. The apparatus may further include a memory bank comprising at least a first subarray and in communication with a first subarray refresh circuit, which may include a first refresh status counter. The first refresh status counter may be in communication with the self-refresh timer and configured to receive the signal from the self-refresh timer, change a count value of the first refresh status counter in a first direction each time the signal is received, and change the count value of the first refresh status counter in a second direction each time the first subarray is refreshed.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: August 24, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Donald M. Morgan
  • Patent number: 11094361
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit has an operative magnetic tunnel junction (MTJ) device configured to store a data state. The operative MTJ device is coupled to a bit-line. A regulating access apparatus is coupled between the operative MTJ device and a first word-line. The regulating access apparatus has one or more regulating MTJ devices that are configured to control a current provided to the operative MTJ device.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: August 17, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Katherine Chiang, Chung Te Lin, Min Cao, Yuh-Jier Mii, Sheng-Chih Lai
  • Patent number: 11081177
    Abstract: Broadly speaking, embodiments of the present techniques provide apparatus and methods for generating a reference current for a memory array sensing scheme, and for using the generated reference current to sense the state of memory cells within the memory array. The generated reference current is particularly suitable for distinguishing between a high resistance state and a low resistance state.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: August 3, 2021
    Assignee: Arm Limited
    Inventor: Akshay Kumar
  • Patent number: 11036631
    Abstract: The present disclosure includes apparatuses and methods related to configurable trim settings on a memory device. An example apparatus can include configuring a set of trim settings for an array of memory cells such that the array of memory cells have desired operational characteristics in response to being operated with the set of trim settings.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: June 15, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
  • Patent number: 11031059
    Abstract: Magnetic random-access memory (MRAM) circuits are provided herein. In one example implementation, an MRAM circuit includes control circuitry coupled to a magnetic tunnel junction (MTJ) element in series with a selector element. This control circuitry is configured to adjust current through the selector element when the selector element is in a conductive state. The circuit also includes a compensation circuitry configured to compensate for a offset voltage across the selector element in the conductive state based on adjustments to the current through the selector element. An output circuit is also configured to report a magnetization state of the MTJ element.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: June 8, 2021
    Assignee: Sandisk Technologies LLC
    Inventors: Christopher J. Petti, Tz-Yi Liu, Ali Al-Shamma, Yoocharn Jeon
  • Patent number: 11031050
    Abstract: In one aspect, the invention concerns a memory system that compensates for power level variations in sense amplifiers for multilevel memory. For example, a compensation circuit can be employed to compensate for current or voltage variations in the power supplied to multilevel memory sense amplifiers. As another example, compensation can be accomplished by application of a bias voltage to the power supply. Another example is a sense amplifier configured with improved input common mode voltage range. Such sense amplifiers can be two-pair and three-pair sense amplifiers. Further examples of the invention include more simplified sense amplifier configurations, and sense amplifiers having reduced leakage current.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: June 8, 2021
    Assignee: Silicon Storage Technology, Inc.
    Inventor: Hieu Van Tran
  • Patent number: 11031073
    Abstract: A Static Random Access Memory (SRAM) cell includes a first boundary and a second boundary opposite to, and parallel to, the first boundary, a first and a second pull-up transistor, a first and a second pull-down transistor forming cross-latched inverters with the first and the second pull-up transistors, and a first and a second pass-gate transistor. Each of the first and the second pull-up transistors, the first and the second pull-down transistors, and the first and the second pass-gate transistors includes a bottom plate as a first source/drain region, a channel over the bottom plate, and a top plate over the channel as a second source/drain region. The SRAM cell further includes a first, a second, a third, and a fourth active region, each extending from the first boundary to the second boundary.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 11017821
    Abstract: A magnetic recording array includes: a plurality of domain wall moving elements; a first wiring which is electrically connected to a reference potential and is electrically connected to at least one domain wall moving element of the plurality of domain wall moving elements; a second wiring which is electrically connected to at least two or more domain wall moving elements of the plurality of domain wall moving elements; a first switching element which is connected between each of the domain wall moving elements and the first wiring; and a second switching element which is connected between each of the domain wall moving elements and the second wiring, wherein an OFF resistance of the first switching element is smaller than an OFF resistance of the second switching element.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: May 25, 2021
    Assignee: TDK CORPORATION
    Inventors: Takuya Ashida, Tatsuo Shibata
  • Patent number: 11004518
    Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 11, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kiyohiko Sakakibara, Hiroki Yabe, Ken Oowada, Masaaki Higashitani
  • Patent number: 11004481
    Abstract: An internal voltage generation device includes: a voltage detection circuit generating a first detection signal by comparing a first voltage with a target voltage; a voltage difference detection circuit enabled in response to an operation enable signal, generating a second detection signal by comparing a voltage difference between the first voltage and a second voltage with a target gap voltage; a control circuit generating a first up/down code and the operation enable signal according to the first detection signal, and generating a second up/down code according to the second detection signal; a first voltage generation circuit generating the first voltage by down-converting a supply voltage, and adjusting a level of the first voltage according to the first up/down code; and a second voltage generation circuit generating the second voltage by boosting up the supply voltage, and adjusting a level of the second voltage according to the second up/down code.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: May 11, 2021
    Assignee: SK hynix Inc.
    Inventor: Sang-Hoon Lee
  • Patent number: 10991431
    Abstract: A semiconductor memory device includes a first wiring, a first memory transistor connected to the first wiring, a first transistor connected between the first wiring and the first memory transistor, a second transistor connected between the first wiring and the first transistor, and second to fourth wirings respectively connected to gate electrodes of the first memory transistor, the first transistor, and the second transistor. From a first timing to a second timing, a voltage difference between the first wiring and the third wiring is maintained at a predetermined value, a voltage difference between the third wiring and the fourth wiring is maintained at a predetermined value, a voltage of the first wiring becomes larger than a voltage of the third wiring, and the voltage of the third wiring becomes larger than a voltage of the fourth wiring.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: April 27, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuki Sakaguchi, Tatsuo Izumi, Masashi Yoshida
  • Patent number: 10978164
    Abstract: A memory device includes a semiconductor column extending above a substrate, a first conductive layer on a first side of the semiconductor column, a second conductive layer on a second side of the semiconductor column, opposite to the first conductive layer, a third conductive layer above or below the first conductive layer and on the first side of the semiconductor column, a fourth conductive layer on the second side of the semiconductor column, opposite to the third conductive layer, and a bit line connected to the semiconductor column. During reading in which a positive voltage is applied to the bit line, first, second, third, and fourth voltages applied to the first, second, third, and fourth conductive layers, respectively, wherein the first voltage and the third voltage are higher than each of the second voltage and the fourth voltage, and the third voltage is higher than the first voltage.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: April 13, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takuya Futatsuyama, Kenichi Abe
  • Patent number: 10978512
    Abstract: An electronic device and a method for fabricating the same are provided. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a plurality of first lines extending in a first direction; a plurality of second lines extending in a second direction that intersects with the first direction; a plurality of variable resistance elements disposed between the first lines and the second lines and located at intersections of the first lines and the second lines; and a plug connected to a first portion of each of the first lines, wherein the plug comprises a conductive layer and a material layer having a resistance value higher than that of the conductive layer.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: April 13, 2021
    Assignee: SK hynix Inc.
    Inventor: Jae-Yeon Lee