Patents Examined by Anthan Tran
  • Patent number: 10840444
    Abstract: A phase change memory apparatus comprises at least one heating layer; and at least one phase change layer comprising a vanadium dioxide layer, wherein each of the at least one phase change layer is set corresponding to each of the at least one heating layer, the at least one heating layer is configured to heat the at least one phase change layer.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: November 17, 2020
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Ji-Wei Hou, Zhi-Quan Yuan, Kai Liu, Peng Liu, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 10839930
    Abstract: A magnetic domain wall type analog memory element includes: a magnetization fixed layer in which magnetization is oriented in a first direction; a non-magnetic layer provided in one surface of the magnetization fixed layer; a magnetic domain wall drive layer including a first area in which magnetization is oriented in the first direction, a second area in which magnetization is oriented in a second direction opposite to the first direction, and a magnetic domain wall formed as an interface between the areas and provided to sandwich the non-magnetic layer with respect to the magnetization fixed layer; and a current controller configured to cause a current to flow between the magnetization fixed layer and the second area at the time of reading.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: November 17, 2020
    Assignee: TDK CORPORATION
    Inventor: Tomoyuki Sasaki
  • Patent number: 10811094
    Abstract: A memory device may include a memory cell array including a plurality of memory cells and a compensation resistor electrically connected to the memory cell array. The compensation resistor may generate a cell current compensating for a voltage drop generated in a parasitic resistor of a signal line connected to at least one memory cell of the plurality of memory cells. The compensation circuit may control a magnitude of resistance of a compensation resistor upon receiving an address corresponding to the memory cell. The compensation circuit may increase a magnitude of the cell current based on adjusting the magnitude of resistance of the compensation resistor to be substantially equal to a resistance value of the parasitic resistor.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: October 20, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Venkataramana Gangasani, Ji-hoon Lim
  • Patent number: 10811084
    Abstract: The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SRAM cell inverters may be asymmetrical in size. The memory may comprise various boost circuits to allow low voltage operation or application of distinguished supply voltages.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: October 20, 2020
    Assignee: XENERGIC AB
    Inventors: Babak Mohammadi, Joachim Neves Rodrigues
  • Patent number: 10797229
    Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, first to fourth magnetic layers, first and second intermediate layers, and a controller. The conductive layer includes first, to fifth portions. The first magnetic layer is separated from the third portion. The second magnetic layer is provided between the third portion and the first magnetic layer. The first intermediate layer is provided between the first and second magnetic layers. The third magnetic layer is separated from the fourth portion. The fourth magnetic layer is provided between the fourth portion and the third magnetic layer. The second intermediate layer is provided between the third and fourth magnetic layers. The controller is electrically connected to the first and second portions. The controller implements a first operation of supplying a first current to the conductive layer, and a second operation of supplying a second current to the conductive layer.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: October 6, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Altansargai Buyandalai, Satoshi Shirotori, Yuichi Ohsawa, Hideyuki Sugiyama, Mariko Shimizu, Hiroaki Yoda, Tomoaki Inokuchi
  • Patent number: 10790002
    Abstract: A non-volatile data retention circuit includes a complementary latch configured to generate and store complementary non-volatile spin states corresponding to an input signal when in a write mode, and to concurrently generate a first charge current signal and a second charge current corresponding to the complementary non-volatile spin states when in read mode, and a differential amplifier coupled to the complementary latch and configured to generate an output signal based on the first and second charge current signals.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: September 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Titash Rakshit, Ryan Hatcher, Jorge A. Kittl
  • Patent number: 10783942
    Abstract: Examples of the present disclosure provide apparatuses and methods for performing a corner turn using a modified decode. An example apparatus can comprise an array of memory cell and decode circuitry coupled to the array and including logic configured to modify an address corresponding to at least one data element in association with performing a corner turn operation on the at least one data element. The logic can be configured to modify the address corresponding to the at least one data element on a per column select basis.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: September 22, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Graham Kirsch, Martin Steadman
  • Patent number: 10777234
    Abstract: An off-chip driver including a first driving circuit is provided. The first driving circuit is used to adjust a slew rate of the off-chip driver. The first driving circuit includes a first pre-driver, a switch string, and a first output stage. The first pre-driver receives a read signal and a first pre-driver control signal. The switch string is configured to perform a voltage division operation in cooperation with the first pre-driver on a power supply voltage according to the read signal, so as to generate a first output stage control signal. The first output stage generates a data signal according to the first output stage control signal.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: September 15, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Taihei Shido
  • Patent number: 10777253
    Abstract: A memory array comprises a data block comprising N serially connected cells. Each cell of the cells comprises a memory element storing a respective bit of the word, a charge adding unit and a switching logic. The last cell of the cells is further configured to receive a sequence of M bits. The memory array further comprises an output block serially connected to the data block. The output block comprises a result accumulation unit. The memory array is configured to operate in accordance with a 3-phase clocking scheme having a sequence of M groups of clock cycles associated with the respective sequence of M bits. The memory array is configured such that a successive and repetitive application of the three phases enables an application of a phase during each clock cycle of the M groups.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Riduan Khaddam-Aljameh, Manuel Le Gallo-Bourdeau, Abu Sebastian, Evangelos Stavros Eleftheriou, Pier Andrea Francese
  • Patent number: 10770148
    Abstract: An operation method of a nonvolatile memory device includes applying a program voltage to a selected word line and programming a selected memory cell connected to the selected word line; reading an adjacent memory cell connected to an adjacent word line of the selected word line; and verifying the selected memory cell by adjusting charge sharing between the selected memory cell and a sensing node, which is connected to the selected memory cell through a bit line.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: September 8, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Taeck Jung, So-Yeong Gwak, Sang-Wan Nam
  • Patent number: 10770125
    Abstract: Methods for sensing ferroelectric memory devices and apparatuses using the same have been disclosed. One such apparatus includes a ferroelectric memory cell coupled to a data line, a reference capacitance, and a common node coupled between the data line and the reference capacitance. A current mirror circuit is coupled to the data line and the reference capacitance. During a sense operation, the common node is configured to be at a fixed voltage and the current mirror circuit is configured to mirror displacement current from the reference capacitance to the ferroelectric memory cell.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Adam D. Johnson
  • Patent number: 10762959
    Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: September 1, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chung H. Lam, Scott C. Lewis, Thomas M. Maffitt, Jack Morrish
  • Patent number: 10755791
    Abstract: According to an embodiment, a semiconductor storage device includes a first memory cell and a control circuit. The first memory cell is configured to store first data. The control circuit is configured to apply a first voltage to a source of the first memory cell in a read operation of the first data in the first memory cell, and to apply a second voltage to the source of the first memory cell in a verify operation of the first data in the first memory cell. The second voltage is lower than the first voltage.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: August 25, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshihiko Kamata, Takuyo Kodama, Yuki Ishizaki, Yoko Deguchi
  • Patent number: 10748584
    Abstract: Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: August 18, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Tsugio Takahashi, Zer Liang
  • Patent number: 10748964
    Abstract: An electronic device and a method for fabricating the same are provided. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a plurality of first lines extending in a first direction; a plurality of second lines extending in a second direction that intersects with the first direction; a plurality of variable resistance elements disposed between the first lines and the second lines and located at intersections of the first lines and the second lines; and a plug connected to a first portion of each of the first lines, wherein the plug comprises a conductive layer and a material layer having a resistance value higher than that of the conductive layer.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: August 18, 2020
    Assignee: SK hynix Inc.
    Inventor: Jae-Yeon Lee
  • Patent number: 10741233
    Abstract: A semiconductor memory device comprises a first memory cell with a first variable resistance element. A first write controller is configured to write data into the first memory cell using a first voltage that is supplied via a first wiring. A second write controller configured to write data into the first memory cell using a second voltage that is lower than the first voltage when the first voltage supplied via the first wiring is reduced below a threshold level.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: August 11, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masahiro Takahashi, Ryousuke Takizawa
  • Patent number: 10734083
    Abstract: A voltage driver includes a voltage divider, a first transistor and a second transistor. The voltage divider is connected with a first voltage source and a second voltage source, and generates a first bias voltage. A drain terminal of the first transistor is connected with a third voltage source. A gate terminal of the first transistor is connected with the voltage divider to receive the first bias voltage. A drain terminal of the second transistor is connected with a source terminal of the first transistor. A gate terminal of the second transistor receives a second bias voltage. A source terminal of the second transistor is connected with a fourth voltage source. The first transistor and the second transistor are of the same conductivity type and match each other. The source terminal of the first transistor generates an output voltage.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: August 4, 2020
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Yu Wu, Wei-Chiang Ong, Chih-Yang Huang
  • Patent number: 10720209
    Abstract: A resistive memory element or device includes: a first, main, memory cell area including a plurality of first resistive memory cells; and a second, buffer, memory cell area including a plurality of second resistive memory cells. The first resistive memory cells of the main memory cell area are configured to store data therein, and the second resistive memory cells of the buffer memory cell area are configured to temporarily store portions of the data therein for at least a stabilization time period while the portions of the data stabilize in the main memory cell area.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: July 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun Kook Park, Young Hoon Oh, Chi Weon Yoon, Yong Jun Lee, Chea Ouk Lim
  • Patent number: 10719122
    Abstract: A device in an automated environment can detect patterns in the user's interactions with accessories in the automated environment and can provide feedback to the user based on the patterns. Examples include: suggesting automation of particular actions based on the patterns; suggesting actions that conform to the pattern when the user performs part of the pattern; or suggesting changes to a pattern to conform to a preferred pattern.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: July 21, 2020
    Assignee: Apple Inc.
    Inventors: Lukas M. Marti, Ronald Keryuan Huang
  • Patent number: 10714183
    Abstract: A high voltage switch circuit includes a first transistor, a first depletion mode transistor, a level shifter, a control signal generator, a second transistor and a second depletion mode transistor. The first transistor transmits the second driving voltage to an output terminal in response to a first gate signal. The first depletion mode transistor transmits the second driving voltage to the first transistor in response to feedback from the output terminal. The control signal generator generates first and second control signals in response to a level-shifted enable signal. The second transistor has a gate electrode connected to the first voltage and is turned on and off in response to the second control signal at a first end of the second transistor. The second depletion mode transistor is connected between a second end of the second transistor and the output terminal, and has a gate electrode receiving the first control signal.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: July 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Kyu Kim, Young-Sun Min, Dae-Seok Byeon, Ho-Kil Lee