Patents Examined by Anthan Tran
  • Decoding system and physical layout for analog neural memory in deep learning artificial neural network
    Patent number: 11423979
    Abstract: Various embodiments of word line decoders, control gate decoders, bit line decoders, low voltage row decoders, and high voltage row decoders and various types of physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. Shared and segmented embodiments of high voltage row decoders are disclosed.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: August 23, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly, Han Tran, Kha Nguyen, Hien Pham
  • Integrated assemblies
    Patent number: 11423972
    Abstract: Some embodiments include an integrated assembly having a memory deck over a base, and having an array of memory cells along the memory deck. The array includes rows which extend along a row direction and columns which extend along a column direction. Wordlines are along the rows and digit-lines are along the columns. CONTROL circuitry is along the base and includes WORDLINE DRIVER circuitry coupled with the wordlines. The CONTROL circuitry is subdivided amongst banks. The banks are elongated along the row direction. Each of the banks is subdivided amongst a series of sections, with the sections being arranged in section rows which extend along the row direction. Each of the sections includes a series of patches, with the patches including INPUT/OUTPUT circuitry. The patches are arranged in groups, with the groups sharing portions of the WORDLINE DRIVER circuitry.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: August 23, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jiyun Li, Yuan He
  • Processing of unassigned row address in a memory
    Patent number: 11417388
    Abstract: Semiconductor devices that include circuitry to mitigate unstable or metastable states in logic circuits in response to receipt of an unassigned row address. The semiconductor device may include one or more logic circuits that are configured to adjust particular address-based control signals to mitigate processing based on the unassigned row address. For example, the one or more logic circuits may override processing of the unassigned row address to provide control signals that correspond to an assigned row address, which may allow the semiconductor device to operate in a known state, rather than performing operations based on an unassigned row address.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Takayuki Miyamoto, Satoshi Yamanaka
  • Reserved rows for row-copy operations for semiconductor memory devices and associated methods and systems
    Patent number: 11417387
    Abstract: Methods, systems, and apparatuses for memory devices (e.g., DRAM) including one or more reserved rows for row-copy operations are described. Such a memory device may include a memory array having a set of rows, where one or more rows of the set are reserved for row-copy operations and hidden (un-addressable) from access commands directed to the memory array. The reserved rows may include a dummy row configured to provide a uniform processing conditions to the memory array. Additionally, or alternatively, the reserved rows may include a buffer row configured to provide a buffer zone in the memory array. In some embodiments, the memory device may perform the row-copy operations in response to detecting row hammering activities. The row-copy operations may mitigate the risks associated with the row hammering activities by routing the row hammering activities to the reserved rows.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Randall J. Rooney
  • Semiconductor memory apparatus
    Patent number: 11417385
    Abstract: A semiconductor memory apparatus is provided. The semiconductor memory apparatus includes a temperature sensor, a plurality of memory blocks and a refresh controller. The temperature sensor detects a device temperature inside the semiconductor memory apparatus to generate a corresponding temperature signal. Each of the memory blocks includes a memory cell array having a plurality of volatile memory cells, and a plurality of word lines. The refresh controller monitors accesses to the word lines, detects accesses that occur a predetermined number of times within a predetermined period, and assigns a refresh operation corresponding to the refresh operation command to a first refresh operation or a second refresh operation.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: August 16, 2022
    Assignee: Winbond Electronics Corp.
    Inventor: Yutaka Ito
  • Memory device and method of operating the same
    Patent number: 11416174
    Abstract: The present disclosure relates to a semiconductor system including a semiconductor device and a controller. The semiconductor device outputs a temperature code corresponding to an internal temperature thereof. The controller controls, based on the temperature code, the semiconductor device to set a temperature measurement mode among at least two temperature measurement modes having different temperature measurement periods and to measure the internal temperature in the set temperature measurement mode.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: August 16, 2022
    Assignee: SK hynix Inc.
    Inventor: Chan Keun Kwon
  • Apparatus with voltage protection mechanism
    Patent number: 11398468
    Abstract: An apparatus includes a protection circuit electrically connected to first and second voltage domains. The protection circuit includes a first silicon-controlled rectifier (SCR) and a second SCR connected in anti-parallel configuration. The first SCR is configured to connect the first voltage domain and the second voltage domain based on detection of a first triggering condition. The second SCR is configured to connect the second voltage domain and the first voltage domain based on detection of a second triggering condition. The protection circuit is configured to isolate the first and second voltage domains without the triggering conditions.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: July 26, 2022
    Assignee: Micron Technology, Inc.
    Inventors: James E. Davis, Milind Nemchand Furia, Michael D. Chaine, Eric J. Smith
  • Compact non-volatile memory device
    Patent number: 11393537
    Abstract: A non-volatile memory device includes a substrate, a plurality of memory words, a control block, a first electrically-conducting link, and a plurality of second electrically-conducting links. The substrate includes a substantially planar surface. The memory words include B memory words disposed at the substantially planar surface. The control block includes B control elements disposed at the substantially planar surface. The first electrically-conducting link is disposed in a first plane parallel to the substantially planar surface. The first electrically-conducting link connects one of the B control elements to a memory word of the memory words. The plurality of second electrically-conducting links includes B-1 second electrically-conducting links respectively connecting B-1 remaining control elements to B-1 corresponding memory words of the plurality of memory words.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: July 19, 2022
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: François Tailliet, Marc Battista
  • Selective reading of memory with improved accuracy
    Patent number: 11379286
    Abstract: This disclosure relates to selectively performing a read with increased accuracy, such as a self-reference read, from a memory. In one aspect, data is read from memory cells, such as magnetoresistive random access memory (MRAM) cells, of a memory array. In response to detecting a condition associated with reading from the memory cells, a self-reference read can be performed from at least one of the memory cells. For instance, the condition can indicate that data read from the memory cells is uncorrectable via decoding of error correction codes (ECC). Selectively performing self-reference reads can reduce power consumption and/or latency associated with reading from the memory compared to always performing self-reference reads.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: July 5, 2022
    Assignee: OVONYX MEMORY TECHNOLOGY, LLC
    Inventors: Wayne Kinney, Gurtej S. Sandhu
  • System and method for performing memory operations in RRAM cells
    Patent number: 11373704
    Abstract: A resistive RAM (RRAM) device has a bit line, a word line, a source line carrying a bias voltage that is a substantially static and non-negative voltage, an RRAM cell, and a bit line control coupled to the bit line circuit. The RRAM cell includes a gate node coupled to the word line, a bias node coupled to the source line, and a bit line node coupled to the bit line. The bit line control circuit is configured to generate non-negative command voltages to perform respective memory operations on the RRAM cell.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: June 28, 2022
    Assignee: Hefei Reliance Memory Limited
    Inventor: Brent Steven Haukness
  • Apparatuses and methods for selective row refreshes
    Patent number: 11361808
    Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: June 14, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Debra M. Bell, Jeff A. McClain, Brian P. Callaway
  • Multiplexed signal development in a memory device
    Patent number: 11360704
    Abstract: Methods, systems, and devices related to multiplexed signal development in a memory device are described. In one example, an apparatus in accordance with the described techniques may include a set of memory cells, a sense amplifier, and a set of signal development components each associated with one or more memory cells of the set of memory cells. The apparatus may further include a selection component, such as a signal development component multiplexer, that is coupled with the set of signal development components. The selection component may be configured to selectively couple a selected signal development component of the set of signal development components with the sense amplifier, which may support examples of signal development during overlapping time intervals.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: June 14, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Dmitri A. Yudanov, Shanky Kumar Jain
  • Semiconductor memory device and method of operating the same
    Patent number: 11361828
    Abstract: Provided herein may be a semiconductor memory device. The semiconductor memory device may include: a memory cell array including a plurality of memory blocks; a peripheral circuit configured to apply an erase voltage to a source line and a plurality of select lines of a selected memory block among the plurality of memory blocks during an erase operation; and a control logic configured to control the peripheral circuit to form a trap in an area below at least one of a plurality of source select transistors included in the selected memory block, before the erase voltage is applied to the selected memory block.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: June 14, 2022
    Assignee: SK hynix Inc.
    Inventors: Dae Hwan Yun, Myeong Won Lee
  • Threshold voltage setting with boosting read scheme
    Patent number: 11348649
    Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: May 31, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Kiyohiko Sakakibara, Hiroki Yabe, Ken Oowada, Masaaki Higashitani
  • Giant spin hall-based compact neuromorphic cell optimized for differential read inference
    Patent number: 11348629
    Abstract: A non-volatile data retention circuit includes a complementary latch configured to generate and store complementary non-volatile spin states corresponding to an input signal when in a write mode, and to concurrently generate a first charge current signal and a second charge current corresponding to the complementary non-volatile spin states when in read mode, and a differential amplifier coupled to the complementary latch and configured to generate an output signal based on the first and second charge current signals.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: May 31, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Titash Rakshit, Ryan Hatcher, Jorge A. Kittl
  • Driver leakage control
    Patent number: 11342014
    Abstract: Embodiments herein relate to column select circuitry of a memory device. Specifically, the column select circuitry includes a pre-header circuit coupled to a pre-driver circuit. The pre-header circuit is configured to couple a gate of a transistor of a main column select driver circuit of the column select circuitry to a first voltage supply during operation and a second voltage supply when in a standby state. A voltage of the second voltage supply is greater than a voltage of the first voltage supply. The voltage of the second power supply applied to the gate of the transistor of the main column select driver circuit reduces current leakage through the transistor and enables a reduction in a size of the column select circuitry.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: May 24, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Charles L. Ingalls
  • Compute-in-memory (CIM) cell circuits employing capacitive storage circuits for reduced area and CIM bit cell array circuits
    Patent number: 11322199
    Abstract: A CIM bit cell circuit employing a capacitive storage circuit to store a binary weight data as a voltage occupies half or less of the area of a 6T SRAM CIM bit cell circuit, reducing the increase in area incurred in the addition of a CIM bit cell array circuit to an IC. The CIM bit cell circuit includes a capacitive storage circuit that stores binary weight data in a capacitor and generates a product voltage indicating a binary product resulting from a logical AND-based operation of the stored binary weight data and an activation signal. The capacitive storage circuit may include a capacitor and a read access switch or a transistor. The CIM bit cell circuit includes a write access switch to couple a write bit voltage to the capacitive storage circuit. In a CIM bit cell array circuit, the product voltages are summed in a MAC operation.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: May 3, 2022
    Assignee: QUALCOMM Incorporated
    Inventor: Xia Li
  • Three-state programming of memory cells
    Patent number: 11315633
    Abstract: The present disclosure includes apparatuses, methods, and systems for three-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of three possible data states by applying a voltage pulse to the memory cell, determining whether the memory cell snaps back in response to the applied voltage pulse, and applying an additional voltage pulse to the memory cell based on the determination of whether the memory cell snaps back.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: April 26, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Jeremy M. Hirst, Shanky K. Jain, Richard K. Dodge, William A. Melton
  • Data edge jumping method
    Patent number: 11315625
    Abstract: The invention relates to a data edge jumping method, applied to a memory system, wherein the memory system comprises a processor and a memory driven by the processor, and a plurality of groups of data lines are connected between the processor and the memory. The data edge jumping method comprising: coding data output by the processor to enable total current produced by data transmission through each of the plurality of groups of data lines at the same time to be zero; transmitting the coded data through the plurality of groups of data cables, and decoding the data before reaching the memory; and inputting the decoded data into the memory, and enabling the total current produced in the data lines to be close to 0 A, so that electromagnetic interference is hardly produced by signals transmitted through the data lines, and allowance of signal radiation is large enough.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: April 26, 2022
    Assignee: AMLOGIC (SHANGHAI) CO., LTD.
    Inventors: Chuanting Xu, Kun Zhang
  • RRAM voltage compensation
    Patent number: 11309022
    Abstract: A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: April 19, 2022
    Inventors: Chien-An Lai, Chung-Cheng Chou, Yu-Der Chih